KR20100013962A

KR20100013962A - Programming method of nonvolatile memory device

Info

Publication number: KR20100013962A
Application number: KR1020080075726A
Authority: KR
Inventors: 강원경
Original assignee: 주식회사 하이닉스반도체
Priority date: 2008-08-01
Filing date: 2008-08-01
Publication date: 2010-02-10

Abstract

PURPOSE: A programming method of a nonvolatile memory device is provided to complete a program operation according to a result from comparing the number of program fail cells and allowable fail bits by counting the number of fail bits for every program operation and verification operation. CONSTITUTION: A program operation is performed to memory cells(210). Based on a verification voltage, programmed cells among the memory cells are verified(220). As a result of the verification, in case there are the cells programmed to be with voltages lower than the verification voltage, the number of the cells with lower voltage are counted(230). A number of the counted cells and allowable fail bits are compared(240). In case the number of the counted cells are less than or equal to the number of the allowable fail bits, a pass signal is output(260).

Description

Programming method of nonvolatile memory device

The present invention relates to a program method of a nonvolatile memory device.

Recently, there is an increasing demand for a nonvolatile memory device that can be electrically programmed and erased and that does not require a refresh function to rewrite data at regular intervals.

The nonvolatile memory cell is an electric program / eraseable device that performs program and erase operations by changing a threshold voltage of a cell while electrons are moved by a strong electric field applied to a thin oxide film.

The nonvolatile memory device typically includes a memory cell array having cells in which data is stored in a matrix form, and a page buffer for writing a memory to a specific cell of the memory cell array or reading a memory stored in a specific cell. . The page buffer may include a pair of bit lines connected to a specific memory cell, a register for temporarily storing data to be written to the memory cell array, or a register for reading and temporarily storing data of a specific cell from the memory cell array, a voltage of a specific bit line or a specific register. It includes a sensing node for sensing a level, a bit line selection unit for controlling the connection of the specific bit line and the sensing node.

The verification operation of the nonvolatile memory device is performed using whether the program target cell is programmed above the verification voltage. When the incremental step pulse program (ISPP) method is applied, the program operation and the verify operation are repeatedly performed until the programmed target cell is programmed to be greater than or equal to the verify voltage. Typically, the repetition number is limited to a certain number of times, and if there is a cell that is not programmed up to the specific number, the corresponding block is bad-blocked. If the program operation and the verification operation are completed before the specific number of times, there is no big problem. Otherwise, the time required for the program and the verification operation is greatly increased.

On the other hand, since the ECC algorithm is applied to the nonvolatile memory device recently, it is necessary to reduce the time required for the program operation and the verification operation.

The problem to be solved by the present invention according to the above problem is to count the number of fail bits for every program operation and verify operation, non-volatile to complete the program operation when the number of program fail cells is less than or equal to the allowable fail bit number It is to provide a program method of a memory device.

The above-described program method of a nonvolatile memory device of the present invention includes the steps of: performing a program operation on memory cells, verifying whether all of the program target cells of the memory cells are programmed above a verification voltage, and verifying the program target. Counting the number of corresponding cells if there are cells programmed below the verification voltage among the cells, comparing the number of counted cells with the amount of allowable fail bits, and the number of counted cells as a result of the comparison And outputting a pass signal when is less than or equal to the size of the allowed fail bit number.

In addition, the program method of the nonvolatile memory device of the present invention comprises the steps of performing a program operation on the memory cells, verifying whether the program target cell of the memory cells are all programmed above the verification voltage, and the maximum number of program operations Repeating the program step and the verify step, and counting the number of cells in the program target cell if there are cells programmed below the verify voltage as a result of performing the program step and the verify step for the maximum number of program operations. And comparing the number of counted cells and the size of the allowed fail bit, and outputting a pass signal when the number of counted cells is less than or equal to the size of the allowed fail bit. Characterized in that it comprises a step.

In addition, the program method of the nonvolatile memory device of the present invention comprises the steps of performing a program operation on the memory cells, verifying whether the program target cell of the memory cells are all programmed above the verification voltage, and the predetermined threshold value Repeating the program step and the verify step; and counting the number of the corresponding cells when there are cells programmed below the verify voltage among the program target cells as a result of performing the program step and the verify step by the threshold value; And comparing the number of counted cells with the size of the allowed fail bit, and outputting a pass signal when the number of counted cells is less than or equal to the size of the number of allowed fail bits. It is characterized by.

According to the configuration of the present invention described above it is possible to reduce the time required for the program operation and the verification operation. In particular, an ECC algorithm may be used to compare the number of fail bits and the number of allowable fail bits, and thus, the program may be regarded as completed even for cells in which the program is incomplete. In addition, since the number of times of applying the program pulse is relatively small, the disturbance applied to the cells programmed first is reduced, thereby reducing the distribution of the total threshold voltage.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, only these embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

1 is a block diagram illustrating a nonvolatile memory device according to the present invention.

The nonvolatile memory device 100 may include a memory cell array 110, a page buffer unit 120 including a plurality of page buffers, a column address decoder unit 130, a local data line mux unit 140, and a global data line. The mux unit 150 includes a data register 160 and a path determining unit 170.

The memory cell array 110 includes a plurality of memory cells for storing data, word lines for selecting and activating the memory cells, and bit lines for inputting and outputting data of the memory cells. Word lines and a plurality of bit lines are arranged in a matrix form.

The page buffer unit 120 includes page buffers 122, 124, 126, and 128 respectively connected to a pair of bit lines BLe and BLo. Each page buffer includes a latch that stores specific data, and performs a verification operation based on data stored in specific nodes (node122, node124, node126, and node128) of each latch.

The column decoder 130 decodes a column address to determine which memory cell to store externally input data.

The local data line mux unit 140 transmits externally input data to the column decoder unit or transfers data stored in the page buffer to the global data line mux unit 140. In addition, the global data line mux unit 150 transmits externally input data to the local data line mux unit or transfers data transferred from the local data line mux unit to the data register 160. The number of fail bits is counted based on the data output from the global data line mux unit 150.

The pass determining unit 170 includes a fail bit counter 172, an allowable fail bit number storage 174, and a comparator 176. The fail bit counter 172 determines the number of fail bits based on the data output from the global data line mux unit 150. Normally, the verification operation is performed based on the data stored in the specific node (node122 ~ node128) of the latch included in the page buffer. When the data of the corresponding cell is all set to '1', the verification is considered to be completed. If the data is set to '0', the verification is considered to have failed. Since the stored data of each cell is transmitted to the global data line mux unit 150, when the number of cells in which '0' data is stored is counted in a specific node (node122 to node128) of the latch included in the page buffer, all cells The number of fail bits can be counted.

The allowed fail bit number storage 174 stores the number of bits corresponding to the error correction code (ECC) processing capability of the nonvolatile memory device. Recently, in a nonvolatile memory device, data is stored using an ECC algorithm, and error data is corrected using an ECC algorithm at the time of reading. The ECC algorithm is performed through the control unit, and the present invention can be applied only to the nonvolatile memory device in which the ECC algorithm is used. In this case, the processing capability of the ECC algorithm used in the nonvolatile memory device is set in advance according to the processing capability of the processor used in the control unit. For example, if you use an ECC algorithm that can handle n bits of error, you can correct the error through the ECC algorithm when an error of n bits or less occurs, but you cannot use ECC algorithm if more errors occur. Do. The error allowable bit number of this ECC algorithm is used as the allowable fail bit number. That is, when the number of fail bits is less than or equal to the ECC error allowable bits, error correction is possible through the ECC algorithm. Therefore, it is determined that verification is completed for the memory cells including the corresponding cell.

The comparison unit 176 compares the number of fail bits output from the fail bit counter 172 with the number of allowed fail bits stored in the allowable fail bit number storage 174 and outputs a pass signal according to the result. That is, when the number of fail bits output from the fail bit counter 172 is less than or equal to the allowable fail bit number, the process can be processed by the ECC algorithm. do. On the other hand, if the number of fail bits output from the fail bit counter 172 is larger than the allowable fail bit number, it is impossible to process the ECC algorithm. Therefore, a fail means that the programmed cells are not all programmed above the verify voltage. Output the signal.

Now, the program method of the present invention using the nonvolatile memory device will be described.

2 is a flowchart illustrating a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention, and FIG. 3 is a diagram for describing a concept of a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention. .

First, a program operation is performed (step 210).

The program operation count is set to 1 by the initial program operation. In each program operation, the program operation count is increased by one. The program operation is performed in units of pages, and is divided into a program target cell and an erase target cell according to externally input data.

Next, the program operation verifies whether all of the program target cells have completed the program over the verification voltage (step 220).

Since the verification operation uses a conventional verification operation of the nonvolatile memory device, a detailed description of the operation will be omitted. According to the verifying operation, not only the program target cell is programmed above the verify voltage but also the erase target cell, the first data that is the same as the specific node (node122 to node128) of the latch included in each page buffer, for example, ' 1 'is stored. Second data having a level opposite to the first data, for example, '0', is stored only when the cell to be programmed is not programmed above the verify voltage. If all of the first data is stored in the specific node as a result of the verification, the program target cell is regarded as having completed the program over the verification voltage, and the program operation is terminated while outputting a pass signal (step 260).

However, if there is a program target cell not programmed above the verification result, the fail bit counting operation is performed (step 230).

As described with reference to FIG. 1, the result value of the fail bit counting operation is determined according to data stored in a specific node of a latch included in the page buffer. For example, when there are five cells in which the program target cell is not programmed above the verification voltage, the number of fail bits according to the fail bit counting operation is also set to 5.

Next, the size of the fail bit number and the allowable fail bit number is compared, and a pass signal is output accordingly (step 240).

If the number of fail bits is less than or equal to the allowable number of fail bits, processing may be performed using an ECC algorithm. Therefore, the program target cell is regarded as being programmed with a verification voltage or higher, and the program operation is terminated while outputting a pass signal (step 260). ). In step 220, the program operation is completed when there is no fail bit. However, in step 240, a pass signal is output even when the number of fail bits is limited in consideration of the processing capability of the ECC processing algorithm. Therefore, since the program and verify operations need to be repeated until the number of fail bits is less than or equal to the allowable fail bit number, the time required for the program and verify operations is shortened as compared with the case where the verify operation is performed based only on the step 220. can do.

On the other hand, if the number of fail bits is greater than the allowable number of fail bits, it is determined whether the number of program operations performed corresponds to the maximum number of program operations (step 250).

As a result of the determination, if the number of program operations performed in step 210 corresponds to the maximum number of program operations, the memory cell block including the program target cell is bad-blocked (step 254).

That is, even though the program operation is repeated as many times as the maximum number of program operations, if the program is not completed because the verification voltage is greater than or equal to the verification voltage in step 220, or if the number of fail bits is greater than the allowable number of fail bits, the memory cell including the program target cell is included. View the block as a bad block. The memory cell block stores the address of the memory cell block in the control unit of the nonvolatile memory device, and controls to address another good memory cell block when an attempt is made to address the bad block. The maximum number of program operations may be determined according to a designer's choice in consideration of characteristics of memory cells.

If it is determined that the number of program operations is less than the maximum number of program operations, the program voltage is increased by a step voltage (step 252), and the program and verification operations are repeatedly performed.

Referring to FIG. 3, in this embodiment, not only a verify operation but also a fail bit counting operation and a comparison operation between a fail bit number and an allowable fail bit number for each program operation, the program operation is completed with a minimum program and verify operation. You can do that. As illustrated, the program voltage Vm and the verify voltage Vver are alternately applied according to the ISPP program method. At this time, even when the number of program operations (m) is not the maximum number of program operations (Max), the fail bit counting and the allowable fail bit number comparison operations can be performed, and the program operation is terminated before the maximum number of program operations is reached. Can be.

4 is a flowchart illustrating a program method of a nonvolatile memory device according to still another embodiment of the present invention, and FIG. 5 is a view illustrating a concept of a program method of a nonvolatile memory device according to another embodiment of the present invention. Drawing.

First, a program operation is performed (step 410), and the program operation verifies whether all of the program target cells are completed above the verify voltage by the program operation (step 420). Detailed operation is the same as the embodiment of FIG.

If there is a program target cell not programmed above the verification result, it is determined whether the number of times the program operation is performed corresponds to the maximum number of program operations (step 430).

Unlike the embodiment of FIG. 2, the present embodiment performs a fail bit counting operation only when the maximum program operation count is reached. Therefore, the program voltage is increased by the step voltage until the maximum program operation count is reached (step 4322), and the program operation and the verification operation are repeatedly performed (steps 410 and 420).

If the number of times the program operation is performed corresponds to the maximum number of program operations, the fail bit counting operation is performed (step 440). The detailed operation is as described above.

Next, the size of the fail bit number and the allowable fail bit number is compared, and a pass signal is output accordingly (step 450).

If the number of fail bits is less than or equal to the allowable number of fail bits, processing can be performed using an ECC algorithm. Therefore, the program target cell is regarded as programmed above the verify voltage, and the program operation is terminated while outputting a pass signal (step 460). ). In operation 420, the program operation is completed when there is no fail bit. In operation 440, a pass signal is output even when the number of fail bits is limited, in consideration of the processing capability of the ECC processing algorithm. Therefore, the number of memory cell blocks processed as a bad block is reduced as compared with the case of performing the verification operation based only on the step 420. In other words, if the fail bit is smaller than the allowable fail bit, it is determined as a good memory cell block.

On the other hand, if the number of fail bits is larger than the allowed fail bit number, the memory cell block including the program target cell is bad-blocked (step 452).

That is, even though the program operation is repeated as many times as the maximum number of program operations, if the program is not completed because the verification voltage is greater than or equal to the verification voltage in step 220, or if the number of fail bits is greater than the allowable number of fail bits, the memory cell including the program target cell is included. The block will be badblocked. The maximum number of program operations may be determined according to a designer's choice in consideration of characteristics of memory cells.

Referring to FIG. 5, in the present exemplary embodiment, when a program operation and a verify operation are performed by the maximum program operation count (VMAX), a fail bit counting operation and a comparison operation between a fail bit number and an allowable fail bit number are performed. Accordingly, the time required for the fail bit counting operation and the comparison operation between the fail bit number and the allowable fail bit number can be shortened as compared with the embodiment of FIG. 2. In addition, after the maximum number of program operations is reached, the comparison operation between the number of fail bits and the number of allowable fail bits is performed, thereby reducing the number of memory cell blocks considered as bad blocks.

6 is a flowchart illustrating a program method of a nonvolatile memory device according to still another embodiment of the present invention, and FIG. 7 is a diagram for describing a concept of a program method of a nonvolatile memory device according to another embodiment of the present invention. Drawing.

First, a program operation is performed (step 610), and the program operation verifies whether or not the program has been completed by all of the program target cells above the verify voltage (step 620). Detailed operation is the same as the embodiment of FIG.

If there is a program target cell not programmed above the verification result, it is determined whether the number of times the program operation is performed is greater than a predetermined threshold value (step 630).

Unlike the embodiments of FIGS. 2 and 4, the fail bit counting operation is not performed until the number of program operations reaches a predetermined threshold. After repeating the program operation and reaching the predetermined threshold value, every program operation is performed, as well as the verification operation, the fail bit counting operation and the comparison operation between the fail bit number and the allowable fail bit number are performed. An action can cause a program action to complete. Typically, only one or two program operations do not complete the program operation. Therefore, only the program operation and the verify operation are repeated until the threshold is reached. The threshold is determined by the characteristics of the memory cell. That is, the number of fail operations and the number of allowable fail bits are similar to the number of program operations.

If the number of program operations does not reach the threshold as a result of the determination, the program voltage is increased by a step voltage (step 632), and the program and verification operations are repeatedly performed (steps 610 and 620).

Only when the number of program operations reaches a threshold value, a fail bit counting operation and a comparison operation between a fail bit number and an allowable fail bit number are performed for every program operation.

That is, if the number of times the program operation is performed corresponds to the predetermined threshold value i, the fail bit counting operation is performed (step 640). The detailed operation is as described above.

Next, the size of the fail bit number and the allowable fail bit number is compared, and a pass signal is output accordingly (step 650).

If the number of fail bits is less than or equal to the allowable number of fail bits, processing can be performed using an ECC algorithm. Therefore, the program target cell is regarded as programmed above the verify voltage, and the program operation is terminated while outputting a pass signal (step 670). ). In step 620, the program operation is completed when there is no fail bit. In step 650, the pass signal is output even when the number of fail bits is limited in consideration of the processing capability of the ECC processing algorithm.

On the other hand, if the number of fail bits is greater than the allowed fail bit number, it is determined whether the number of times the program operation is performed corresponds to the maximum number of program operations (step 660).

If it is determined that the number of program operations performed in step 610 corresponds to the maximum number of program operations, the memory cell block including the program target cell is bad-blocked (step 662).

That is, even though the program operation is repeated as many times as the maximum number of program operations, if the program is not completed by the verification voltage or more in step 620 or the number of fail bits is larger than the allowable number of fail bits, the memory cell including the program target cell is included. The block will be badblocked. The maximum number of program operations may be determined according to a designer's choice in consideration of characteristics of memory cells.

If it is determined that the number of program operations is less than the maximum number of program operations, the program voltage is increased by a step voltage (step 632), and the program and verification operations are repeatedly performed.

Referring to FIG. 7, in the present exemplary embodiment, a fail bit counting operation and a comparison operation between a fail bit number and an allowable fail bit number are performed for each program operation from the case where the program operation frequency is greater than or equal to the threshold value Vi.

Accordingly, the time required for the fail bit counting operation and the comparison operation between the fail bit number and the allowable fail bit number can be shortened as compared with the embodiment of FIG. 2. In addition, after the maximum number of program operations is reached, the comparison operation between the number of fail bits and the number of allowable fail bits is performed, thereby reducing the number of memory cell blocks considered as bad blocks.

2 is a flowchart illustrating a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

3 is a view for explaining the concept of a program method of a nonvolatile memory device according to an embodiment of the present invention.

4 is a flowchart illustrating a program method of a nonvolatile memory device according to still another embodiment of the present invention.

5 is a diagram for describing a concept of a program method of a nonvolatile memory device according to still another embodiment of the present invention.

6 is a flowchart illustrating a program method of a nonvolatile memory device according to another exemplary embodiment of the present invention.

7 is a view for explaining the concept of a program method of a nonvolatile memory device according to another embodiment of the present invention.

Claims

Performing a program operation on the memory cells;

Verifying whether all of the program target cells of the memory cells have been programmed above a verification voltage;

Counting the number of cells when there are cells programmed below the verification voltage among the cells to be programmed as a result of the verification;

Comparing the number of counted cells with a size of an allowed fail bit;

And outputting a pass signal when the number of counted cells is less than or equal to the number of allowable fail bits as a result of the comparison.

The method of claim 1, wherein the verifying whether all of the program target cells of the memory cells are programmed above a verification voltage is performed.

And outputting a pass signal when all of the cells to be programmed are programmed to be higher than the verification voltage as a result of the verification.

The method of claim 1, further comprising: performing bad block processing if the number of times of performing the program operation is equal to the maximum number of program operations when the number of counted cells is greater than the size of the allowed fail bit, as a result of the comparison. Program method for a nonvolatile memory device, characterized in that.

The method of claim 1, wherein if the number of counted cells is greater than the allowable number of fail bits, the program voltage is increased by repeating the program voltage if the number of times of performing the program operation is smaller than the maximum number of program operations. The method of claim 1, further comprising the step of.

Performing a program operation on the memory cells;

Repeating the program step and the verify step a maximum number of program operations;

Counting the number of corresponding cells when there are cells programmed below the verification voltage among the program target cells as a result of performing the program step and the verify step for the maximum number of program operations;

Comparing the number of counted cells with a size of an allowed fail bit;

And outputting a pass signal when the number of counted cells is less than or equal to the size of the allowable fail bit, as a result of the comparison.

The method of claim 5, wherein the verifying whether all of the program target cells of the memory cells are programmed above a verification voltage is performed.

6. The method of claim 5, further comprising: bad-blocking a memory cell block including the program target cell when the number of counted cells is greater than an allowable number of fail bits. Program method of volatile memory device.

The method of claim 5, wherein the repeating of the program step and the verify step by the maximum number of program operations comprises:

Re-performing the program operation by increasing a program voltage when there are cells programmed below a verification voltage among the program target cells as a result of performing the program step;

Counting the number of times the program operation is performed;

And comparing the number of executions of the counted program operation with the predetermined maximum number of program operations.

Performing a program operation on the memory cells;

Repeating the program step and the verify step by a predetermined threshold value;

Counting the number of the corresponding cells when there are cells programmed below the verification voltage among the program target cells as a result of performing the program step and the verify step by the threshold value;

Comparing the number of counted cells with a size of an allowed fail bit;

The method of claim 9, wherein the verifying whether all of the program target cells of the memory cells are programmed above a verification voltage is performed.

10. The method of claim 9, further comprising: performing a bad block process if the number of times of performing the program operation is equal to the maximum number of program operations when the number of counted cells is greater than an allowable number of fail bits as a result of the comparison. Program method for a nonvolatile memory device, characterized in that.

10. The method of claim 9, wherein if the number of counted cells is greater than the number of allowable fail bits, if the number of times of performing the program operation is less than the maximum number of program operations, the program voltage is repeatedly performed. The method of claim 1, further comprising the step of.

The method of any one of claims 1 to 12, wherein the allowed fail bit number is equal to the error allowed bit number of an error correction code (ECC) algorithm.