KR20100012504A - Method of fabricating semiconductor apparatus - Google Patents

Abstract

A method of manufacturing a semiconductor device according to the present invention includes forming an interlayer insulating film and a hard mask film on a semiconductor substrate on which an active region is defined, and patterning the hard mask film using a gate mask in the cell array, the core, and the peripheral region. After exposing the core and the peripheral region outside the cell array region through a photo process using a cell close mask, the interlayer insulating layer exposed by the patterned hard mask layer is etched to expose a portion of the semiconductor substrate to form a first recess. Exposing only the cell array region through a photo process using a cell open mask, and then etching the interlayer insulating film, the semiconductor substrate, and the insulating insulating film exposed by the patterned hard mask film to form a second recess, and Forming a gate insulating film in the first and second recesses and filling the gate material.

Description

Manufacturing method of semiconductor device {METHOD OF FABRICATING SEMICONDUCTOR APPARATUS}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a highly integrated semiconductor device, and more particularly, to a method for manufacturing a unit cell that operates stably in a highly integrated semiconductor memory device.

In general, a semiconductor is one of a class of materials according to electrical conductivity, and is a material belonging to an intermediate region between conductors and non-conductors. In a pure state, a semiconductor is similar to non-conductor, but the electrical conductivity is increased by the addition of impurities or other operations. Such a semiconductor is used to create a semiconductor device such as a transistor by adding impurities and connecting conductors. A device having various functions made using the semiconductor device is called a semiconductor device. A representative example of such a semiconductor device is a semiconductor memory device.

The semiconductor memory device includes a plurality of unit cells composed of a capacitor and a transistor, and a double capacitor is used to temporarily store data, and a transistor is used to control signals (word lines) by using a property of a semiconductor whose electrical conductivity varies depending on the environment. Correspondingly used to transfer data between the bit line and the capacitor. In addition, the semiconductor memory device may include a core region including circuits for transferring data transferred to a unit cell or sensing and amplifying data output from the unit cell, and connecting the core region to the outside of the semiconductor memory device and used in the semiconductor memory device. Peripheral areas including circuitry for generating voltages, and the like.

As the degree of integration of semiconductor memory devices increases, the size of various internal circuits needs to be reduced. In particular, reducing the area of the cell array that occupies the largest area in the semiconductor memory device is more efficient in increasing the density of the semiconductor memory device relative to other circuits. For this reason, various methods for making a cell array including a unit cell having a size of 6F ² have recently been proposed, including US Patent No. 7,034,408 (Title: Memory device and method of manufacturing a memory device, inventor: Schloesser). Can be. Hereinafter, a characteristic configuration and a manufacturing method of the above-described US patent will be described, and details thereof will be omitted.

In the above-described US patent, a cell transistor is formed as a recess gate in order to prevent short channel effects that may occur as the unit cell is reduced in size. In particular, word lines were embedded in a semiconductor substrate on which active regions were formed and protected by an insulating film, and then bit line contacts were formed between the insulating films or above the insulating films. The word line constituting the gate of the cell transistor included in the unit cell is generally formed at a level higher than the surface of the semiconductor substrate. However, in the above-described US patent, the word line is formed below the surface of the semiconductor substrate to form a bit line. It is easier to make electrical disconnection with bit line contacts connected with Conventionally, when the electrical disconnection between the word line and the bit line is made only through an insulating film, the performance of the semiconductor memory device is deteriorated due to the increase of the leakage current and the decrease of the operating speed due to the parasitic capacitance of the bit line. The word line is buried so that the parasitic capacitance can be greatly reduced while the bit lines and bit line contacts and electrical disconnects become clear.

Referring to the summary of the above-described US patent, instead of forming a recess gate when forming a transistor included in a peripheral region, the gate of the transistor is formed in the same structure as a bit line formed by stacking a plurality of layers of a cell array. . That is, in the aforementioned US patent, a word line including a gate of a cell transistor included in a unit cell is formed using a word line mask, while gate electrodes of transistors in a core and a peripheral circuit are formed in a cell array. A gate electrode is formed by forming a gate electrode by using a mask in forming a line and depositing the same material as a plurality of conductive materials constituting a bit line. Therefore, an alignment error occurs between the word line composed of the gate of the cell transistor and the gate of the transistor formed in the core and the peripheral circuit at the edge of the cell array. Moreover, even if the design rule is reduced, such alignment error is not reduced, which causes a malfunction of the semiconductor memory device.

In order to solve the above-described conventional problems, the present invention includes a region in which a gate electrode of a cell array embedded in a semiconductor substrate and a gate electrode of a transistor having a different structure included in a core connected to the cell array and a peripheral region are formed. A manufacturing method of a semiconductor memory device determined using a gate mask and a semiconductor memory device manufactured accordingly are provided.

The present invention provides a method of forming an insulating insulating layer defining an active region by performing an STI process on a semiconductor substrate, forming an interlayer insulating layer and a hard mask layer on the semiconductor substrate, and a gate mask in a cell array, a core, and a peripheral region. Patterning the hard mask layer using the semiconductor layer; exposing only the core and the peripheral region through a photo process using a cell close mask; and then etching the interlayer insulating layer exposed by the patterned hard mask layer to etch the semiconductor substrate. Exposing a portion and forming a first recess; exposing only the cell array region through a photo process using a cell open mask; and then exposing the interlayer insulating layer, the semiconductor substrate, and the substrate exposed by the patterned hard mask layer. Etching the insulating insulating film to form a second recess, wherein the first and second recesses Forming a gate insulating film and filling the gate material, exposing only the cell array region through a photo process using the cell open mask, and then lowering the gate material lower than the surface of the semiconductor substrate in the cell array region. And forming a gate pattern by forming an upper gate insulating layer on the gate material, thereby forming a gate pattern.

Advantageously, the method of manufacturing a semiconductor memory device comprises forming a sidewall insulating film on sidewalls of the gate pattern in the core and peripheral regions; And forming source / drain regions on both sides of the gate pattern in the core and peripheral regions.

Preferably, the etching depth of the semiconductor substrate and the insulating insulating layer is the same when forming the second recess.

Preferably, the isolation insulating layer is more deeply etched than the semiconductor substrate when the second recess is formed.

Preferably, the thickness of the gate insulating film in the core and the peripheral region is varied.

Preferably, the gate insulating layer is formed to have a different thickness according to the cell array, the core and the peripheral region.

Preferably, the gate insulating film includes any one selected from the group consisting of an oxide film and a nitrided oxide film.

Preferably, when the gate insulating film is formed differently according to the cell array, the core and the peripheral area, the gate insulating film formed on the core and the peripheral area is any one selected from the group consisting of an oxide film, an aluminum oxide film, and a hafnium oxide film. Characterized in that it comprises a.

Preferably, the sidewall insulating film comprises any one selected from the group consisting of an oxide film, a nitride film and an oxynitride film.

Preferably, the gate material comprises any one selected from the group consisting of polycrystalline silicon, tungsten polyside (WSi _x ), TaN, TiN and tungsten (W).

According to the present invention, in the fabrication of transistors having different structures formed in a cell array, a core, and a peripheral region in a semiconductor memory device having a structure in which a word line is buried in a semiconductor substrate, the position of the gate pattern is determined by using a mask. Accordingly, there is an advantage in that the operation stability of the semiconductor memory device can be improved by preventing alignment errors occurring between gate patterns connected between the regions.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

According to the present invention, in manufacturing a semiconductor memory device having a structure in which word lines in a cell array are embedded in a semiconductor substrate, gate patterns of transistors in a core region and a peripheral region outside the cell array and a region in which word lines in the cell array are to be formed The alignment error is eliminated by the photo process using a single gate mask, and the gate patterns of the word lines in the cell array and the transistors in the core region and the peripheral region are fabricated using cell open mask and cell close mask. To be possible.

1A to 1D are plan views illustrating an ISO mask and a gate mask according to an embodiment of the present invention for forming a semiconductor memory device.

1A and 1B illustrate ISO mask patterns 102A and 102B and first and second gate mask patterns 104A and 104B in a cell array according to unit cell sizes. Specifically, FIG. 1A illustrates a case in which a unit cell has a size of 8F ² , and FIG. 1B illustrates a case in which a unit cell has a size of 6F ² . In this case, F means a minimum line width according to a design rule.

In addition, in contrast to the ISO mask patterns 102C and 102D, FIG. 1C illustrates a third gate mask pattern 104C that can define where gate line widths of transistors in the core and the peripheral region of the semiconductor memory device are formed differently. 1D illustrates the fourth gate mask pattern 104D of the transistor having a large line width in the core and the peripheral region.

In the method of manufacturing a semiconductor memory device according to an embodiment of the present invention, various first, second, third, and fourth gate mask patterns 104A or 104B, 104C, and 104D shown in FIGS. It is characterized by being included in the gate mask. As a result, a word line embedded in the cell array corresponding to the first or second gate mask pattern 104A or 104B and a transistor formed in the core region and the peripheral region outside the cell array corresponding to the gate mask patterns 104C and 104D. It is possible to form the gate electrode using one gate mask.

2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention using the gate mask shown in FIGS. 1A to 1D.

Referring to FIG. 2A, an isolation insulating film 202 is formed in the semiconductor substrate 201 by performing a shallow trench isolation (STI) process. The STI process is described in detail as follows. First, a pad oxide film (not shown) and a pad nitride film (not shown) are sequentially stacked on the semiconductor substrate 201 (the oxidation process and the deposition process are performed), and then the etching process using the active mask is performed. A trench is formed in the trench. Then, the insulating insulating film 202 is deposited to fill the trench, followed by chemical mechanical polishing (CMP) to form the insulating insulating film 202 with the trench embedded therein, and then the pad nitride film and the pad oxide film. Remove sequentially.

After the isolation insulating film 202 is formed through the STI process, the buffer insulating film 203 is formed on the exposed semiconductor substrate 201. A photoresist (not shown) is coated on the buffer insulating layer 203, and a photo process using an implant mask is performed to inject wells and channel ions into necessary portions to remove remaining photoresist. Here, in order to form the well and the channel region, the semiconductor substrate 201 is exposed as necessary by using each mask, and then ion implantation is repeatedly performed. Thereafter, a first insulating film 204 is formed on the buffer insulating film 203 and the insulating insulating film 202.

Referring to FIG. 2B, the hard mask film 205 is deposited on the first insulating film 204, and then the second insulating film 206 is deposited on the hard mask film 205. After applying the first photoresist film (not shown) on the second insulating film 206, the photoresist is patterned using a gate mask defining a gate pattern shown in FIGS. 1A to 1D to pattern the first photoresist film, and then the second insulating film ( 206 and the hard mask film 205 are etched. In this case, when the second insulating film 206 and the hard mask film 205 are etched, the first photoresist film remaining on the second insulating film 206 may also be removed.

Referring to FIG. 2C, the third insulating film 207 is coated on the patterned second insulating film 206 and the hard mask film 205 to a predetermined thickness. Subsequently, the second photoresist layer 208 is applied to the entire surface, and then the photoresist using a cell close mask is performed to remove the second photoresist layer 208 in the core region and the peripheral region except the cell array region. After the third insulating layer 207 is removed from the exposed core region and the peripheral region through an isotropic etching process, the first insulating layer 204 exposed between the patterned hard mask layer 205 is etched to form a first recess. . At this time, the second insulating film 206 remaining on the hard mask film 205 is also removed by the etching selectivity in the process of etching the first insulating film 204.

Referring to FIG. 2D, after the photoresist film remaining in the cell array region is removed through wet etching, the third photoresist film 209 is coated on the entire surface. Thereafter, a photo process using a cell open mask is performed to remove the third photoresist layer 209 in the cell array region, and then the exposed third insulating layer 207 is removed through an isotropic etching process.

As shown in FIG. 2E, the first insulating film 204, the buffer insulating film 203, and the semiconductor substrate 201 and the insulating insulating film 202 are formed by using the hard mask film 205 patterned in the cell array region as an etching mask. Is etched to form a second recess. At this time, the semiconductor substrate 201 and the insulating insulating film 202 are etched to the same depth. In addition, the second insulating layer 206 remaining on the hard mask layer 205 in the etching process for forming the recess is removed by an etching selectivity, and a portion of the hard mask layer 205 is etched to reduce the thickness.

Although not shown, after forming the second recess, an ion implantation process may be further performed on the semiconductor substrate 201 to form the channel region, and the chemical dry etching process may be performed to round the lower portion of the second recess. (CDE) process may be further performed.

Referring to FIG. 2F, after removing the third photoresist layer 209 remaining in the core region and the peripheral region, the hard mask layer 205 remaining in the cell array region and the core region and the peripheral region is removed. Thereafter, the fourth insulating film 210 is deposited on the entire surface to a predetermined thickness and dry etching is performed so that the fourth insulating film 210 remains only on the sidewalls of the first and second recesses. At this time, the buffer insulating film 203 exposed between the first insulating film 204 in the core region and the peripheral region is also etched together.

As shown in FIG. 2G, a gate insulating film 211 is formed on the exposed semiconductor substrate 201 in the first and second recesses, and a conductive material is embedded in the first and second recesses so that the gate electrode ( 212). Referring to <X-X '> and <Y-Y'>, in the case of narrow recesses of the cell array in the semiconductor memory device, the recesses are completely filled due to the conductive material, but are shown in <II-II '>. As shown, in the case of a wide gate region, the recess is not completely filled by the conductive material. Since it is not efficient to deposit a thick conductive material to completely fill the wide gate region, the first gate upper insulating layer 213 is deposited so that the recess corresponding to the wide gate region is completely filled. Here, the conductive material constituting the gate electrode 212 includes polycrystalline silicon, tungsten polyside (WSi _x ), TaN, TiN, or tungsten (W).

Referring to FIG. 2H, the gate electrode 212 formed by filling the recess is etched by a predetermined thickness through a first etch-back process. In this case, the first etch back process allows the upper portion of the gate electrode 212 to remain higher than the semiconductor substrate 201. After performing the first etch back process, the exposed first insulating layer 204 and the fourth insulating layer 210 are etched by a predetermined amount through isotropic wet etching to form a recess having a wider width than that of the gate electrode 212. To form.

Referring to FIG. 2I, after the fourth photoresist layer 214 is applied to the cell array region, the entire surface of the core and the peripheral region, the photoresist using a cell open mask is performed to remove the fourth photoresist layer 214 on the cell array region. do. Thereafter, the gate electrode 212 exposed to the cell array region is etched by a predetermined thickness through a secondary etch back process, in which the upper part of the gate electrode 212 is lower than the upper part of the semiconductor substrate 201. To remain. After the second etch back process, the fourth photoresist 214 remaining on the core and the peripheral region is removed.

Referring to FIG. 2J, recesses formed on the gate electrode 212 formed in the cell array region, the core and the peripheral region, that is, the first and second etch back processes and the first insulating layer 204 are wetted. After filling the two-gate upper insulating layer 215, a chemical mechanical polishing process (CMP) is performed to planarize it. At this time, due to the isotropic wet etching performed before the second etch back process, the second gate upper insulating layer 215 is formed on the gate electrode 212 to have a smaller width than the surface of the semiconductor substrate 201, but the semiconductor The width is wider in an area higher than the surface of the substrate 201.

Only the second gate upper insulating layer 215 is formed on the gate electrode 212 in the narrow cell array region of the gate electrode 212, but the gate electrode 212 is positioned on the wide area of the gate electrode 209. In addition to the second gate upper insulating layer 215, a first gate upper insulating layer 213 is formed together. Therefore, in order to ensure uniform characteristics of the transistor in the semiconductor memory device, it is preferable that the first gate upper insulating film 213 and the second gate upper insulating film 215 are made of the same material.

After that, the LDD regions of the cell transistor and the core and the peripheral circuit are formed, and the sidewall insulating layer is formed, and then the source / drain regions are formed. After forming the source / drain regions, a bit line plug for connecting the bit line and the cell transistor and a bit line contact are formed, and a storage node plug for connecting the cell transistor and the capacitor is formed. Thereafter, bit lines and capacitors are formed in the cell array region, and other metal wirings and the like are further formed to manufacture the semiconductor memory device.

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention.

In the method of manufacturing a semiconductor memory device according to another exemplary embodiment of the present invention, the process of forming the isolation insulating film 302 through the STI process in the semiconductor substrate 301 may include the semiconductor substrate 301 and the first insulating film 304 in the cell array region. ) And proceed to the same process as described in Figures 4a to 4e to form a second recess to form a structure as shown in Figure 3a.

Referring to FIG. 3B, the insulating insulating layer 302 is additionally etched in the exposed cell array region so that the semiconductor substrate 301 in the cell array region has a fin structure that protrudes relative to the insulating insulating layer 302. Thereafter, after removing the third photoresist layer 209 remaining in the core region and the peripheral region, the hard mask layer 305 remaining in the cell array region and the core region and the peripheral region is removed. Thereafter, the fourth insulating layer 310 is deposited to a predetermined thickness on the entire surface and dry etching is performed so that the fourth insulating layer 310 remains only on sidewalls of the first and second recesses. Subsequently, the buffer insulating layer 303 exposed between the first insulating layer 304 in the core region and the peripheral region is etched.

Subsequently, as described with reference to FIGS. 2G to 2I, the gate electrode 312 is formed and the first and second gate upper insulating layers 313 and 315 are formed to complete the gate pattern as illustrated in FIG. 3C.

After completion of the gate pattern, the LDD regions of the cell transistor and the core and the peripheral circuit are formed, the sidewall insulating film is formed, the source / drain regions are formed, and as described above, the components required for the semiconductor memory device are sequentially Form.

As described above, in the present invention, the word line in the cell array region is embedded in the semiconductor substrate to reduce parasitic capacitance occurring between the word line and the bit line, thereby improving the operational stability of the semiconductor memory device. By using the gate mask to determine the region in which the gates of the transistors in the cell array region and the core and the peripheral region are to be formed, conventional alignment errors can be prevented. In addition, in the present invention, it is possible to form a transistor having a fin structure by etching the insulating insulating layer exposed in the cell array region more deeply than the semiconductor substrate without an additional photo process.

In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

1A to 1D are plan views illustrating an ISO mask and a gate mask according to an embodiment of the present invention for forming a semiconductor memory device.

2A to 2J are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present invention using the gate mask shown in FIGS. 1A to 1D.

3A to 3C are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present invention.

Claims (10)

Performing an STI process on the semiconductor substrate to form an isolation insulating film defining an active region; Forming an interlayer insulating film and a hard mask film on the semiconductor substrate; Patterning the hard mask layer using a gate mask in a cell array, a core, and a peripheral region; Exposing only the core and the peripheral region through a photo process using a cell close mask, and then etching the interlayer insulating layer exposed by the patterned hard mask layer to expose a portion of the semiconductor substrate and form a first recess. step; Exposing only the cell array region through a photo process using a cell open mask, and then etching the interlayer insulating layer, the semiconductor substrate, and the insulating insulating layer exposed by the patterned hard mask layer to form a second recess. ; Forming a gate insulating film in the first and second recesses and filling a gate material; Exposing only the cell array region through a photo process using the cell open mask and etching the gate material to be lower than the surface of the semiconductor substrate in the cell array region; And Forming a gate pattern by forming a gate upper insulating layer on the gate material A manufacturing method of a semiconductor memory device comprising a. The method of claim 1, Forming a sidewall insulating film on sidewalls of the gate pattern in the core and peripheral regions; And And forming source / drain regions on both sides of the gate pattern in the core and peripheral regions. The method of claim 1, And forming an etching depth between the semiconductor substrate and the insulating insulating layer at the time of forming the second recess. The method of claim 1, And etching the isolation insulating layer more deeply than the semiconductor substrate when the second recess is formed. The method of claim 1, And varying thicknesses of the gate insulating film in the core and in the peripheral region. The method of claim 1, And the gate insulating film is formed to have a different thickness depending on the cell array, the core and the peripheral area. The method of claim 1, And the gate insulating film includes any one selected from the group consisting of an oxide film and a nitrided oxide film. The method of claim 1, When the gate insulating film is formed differently according to the cell array, the core, and the peripheral area, the gate insulating film formed on the core and the peripheral area includes any one selected from the group consisting of an oxide film, an aluminum oxide film, and a hafnium oxide film. A method of manufacturing a semiconductor memory device. The method of claim 1, And the sidewall insulating film includes any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride film. The method of claim 1, Wherein the gate material comprises any one selected from the group consisting of polycrystalline silicon, tungsten polyside (WSi _x ), TaN, TiN, and tungsten (W).

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