KR20090122688A - Clock delay circuit - Google Patents

Abstract

The present invention relates to a clock delay circuit, comprising: a first logic combination section for inverting an input signal and outputting it as a first output signal while the clock signal is at a first level; A second logic combination unit for inverting the clock signal and outputting the second and third output signals while the first output signal is at a second level; A third logic combiner for inverting the second output signal while the clock signal is at a second level and outputting the input signal and the fourth output signal input to the first logic combiner; And a delay signal output unit configured to logically combine the third and fourth output signals to output a delay clock signal having a period greater than that of the clock signal.

Description

Clock delay circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock delay circuit, and more particularly, to a clock delay circuit that can be implemented in a small size by changing elements constituting the circuit.

Proper voltage supply is required for correct operation of memory circuits and various integrated circuits (ICs). In particular, when a high voltage is required for these circuits, a pump circuit that operates in response to the clock signal CLK is used. The frequency and width of the clock signal CLK are adjusted according to the magnitude of the voltage to be generated. The frequency of the clock signal CLK is adjusted through a clock delay circuit including a plurality of logic gates.

Such clock delay circuits are typically constructed using inverters and flip-flops. In particular, the flip-flop circuit is a circuit used for temporarily preserving or delaying data, and the area is large by using a reset-set (RS) latch.

As the area of the clock delay circuit increases, it means that the total circuit area of the memory circuit or the IC in which the clock delay circuit is necessary is increased.

1 is a block diagram of a clock delay circuit.

Referring to FIG. 1, a clock delay circuit includes first and second inverters IN1 and IN2 and a clock delay unit 100.

The first inverter IN1 inverts the input clock CLK. The output signal of the first inverter IN1 is input to the first input terminal CP of the clock delay unit 100. The signal input to the first input terminal CP is internally delayed for a predetermined time and then output to the output terminal Q.

The second inverter IN2 inverts and outputs the signal output from the output terminal Q of the clock delay unit 100. The second inverter IN2 is the delay clock signal CLK_D.

The delay clock unit 100 includes an RS (Reset-Set) flip-flop circuit in order to delay and output the signal input to the first input terminal (CP) for a predetermined time. Such a flip-flop circuit makes the area of the entire clock delay circuit large.

Accordingly, an aspect of the present invention is to provide a clock delay circuit that can reduce an area by using a transistor that occupies a smaller area than a flip-flop or an inverter.

A clock delay circuit according to a feature of the invention,

A first logic combination unit for inverting the input signal and outputting the first output signal as the first output signal while the clock signal is at the first level; A second logic combination unit for inverting the clock signal and outputting the second and third output signals while the first output signal is at a second level; A third logic combiner for inverting the second output signal while the clock signal is at a second level and outputting the input signal and the fourth output signal input to the first logic combiner; And a delay signal output unit configured to logically combine the third and fourth output signals to output a delay clock signal having a period greater than that of the clock signal.

In the second logic combination unit, the second output signal is output by holding a pulled up or pulled up state according to the clock signal while the first output signal is at a first level, and the first output signal is output to the second output signal. The inverted signal of the clock signal is output while the level is low, and the third output signal is output by holding a pulled down or pulled down state according to a clock signal while the first output signal is in the first level. The inverted signal of the clock signal is output while the output signal is at the second level.

In the third logic combination unit, the input signal is maintained in an output state or pulled down or maintains a pull-down state in accordance with the clock signal while the second output signal is at a first level. During the second level, the output signal is pulled up according to the clock signal, and the fourth output signal is the same as the inverted signal of the second output signal.

The delay clock signal is characterized in that the same as the inverted signal of the first output signal.

The delay signal output unit may include a NOR gate.

The first level is a low level, the second level is characterized in that the high level.

The first logic combiner includes first and second transistors of a first type and a third transistor of a second type opposite to the transistor of the first type, wherein the first to third transistors are power supply voltage nodes. And is connected in series between the ground node.

The input signal is input to the gates of the first and third transistors, the clock signal is input to the gates of the second transistor, and the first output signal is output from the contacts of the second and third transistors. It is done.

The second logic combination portion includes a fourth transistor of the first type and fifth and sixth transistors of the second type, wherein the fourth to sixth transistors are connected in series between a power supply node and a ground node. It is characterized in that the connection.

The clock signal is input to the gates of the fourth and sixth transistors, the first output signal is input to the gate of the fifth transistor, and the second output signal is input from the contacts of the fourth and fifth transistors. And the third output signal is output from the contacts of the fifth and sixth transistors.

The third logic combiner includes a seventh transistor of the first type and eighth and ninth transistors of the second type, wherein the seventh to ninth transistors are connected in series between a power supply node and a ground node. It is characterized in that the connection.

The second output signal is input to the gates of the seventh and ninth transistors, the clock signal is input to the gate of the eighth transistor, and the input signal is output from the contacts of the seventh and eighth transistors. And the fourth output signal is output from the contacts of the eighth and ninth transistors.

As described above, the clock delay circuit according to the present invention can reduce the total area by using transistors to implement the circuit configuration, which includes a flip-flop or an inverter and occupies a large area.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and only the present embodiments are intended to make the disclosure of the present invention complete and to those skilled in the art. It is provided for complete information.

2A is a block diagram of a clock delay circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 2A, the clock delay circuit 200 according to an embodiment of the present invention includes first to third logic combination units 210 to 230 and a delay signal output unit 240.

The first to third logic combination units 210 to 230 respectively invert and output the input signal according to the clock signal CLK. The delay signal output unit 240 logically combines the output signals of the second and third logic combination units 220 and 230 and outputs the delayed clock signal CLK_D.

FIG. 2B is a detailed circuit diagram of FIG. 2A.

Referring to FIG. 2B, the first logic combiner 210 includes first and second PMOS transistors P1 and P2 and a first NMOS transistor N1, and the second logic combiner 220 includes a third transistor. PMOS transistor P3 and second and third NMOS transistors N2 and N3.

The third logic combiner 230 includes a fourth PMOS transistor P4 and fourth and fifth NMOS transistors N4 and N5, and the delay signal output unit 240 includes a NOR gate NOR.

In the first logic combination unit 210, the first and second PMOS transistors P1 and P2 and the first NMOS transistor N1 are connected in series between a power supply node and a ground node. The third signal C output from the third logic combination unit 230 is input to the gates of the first PMOS transistor P1 and the first NMOS transistor N1.

The clock signal CLK is input to the gate of the second PMOS transistor P2. The node K1, which is a contact point of the second PMOS transistor P2 and the first NMOS transistor N1, is input to the second logic combination unit 220.

In the second logic combination unit 220, the third PMOS transistor P3 and the second and third NMOS transistors N2 and N3 are connected in series between a power supply voltage node and a ground node. The clock signal CLK is input to the gates of the third PMOS transistor P3 and the third NMOS transistor N3.

The node K1 of the first logic combination unit 210 is connected to the gate of the second NMOS transistor N2. The node K2, which is a contact point of the third PMOS transistor P3 and the second NMOS transistor N2, is connected to the third logic combination unit 230. The first signal A is output from the node K3, which is a contact point of the second NMOS transistor N2 and the third NMOS transistor N3.

The fourth PMOS transistor P4 and the fourth and fifth NMOS transistors N4 and N5 of the third logic combination unit 230 are connected in series between the power supply voltage node and the ground node. The node K2 of the second logic combination unit 220 is connected to the gates of the fourth PMOS transistor P4 and the fifth NMOS transistor N5.

The clock signal CLK is input to the gate of the fourth NMOS transistor N4. The second signal B is output from the node K5, which is a contact point of the fourth NMOS transistor N4 and the fifth NMOS transistor N5, and the contact point of the fourth PMOS transistor P4 and the fourth NMOS transistor N4. The third signal C is output from the in node K4.

The second and third signals B and C are respectively input to the NOR gate NOR. The NOR gate NOR performs a NOR operation on the second and third signals B and C and outputs the delayed clock signal CLK_D.

The operation of the clock delay circuit 200 will be described with reference to the following timing diagram.

3 is a timing diagram for describing an operation of FIG. 2B.

Referring to FIG. 3, each operation will be described according to the time when the clock signal CLK is changed. That is, each of the first to fourth sections T1 to T4 will be described.

At this time, the node K1 is initially set to the low level by the input of the power-on reset signal, the first signal A is set to the low level, and the third control signal C is set to the high level. When the node K1 is at the low level, the second NMOS transistor N2 is turned off. When the third signal C is at the high level, the first NMOS transistor N1 is turned on.

When the clock signal CLK is input at the low level in the first period T1, the second and third PMOS transistors P2 and P3 are turned on. When the third PMOS transistor P3 is turned on, the node K2 is at a high level. When the node K2 is at the high level, the fifth NMOS transistor N5 is turned on. Therefore, the second signal B is at a low level.

In the first period T1, the first signal A is at a low level, and the second signal B is at a low level. Therefore, the delay clock signal CLK_D output from the NOR gate NOR is at a high level.

Next, the second PMOS transistor P2 is turned off in the second period T2 at which the clock signal CLK is at a high level. In this case, since the third signal C is at the high level in the first period T1, the first NMOS transistor N1 is turned on. Therefore, the node K1 is maintained at a low level.

The third and fourth NMOS transistors N3 and N4 are turned on by the high level clock signal CLK. When the third NMOS transistor N3 is turned on, since the node K3 is connected to the ground node, the first signal A is maintained at a low level. When the fourth NMOS transistor N4 is turned on, the third signal C is changed to the low level.

In the second period T2, both the first signal A and the second signal B are at a low level, and the NOR gate NOR outputs a high level delay clock signal CLK_D.

In the third section T3, the clock signal CLK is changed to the low level. When the clock signal CLK is at the low level, the second and third PMOS transistors PP2 and P3 are turned on. At this time, since the third signal C was at the low level in the second period T2, the first PMOS transistor P1 is turned on. Therefore, the first and second PMOS transistors P1 and P2 are turned on, and the node K1 is at a high level.

When the node K1 is at a high level, the second NMOS transistor N2 is turned on. Accordingly, the third PMOS transistor P3 and the second NMOS transistor N2 are turned on so that the node K2 and the first signal A are both at a high level.

The fifth NMOS transistor N5 is turned on while the node K2 is at a high level. The fourth NMOS transistor N4 is turned on by the clock signal CLK. Therefore, the low level state of the third signal C is maintained in the second period C.

In the third section T3, the first signal A is at a high level and the second signal B is at a low level. Therefore, the NOR gate NOR outputs a low level delay clock signal CLK_D.

Finally, in the fourth period T4, the clock signal CLK is changed back to the high level. When the clock signal CLK is at the high level, the third and fourth NMOS transistors N3 and N4 are turned on.

Since the third signal C is at the low level in the third period T3, the first PMOS transistor P1 is turned on and the first NMOS transistor N1 is turned off. Therefore, the node K1, which was at the high level in the third section T3, is maintained at the high level.

When the node K1 is at a high level, the second NMOS transistor N2 is turned on. When the third NMOS transistor N3 is turned on by the clock signal CLK, the node K2 and the first signal A become a low level.

When the node K2 is at the low level, the fourth PMOS transistor P4 is turned on. When the fourth NMOS transistor N4 is turned on by the clock signal, the second and third signals B and C are at a high level.

In the fourth period T4, the first signal A is at a low level and the second signal B is at a high level. Therefore, the NOR gate NOR outputs a low level signal to the delay clock signal CLK_D.

As described above, while the node K1 and the clock signal CLK of the first logic combiner 210 are input at the high level, the node K2 of the second logic combiner 220 is made low. A signal obtained by logically multiplying the signals of the node K1 of the first logical combining unit 210 and the node K2 of the second logical combining unit 220 is output as the first signal A. FIG.

A signal obtained by inverting the signal of the node K2 of the second logic combiner 220 is the second signal B of the third logic combiner 230, and the third signal ( A signal having the same level as the output of C) is output as the second signal B. FIG.

While the clock signal CLK is at the low level, the third signal C is maintained without changing the level.

The node K1 of the first logic combiner 210 changes its logic level at the falling edge of the clock signal CLK, and the third signal C of the third logic combiner 230 is the clock signal CLK. The logic level changes at the rising edge of. The delay clock signal CLK_D is a waveform inverted from the node K1 while changing at the falling edge of the clock signal CLK.

4A and 4B are waveform diagrams obtained through actual simulation of a clock delay circuit according to an embodiment of the present invention.

4A shows waveforms of the first and second signals A and B, and FIG. 4B shows the clock signal CLK and the delay clock signal CLK_D. Thus, the clock delay circuit can be configured by using a transistor having a smaller area than the logic gate.

As described above, the logic gate may include only one NOR gate NOR, and the rest may implement the clock delay circuit 200 using transistors that occupy a smaller area than the logic gate to output the delay clock signal CLK_D.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram of a clock delay circuit.

2A is a block diagram of a clock delay circuit according to an exemplary embodiment of the present invention.

FIG. 2B is a detailed circuit diagram of FIG. 2A.

3 is a timing diagram for describing an operation of FIG. 2B.

4A and 4B are waveform diagrams obtained through actual simulation of a clock delay circuit according to an embodiment of the present invention.

* Brief description of the main parts of the drawings *

200: clock delay circuit

210 to 230: first to third logical combination portion

240: delay signal output unit

Claims (12)

A first logic combination unit for inverting the input signal and outputting the first output signal as the first output signal while the clock signal is at the first level; A second logic combination unit for inverting the clock signal and outputting the second and third output signals while the first output signal is at a second level; A third logic combiner for inverting the second output signal while the clock signal is at a second level and outputting the input signal and the fourth output signal input to the first logic combiner; And A delay signal output unit configured to logically combine the third and fourth output signals to output a delay clock signal having a period greater than the clock signal; Clock delay circuit comprising a. The method of claim 1, In the second logic combination portion, The second output signal is output by holding a pulled up or pulled up state according to the clock signal while the first output signal is at a first level, and inverting the clock signal while the first output signal is at a second level. Output the signal, The third output signal is output by holding a pulled down or pulled down state according to a clock signal while the first output signal is a first level, and inverting the clock signal while the first output signal is a second level. A clock delay circuit comprising a signal output. The method of claim 1, In the third logic combination section, The input signal maintains an output state, pulls down or maintains a pull-down state according to the clock signal while the second output signal is at a first level, and applies the clock signal while the second output signal is at a second level. Therefore, the output is pulled up. And the fourth output signal is the same as the inverted signal of the second output signal. The method of claim 1, And the delay clock signal is the same as the inverted signal of the first output signal. The method of claim 1, And the delay signal output unit includes a NOR gate. The method of claim 1, Wherein the first level is a low level and the second level is a high level. The method of claim 1, The first logical combination portion, First and second transistors of a first type and a third transistor of a second type opposite to the first type of transistor, And the first to third transistors are connected in series between a power supply voltage node and a ground node. The method of claim 7, wherein The input signal is input to gates of the first and third transistors, and the clock signal is input to gates of the second transistor. And the first output signal is output from the contacts of the second and third transistors. The method of claim 7, wherein The second logical combination portion, And a fourth transistor of the first type and fifth and sixth transistors of the second type, wherein the fourth to sixth transistors are connected in series between a power supply voltage node and a ground node. Clock delay circuit. The method of claim 9, The clock signal is input to the gates of the fourth and sixth transistors, the first output signal is input to the gate of the fifth transistor, And the second output signal is output from the contacts of the fourth and fifth transistors, and the third output signal is output from the contacts of the fifth and sixth transistors. The method of claim 9, The third logic combination portion, A seventh transistor of the first type and eighth and ninth transistors of the second type, wherein the seventh to ninth transistors are connected in series between a power supply node and a ground node; Delay circuit. The method of claim 11, The second output signal is input to the gates of the seventh and ninth transistors, the clock signal is input to the gates of the eighth transistors, And the input signal is output from the contacts of the seventh and eighth transistors, and the fourth output signal is output from the contacts of the eighth and ninth transistors.

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