KR20090117172A - Memory device and memory data read method - Google Patents

Abstract

PURPOSE: A memory device and a memory data reading method for MLC and MBC are provided to reduce time for search reading voltage level and read from the memory device by using writing voltage level. CONSTITUTION: A memory device(100) includes a memory cell array(110), a reading unit(120), and a controller(130). The memory cell array includes memory cells. The reading unit reads data from the memory cell array and uses the first reading voltage level. The reading unit produces the first index information based on data. The controller reads the second index information stored in the memory cell array.

Description

How to read memory device and memory data {MEMORY DEVICE AND MEMORY DATA READ METHOD}

The present invention relates to a method of reading data of a memory device, and more particularly, to an apparatus and method of reading data of a multi-level cell (MLC) or a multi-bit cell (MBC) memory device. It is about.

Single-level cell (SLC) memory is a memory that stores one bit of data in one memory cell. Single level cell memory is also referred to as single-bit cell (SBC) memory. The process of storing data in a memory cell (single level cell) of a single level cell memory is also called a program process and may change a threshold voltage of the memory cell. For example, when data of logic "1" is stored in a single level cell, the single level cell may have a threshold voltage of 1.0 Volt. In case of data of logic "0", the single level cell has a threshold of 3.0 Volt. May have a voltage.

Due to the difference in minute electrical characteristics between the single level cells, the threshold voltage formed in each of the single level cells in which the same data is programmed has a range of distribution. For example, if the voltage read from the memory cell is 0.5-1.5 Volt, the data stored in the memory cell is logic " 1 ", and if the voltage read from the memory cell is 2.5-3.5 Volt, the data stored in the memory cell The data can be determined as logic "0". Data stored in the memory cell is distinguished by a difference in current / voltage of the memory cell during a read operation.

Meanwhile, a multi-level cell (MLC) memory capable of programming two or more bits of data in one memory cell has been proposed in response to a demand for high integration of memory. Multi-level cell memory is also called multi-bit cell (MBC) memory. However, as the number of bits programmed into one memory cell increases, the reliability decreases, and the read failure rate increases. In order to program m bits in one memory cell, any one of 2 ^m threshold voltages must be formed in the memory cell. Due to the difference in minute electrical characteristics between the memory cells, the threshold voltages of the memory cells in which the same data is programmed may form a range of distribution. In this case, one threshold voltage distribution may correspond to each of the 2 ^m data values that may be generated by the m bits.

However, because the voltage window of the memory is limited, the distance between 2 ^m dispersions of the threshold voltage between adjacent bits decreases as m increases, and if the distance between the dispersions further decreases, May overlap. Overlapping spreads can increase the read failure rate.

According to embodiments of the present invention, the time for searching for the optimal read voltage level can be shortened, and data can be read from the memory device using the optimal read voltage level.

In an embodiment, a memory device may include a memory cell array including a plurality of memory cells, read data from the memory cell array using a first read voltage level, and read first index information based on the read data. A generating unit and a control unit which reads second index information stored in the memory cell array and determines whether to generate a second read voltage level based on a comparison result of the first index information and the second index information. It may include.

According to another aspect of the present invention, a method of reading memory data may include reading data from a memory cell array using a first read voltage level, generating first index information based on the read data, and writing to the memory cell array. Reading stored second index information, comparing the first index information and the second index information, and determining whether to generate a second read voltage level based on the comparison result. have.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited or limited by the embodiments. Like reference numerals in the drawings denote like elements.

1 is a diagram illustrating a memory device 100 according to an embodiment of the present invention.

Referring to FIG. 1, the memory device 100 may include a memory cell array 110, a reader 120, and a controller 130.

The memory cell array 110 includes a plurality of memory cells. The memory cell array 110 may store data and second index information. The second index information may include management information about the data.

The read unit 120 reads data from the memory cell array 110 using the first read voltage level. The reader 120 generates first index information based on the read data.

The read unit 120 may compare the threshold voltage of the memory cell in which the data is stored in the memory cell array 110 with the first read voltage level. The read unit 120 may determine that data stored in the memory cell having the threshold voltage higher than the first read voltage level is "0", and read data stored in the memory cell having the threshold voltage lower than the first read voltage level. 1 "can be determined.

The controller 130 reads the second index information stored in the memory cell array 110. The controller 130 determines whether to generate a second read voltage level based on a comparison result of the first index information and the second index information.

If the difference between the first index information and the second index information is greater than or equal to the reference value, the controller 130 may generate a second read voltage level based on the difference between the first index information and the second index information. The reader 120 may read data from the memory cell array 110 again using the generated second read voltage level. The reader 120 may update the data using the read back data. The reader 120 may update first index information based on the updated data. The controller 130 may determine whether to generate the third read voltage level based on the comparison result of the updated first index information and the second index information.

The memory device 100 may adjust the read voltage level until the difference between the updated first index information and the second index information is less than a reference value. The memory device 100 may read data again using the adjusted read voltage level until the difference between the updated first index information and the second index information is less than a reference value, and update the first index information.

The memory device 100 may search for a read voltage level such that a difference between the first index information generated based on the read data and the second index information stored in the memory cell array 110 is less than a reference value.

The searched read voltage level may be an ideal read voltage level such that first index information that is about the same or substantially similar to the second index information is generated. The memory device 100 may shorten the time required to search for an ideal read voltage level.

The controller 130 may control the reader 120 to output the read data when the difference between the first index information and the second index information is less than the reference value.

The read unit 120 may calculate the number of memory cells having a threshold voltage higher than the first read voltage level, and generate the calculated number of memory cells as first index information. If the first index information is greater than the second index information, the controller 130 may set a voltage level higher than the first read voltage level as the second read voltage level. If the first index information is smaller than the second index information, the controller 130 may set a voltage level lower than the first read voltage level as the second read voltage level.

According to another exemplary embodiment, the reader 120 may generate the number of memory cells having a threshold voltage lower than the first read voltage level as first index information. In this case, when the first index information is greater than the second index information, the controller 130 may set a voltage level lower than the first read voltage level as the second read voltage level.

2 is a diagram illustrating a memory device 200 according to another embodiment of the present invention.

2, the memory device 200 includes a memory cell array 210, a reader 220, and a controller 230, an error control code or error control coding (ECC) decoder 240, and a programming unit. 250 may further include.

The memory cell array 210 may include a data storage 211 in which data is stored and an index storage 212 in which second index information is stored.

The programming unit 250 may program data into the data storage unit 211, and program second index information corresponding to the data into the index storage unit 212.

The process of storing data by changing the threshold voltage of the memory cell is also called programming. The programming unit 250 may set a target threshold voltage section of the memory cell based on data to be stored in the memory cell. The programming unit 250 may change the threshold voltage of the memory cell such that the threshold voltage of the memory cell is included in the set target threshold voltage section.

For example, the programming unit 250 may set a target threshold voltage range of 1 volt or more and 2 volt or less for the memory cell in which the data “1” is to be stored, and 3 volt or more for the memory cell in which the data “0” is to be stored. You can set the target threshold voltage range below 4 volts.

The programming unit 250 may change the threshold voltage of the memory cell in which the data “1” is to be stored such that the threshold voltage of the memory cell in which the data “1” is to be stored is included in a target threshold voltage section of 1 volt or more and 2 volt or less. The programming unit 250 may change the threshold voltage of the memory cell in which the data “0” is to be stored so that the threshold voltage of the memory cell in which the data “0” is to be stored is included in a target threshold voltage section of 3 volts to 4 volts.

In some example embodiments, the programming unit 250 may change the threshold voltage of the memory cell by comparison with the verify voltage. The programming unit 250 may set a verify voltage for the memory cell based on data to be stored in the memory cell.

For example, the programming unit 250 may set a verify voltage of 1 volt for a memory cell in which data "1" is to be stored, and set a verify voltage of 3 volt for a memory cell in which data "0" is to be stored. . The programming unit 250 may change the threshold voltage of the memory cell in which the data “1” is to be stored such that the memory cell in which the data “1” is to be stored has a threshold voltage higher than the verify voltage of 1 volt. The programming unit 250 may change the threshold voltage of the memory cell in which the data “0” is to be stored so that the memory cell in which the data “0” is to be stored has a threshold voltage higher than the verify voltage of 3 volts.

The programming unit 250 may apply a condition voltage to the memory cell to change the threshold voltage of the memory cell for a predetermined time period. The programming unit 250 compares the threshold voltage of the memory cell with a verify voltage or a target threshold voltage section after a predetermined time interval, and when the threshold voltage of the memory cell is higher than the verify voltage or included in the target threshold voltage section. The threshold voltage change for the cell can be stopped.

The memory cells of the memory devices 100 and 200 that store data according to the change of the threshold voltage may include a control gate (CG) and a floating gate (FG), and an insulator (CG and FG) may be formed between the memory cells. An insulator may be inserted, and an insulator may be inserted between the FG and the substrate.

The program process of storing data in the memory cell or the process of erasing data stored in the memory cell may be performed by a hot carrier effect (HCE) or Fowler-Nordheim Tunneling (FN tunneling) mechanism. Can be.

Under certain bias conditions, a channel may be formed in the region closest to the FG in the substrate region. A channel is an area in which minority carriers of a substrate area are densely formed. The memory devices 100 and 200 control these minority carriers to program data in a memory cell or erase data stored in the memory cell. can do.

When specific bias is applied to the source, drain and CG of the substrate region, minority carriers in the channel may move to the FG. Representative mechanisms by which minority carriers in the channel move to the FG include HCE and F-N tunneling.

The read unit 220 may read data from the data storage unit 211 using a read voltage level and generate first index information based on the read data.

The first index information may be the number of memory cells having a threshold voltage higher than a read voltage level among the memory cells of the data storage 211.

The controller 230 may read the second index information stored in the index storage 212 and compare the first index information with the second index information. The controller 230 may adjust the read level voltage until the same first index information as the second index information stored in the index storage 212 is generated from the read data. The controller 230 may search for an optimal read level voltage capable of obtaining first index information that is the same as or very similar to the second index information.

An error control code or error control coding (ECC) decoder 240 may decode the read data and generate output data. The process of generating a codeword by adding redundant information to a message is called ECC encoding, and the process of separating a message and surplus information from a codeword is called ECC decoding. can do.

The ECC decoder 240 may divide the read data into a plurality of codewords, and decode each of the codewords to separate a message. For example, if the read data is 1000 bits, the ECC decoder 240 may divide the read data into ten 100 bit codewords. If the ratio of message to surplus information is 80 to 20, the ECC decoder 240 may separate the 80 bit message and the 20 bit surplus information from each codeword. The ECC decoder 240 may combine the separated messages to generate output data.

The larger the ratio of (redundant information / message), the greater the number of errors that the ECC decoder 240 can correct. Depending on the type of ECC decoder 240, an error correcting capability may be explicitly revealed. ECCs, in which error correction capabilities are explicitly revealed, include block codes. Examples of block codes are BCH (Bose, Ray-Chaudhuri, Hocquenghem) code or Reed-Solomon code. Decoding techniques, Euclid decoding techniques, and the like. If the number of errors included in the codeword is less than the error correction capability, the ECC decoder 240 may correct all the errors included in the codeword.

In some embodiments, an ECC decoding technique may be used in which the error correction capability of the ECC decoder 240 is not explicitly revealed. If the error rate of the input codeword of the ECC decoder 240 is less than or equal to the threshold value, the error rate of the output message of the ECC decoder 240 may be significantly reduced. In this case, the threshold may be referred to as an error correcting range.

The controller 230 may set the reference value based on the error correction capability of the ECC decoder 240. The controller 230 may generate a second read voltage level when a difference between the first index information and the second index information is greater than or equal to the reference value. According to an embodiment, the controller 230 may set the reference value based on the error correction range of the ECC decoder 240.

The memory device 200 may shorten the time for searching for the optimal read voltage level by setting the reference value based on the error correction capability or the error correction range of the ECC decoder 240. The read data may include an error corresponding to a difference between the first index information and the second index information. If the difference between the first index information and the second index information is less than the reference value, the ECC decoder 240 corrects all of the errors of the read data (when the error correction capability is explicitly revealed) or notifies the error rate of the read data. Can be reduced (if the error correction capability is not explicitly revealed).

3 is a diagram illustrating a memory device 300 according to another exemplary embodiment of the present invention.

Referring to FIG. 3, the memory device 300 may include a memory cell array 310, a reader 320, and a controller 330, and may further include a page buffer 340 and a code memory 350. .

The memory cell array 310 includes a plurality of memory cells, and the read unit 320 reads data from the memory cell array 310 using a read voltage level. The read unit 320 generates first index information based on the read data.

The controller 330 reads the second index information stored in the memory cell array 310 and compares the first index information with the second index information.

The page buffer 340 may store the read data. The controller 330 may determine whether to output data stored in the page buffer 340 based on a result of comparing the first index information and the second index information.

If the first index information is equal to the second index information, the controller 330 may consider that the read data has no error and may control the page buffer 340 to output data stored in the page buffer 340.

If the first index information is different from the second index information, the controller 330 may regard the read data as having an error and may control the page buffer 340 not to output data stored in the page buffer 340. .

According to an exemplary embodiment, if the first index information is very similar to the second index information, the controller 330 may consider that the read data has very few errors. In this case, the controller 330 may control the page buffer 340 to output data stored in the page buffer 340 when a difference between the first index information and the second index information is equal to or less than a reference value.

According to an exemplary embodiment, a set of memory cells that are simultaneously accessed by the reader 320 may be referred to as a page. In this case, the page buffer 340 may store data to be programmed in the page, and maintain the stored data while a programming operation is performed. The page buffer 340 may store data read from memory cells included in a page, and output the stored data according to a command of the controller 330.

The code memory 350 may store a read voltage level code. The read voltage level may be generated by a digital to analog converter (DAC). The DAC can generate analog voltage levels corresponding to digital values. For example, the DAC may generate 256 analog voltage levels using an 8 bit digital value, and the read voltage level may be any one of the 256 analog voltage levels. The read voltage level code may be a digital value corresponding to the read voltage level.

If the first index information is equal to the second index information, the controller 330 may set the current read voltage level to an optimal read voltage level. In this case, the controller 330 may store the read voltage level code corresponding to the current read voltage level in the code memory 350.

According to an exemplary embodiment, if the first index information is very similar to the second index information, the controller 330 may set the current read voltage level to an optimal read voltage level. At this time, if the difference between the first index information and the second index information is less than the reference value, the controller 330 may set the current read voltage level to an optimal read voltage level.

If the first index information is different from the second index information, the controller 330 may generate a new read voltage level by adjusting the current read voltage level. The memory device 300 may search for an optimal read voltage level by adjusting the read voltage level until the first index information is equal to the second index information.

The code memory 350 may store a read voltage level code corresponding to the optimal read voltage level searched by the controller 330.

In some embodiments, the controller 330 may search for an optimal read voltage level for each of the memory cells of the memory cell array 310. In this case, the code memory 350 may store a read voltage level code corresponding to an optimal read voltage level for each of the memory cells of the memory cell array 310.

In some embodiments, the controller 330 may search for an optimal read voltage level for memory cells connected to each of the word lines. In this case, the code memory 350 may store a read voltage level code corresponding to an optimal read voltage level for each of the word lines. The memory device 300 may set a set of memory cells connected to one word line as a page. The memory device 300 may simultaneously perform programming operations on memory cells included in a page, and simultaneously read data from memory cells included in the page.

According to an exemplary embodiment, the controller 330 may search for an optimal read voltage level for memory cells included in each of the blocks in the memory cell array 310. In this case, the code memory 350 may store a read voltage level code corresponding to an optimal read voltage level for each of the blocks. The memory device 300 may simultaneously perform an erase operation on memory cells included in one block.

The memory device 300 may set a read voltage level corresponding to a read voltage level code stored in the code memory 350 as a default read voltage level. The memory device 300 may perform an initial read operation using a default read voltage level while performing a data read operation on new memory cells.

4 is a diagram illustrating an example of an operation of the memory device 100 of FIG. 1.

Referring to FIG. 4, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells having the threshold voltage.

Threshold voltages of memory cells that store the same data may be included in a threshold voltage section of a predetermined range. Threshold voltages of memory cells in which the same data are stored may form a distribution in a range.

Threshold voltages of memory cells in which data A is stored may form a distribution 410.

Threshold voltages of memory cells in which data B is stored may form a distribution 420.

Data A and data B may be m (m is a positive integer) bits of data. For example, data A may be two bit data "10" and data B may be two bit data "00".

It is assumed that a threshold voltage of memory cells in which data B is stored changes with time to form a distribution 430. Assume that the number of memory cells corresponding to spread 430 is equal to the number of memory cells corresponding to spread 420.

There may be a mechanism such as FG coupling or charge loss because the threshold voltage of the memory cells undergoes an unwanted change over time.

As described above, the process of programming data in the memory cell or erasing data stored in the memory cell may be performed by HCE or F-N tunneling.

HCE can move many carriers to FG in less time than F-N tunneling, but can cause relatively large physical damage to the insulator between the FG and the substrate. F-N tunneling can cause relatively little damage to the insulator, but if the number of times of programming the data in the memory cell and erasing the data stored in the memory cell increases, the damage at this time cannot be ignored.

When carriers are accumulated in the FG and charges are formed, data of the memory cell is determined based on the formed charges. At this time, if the insulator around the FG receives physical damage, a leaking path of a carrier may be generated in the insulator.

The charge charged in the FG must be maintained in the FG before the discharge condition is established, but due to the natural diffusion phenomenon, the charge charged in the FG may diffuse around, and the insulator around the FG is damaged to form a charge leakage path. The charge charged in the FG may be lost. The mechanism by which the charge charged in the FG is lost tends to lower the threshold voltage of the memory cell.

The reader 120 may set the voltage level 440 to the first read voltage level. The reader 120 may read data from the memory cell array 110 using the voltage level 440. The read unit 120 may count the number of memory cells having a threshold voltage higher than the voltage level 440, and generate the number of the counted memory cells as first index information.

Since the read unit 120 does not recognize the change in the threshold voltage of the memory cells in which the data B is stored, the read unit 120 may set the voltage level 440 to the first read voltage level based on the positions of the dispersion 410 and the distribution 420. have.

The spreading portion 431 represents memory cells having a threshold voltage lower than the voltage level 440 among the memory cells corresponding to the spreading 430, and the area of the spreading portion 431 represents the voltage level of the memory cells in which the data B is stored. The number of memory cells having a threshold voltage lower than 440 is shown.

The spreading portion 432 represents memory cells having a threshold voltage higher than the voltage level 440 among the memory cells corresponding to the spreading 430, and the area of the spreading portion 432 represents a voltage level of the memory cells in which the data B is stored. The number of memory cells having a threshold voltage higher than 440 is shown.

The reader 120 may generate the number of memory cells corresponding to the scattering part 432 as first index information. The first index information may correspond to the area of the scattering portion 432.

The second index information stored in the memory cell array 110 may be the number of memory cells corresponding to the dispersion 420. Since the number of memory cells corresponding to the spread 430 is assumed to be the same as the number of memory cells corresponding to the spread 420, the second index information may correspond to the area of the spread 430.

Since the first index information corresponds to the area of the scattering portion 432 and the second index information corresponds to the area of the scattering 430, the controller 130 may control the second index information based on the difference between the first index information and the second index information. You can set the read voltage level.

If the first index information is smaller than the second index information, the controller 130 may set the voltage level 450 lower than the voltage level 440 as the second read voltage level.

The controller 130 may adjust the difference between the first read voltage level and the second read voltage level based on the area of the dispersion portion 431 that is the difference between the second index information and the first index information. The controller 130 may select the second read voltage level such that the difference between the first read voltage level and the second read voltage level increases as the area of the scattering portion 431 increases.

The controller 130 may select the second read voltage level according to the area of the dispersion portion 431, but may select the second read voltage level so that the difference between the second read voltage level and the first read voltage level is not greater than the maximum value. have. This is because if the difference between the second read voltage level and the first read voltage level is too large, the trajectory of the read voltage level may diverge without converging to the optimal read voltage level. The memory device 100 may set a maximum value of the change of the read voltage level so as to search for the optimal read voltage level.

5 is a diagram illustrating another example of an operation of the memory device 100 of FIG. 1.

Referring to FIG. 5, the horizontal axis represents a threshold voltage of a memory cell, and the vertical axis represents the number of memory cells having a threshold voltage.

Threshold voltages of memory cells in which data C is stored may form a distribution 510.

Threshold voltages of memory cells in which data D is stored may form a distribution 520.

Data C and data D may be m (m is a positive integer) bits of data. For example, data C may be 3-bit data “001” and data D may be 3-bit data “011”.

It is assumed that a threshold voltage of memory cells in which data C is stored changes with time to form a distribution 530. Assume that the number of memory cells corresponding to spread 530 is equal to the number of memory cells corresponding to spread 510.

As described above, there may be a mechanism such as FG coupling or charge loss because the threshold voltage of the memory cells undergoes an unwanted change over time.

The FG coupling refers to a phenomenon in which the threshold voltage of the central memory cell is affected by the amount of change in the threshold voltage of neighboring memory cells. The threshold voltage of the central memory cell is affected by the coupling of parasitic capacitance between the FGs of the memory cells.

If the programming process increases the threshold voltage, the threshold voltage of the central memory cell is increased by the FG coupling to a desired value. By mechanisms such as FG coupling, the distribution of threshold voltages of memory cells tends to spread.

Since the voltage window in which the multi-bit cell operates is limited, the spread of the threshold voltages increases, so the probability of overlap of the threshold voltages increases. The deeper the overlap of threshold voltages, the higher the error rate of not being able to read the programmed data correctly.

The reader 120 may set the voltage level 540 to the first read voltage level. The reader 120 may read data from the memory cell array 110 using the voltage level 540. The read unit 120 may count the number of memory cells having a threshold voltage higher than the voltage level 540, and generate the number of the counted memory cells as first index information.

The spreading portion 531 represents memory cells having a threshold voltage lower than the voltage level 540 among the memory cells corresponding to the spreading 530, and the area of the spreading portion 531 represents a voltage level of the memory cells in which the data C is stored. The number of memory cells having a threshold voltage lower than 540 is shown.

The spreading portion 532 represents memory cells having a threshold voltage higher than the voltage level 540 among the memory cells corresponding to the spreading 530, and the area of the spreading portion 532 corresponds to the voltage level of the memory cells in which the data C is stored. The number of memory cells having a threshold voltage higher than 540 is shown.

The reader 120 may generate, as first index information, the sum of the number of memory cells corresponding to the spreading portion 532 and the number of memory cells corresponding to the spreading 520. The first index information may correspond to the sum of the area of the scattering portion 532 and the area of the scattering 520.

The second index information stored in the memory cell array 110 may be the number of memory cells corresponding to the dispersion 520. Therefore, the second index information may correspond to the area of the dispersion 520.

Since the first index information corresponds to the sum of the area of the scattering portion 532 and the area of the scattering 520, and the second index information corresponds to the area of the scattering 520, the controller 130 may control the first index information and the second. The second read voltage level may be set based on the difference in the index information.

If the first index information is greater than the second index information, the controller 130 may set a voltage level 550 higher than the voltage level 540 as the second read voltage level.

The controller 130 may adjust the difference between the first read voltage level and the second read voltage level based on the area of the dispersion portion 532 that is the difference between the second index information and the first index information. The controller 130 may select the second read voltage level such that the difference between the first read voltage level and the second read voltage level is larger as the area of the scattering portion 532 is larger.

FIG. 6 is a diagram illustrating still another example of the operation of the memory device 100 of FIG. 1.

Referring to FIG. 6, the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells having the threshold voltage.

Threshold voltages of memory cells in which data E is stored may form a distribution 610.

Threshold voltages of memory cells in which data F is stored may form a distribution 620.

Data E and data F may be m (m is a positive integer) bits of data. For example, data E may be 4-bit data “0101” and data F may be 4-bit data “0111”.

Since the distance between the dispersions increases as m increases, there may be a case where the spreads overlap with each other as m increases. The case where the spread 610 and the spread 620 overlap each other is shown.

The controller 130 may generate the number of memory cells having a threshold voltage higher than the read voltage level as first index information. The second index information stored in the memory cell array 110 may be the number of memory cells in which the data F is stored. In this case, the second index information may correspond to the area of the dispersion 620.

If the read unit 120 selects the voltage level 640 as the read voltage level, the read unit 120 may select the number of memory cells having a threshold voltage higher than the voltage level 640 and the data F of the memory cells in which the data E is stored. The sum of the number of memory cells having a threshold voltage higher than the voltage level 640 among the stored memory cells may be generated as first index information.

When the memory device 100 generates the number of memory cells having a threshold voltage higher than the read voltage level as the first index information, the optimal read voltage level may be set to the voltage level 640 in the embodiment of FIG. 6.

If the number of samples is large, the spread may be proportional to the probability that a memory cell corresponds to the spread. For example, the probability that the memory cell having the threshold voltage of the voltage level 640 corresponds to the spread 620 may be higher than the probability that the memory cell having the threshold voltage of the voltage level 640 corresponds to the spread 610. In other words, the probability that the memory cell having the threshold voltage of the voltage level 640 stores the data F may be higher than the probability that the memory cell having the threshold voltage of the voltage level 640 stores the data E. FIG.

The probability that the memory cell having the threshold voltage of the voltage level 630 stores data E may be equal to the probability that the memory cell having the threshold voltage of the voltage level 630 stores data F.

When the memory cell has a threshold voltage higher than the voltage level 630, the probability that the memory cell stores the data F may be higher than the probability that the memory cell stores the data E. When the memory cell has a threshold voltage lower than the voltage level 630, the probability that the memory cell stores the data E may be higher than the probability that the memory cell stores the data F.

Thus, in the embodiment of FIG. 6, the optimal read voltage level may be the voltage level 630. The memory device 100 sets an offset based on the shape of the spread 610 and the spread 620 to select the voltage level 630 as an optimal read voltage level, and based on the set offset, 2 You can adjust the index information.

When the read unit 120 generates the number of threshold voltages higher than the read voltage level as the first index information, the memory device 100 may be configured with respect to a dispersion having a left biased form such as the spread 610 and the spread 620. You can set a positive offset. On the contrary, the memory device 100 may set a negative offset with respect to a dispersion having a right biased form.

The memory device 100 generates the adjusted second index information by adding an offset to the second index information, compares the adjusted second index information with the first index information, and adjusts the voltage level 630 to an optimal read voltage. You can choose by level.

7 is a diagram illustrating a memory device 700 according to another embodiment of the present invention.

Referring to FIG. 7, the memory device 700 includes a memory cell array 780, a read unit 1 710, a read unit 2 720, a counter 1 730, a counter 2 740, and an offset adjuster 750. And a comparator 760 and a voltage generator 770.

The voltage generator 770 may set a read voltage level and transmit the set read voltage level to the reader 1 710 and the reader 2 720.

The read unit 1 710 transmits a data read request to the memory cell array 780 and reads data from the memory cell array 780. In this case, the read unit 1 710 may read data using the read voltage level.

The read unit 2 720 transmits an index information read request to the memory cell array 780 and reads index information from the memory cell array 780.

The counter 1 730 may generate first index information by counting the number of memory cells included in the threshold voltage section from the read data. The threshold voltage section may be a section classified by the read voltage level.

Counter 2 740 may generate second index information by separating the number of memory cells included in the threshold voltage section from the index information.

The offset adjuster 750 may generate adjusted second index information by adding an offset to the second index information. The offset adjustment unit 750 may set the offset based on the form of the distribution of the threshold voltage.

The comparison unit 760 may compare first index information and the adjusted second index information. The comparator 760 may control the reader 1 710 to output current read data as output data when the first index information and the adjusted second index information are the same. The comparator 760 may control the reader 1 710 to read the next data and the reader 2 720 to read the next index information if the first index information and the adjusted second index information are the same. have.

The comparison unit 760 transmits the difference between the first index information and the adjusted second index information to the voltage generator 770 when the first index information and the adjusted second index information are different, and reads the first unit 710. Readout 1 710 may control the readout 1 710 to read data back from the memory cell array 780.

The voltage generator 770 may adjust the read voltage level based on the difference between the first index information and the adjusted second index information, and transmit the adjusted read voltage level to the reader 1 710. The read unit 1 710 may retransmit a read request to the memory cell array 780 and read data again from the memory cell array 780 using the adjusted read voltage level.

FIG. 8 is a diagram illustrating another example of the memory device 700 of FIG. 7.

Referring to FIG. 8, the voltage generator 770 may generate a read voltage level corresponding to a voltage level code received from a multiplexer 820.

The comparator 760 may generate a voltage level code based on the difference between the first index information and the adjusted second index information. The multiplexer 820 selects any one of a voltage level code received from the code memory 810 and a voltage level code received from the comparator 760 according to a signal received from the comparator 760 and generates a voltage generator ( 770.

The comparator 760 may control the code memory 810 to store the voltage level code received from the comparator 760 when the first index information is equal to or nearly similar to the adjusted second index information. At this time, the voltage level corresponding to the stored voltage level code may be regarded as an optimal read voltage level.

The comparator 760 allows the multiplexer 820 to transmit a voltage level code (corresponding to an optimal read voltage level code) stored in the code memory 810 to the voltage generator 770 during a next data read operation. 820 may be controlled.

The memory device 700 may shorten the time for searching for the optimal read voltage level by using the previously found optimal read voltage level as the default read voltage level in the next data read operation.

9 is a diagram illustrating an example of an operation of the memory device 200 of FIG. 2.

Referring to FIG. 9, a distribution of threshold voltages of a multi-bit cell storing three bit data is shown.

The memory cell array 210 may include multi-bit cells that store 3-bit data.

The first group 910 shows the distribution of threshold voltages of the multi-bit cells after the first data page has been programmed.

The spread 911 may be a spread of multi bit cells in which a first data page "1" is programmed. The spread 912 may be a spread of multi bit cells in which a first data page "0" is programmed.

The programming unit 250 may count the number of multi-bit cells corresponding to the spread 911 and the number of multi-bit cells corresponding to the spread 912 based on the first data page. The programming unit 250 generates the number of multi-bit cells corresponding to the spread 911 and the number of multi-bit cells corresponding to the spread 912 as second index information and programs the second index information into the multi-bit cells. can do.

After the programming operation of the first data page is performed, the controller 230 may adjust the read voltage level such that a difference between the first index information and the second index information is equal to or less than a reference value. In this case, the memory device 200 may set the voltage level between the distribution 911 and the distribution 912 as the read voltage level, and the first index information is the number of multi-bit cells having a threshold voltage higher than the read voltage level. In this case, the second index information may be the number of multi-bit cells corresponding to the spread 912.

After the programming operation of each of the data pages is performed, the memory device 200 may perform a first internal read operation to identify a threshold voltage state of the programmed multi-bit cell. For example, the multi-bit cells corresponding to the distribution 912 may have a first threshold voltage state. Since the memory device 200 knows the number of multi-bit cells that are simultaneously programmed, when the number of multi-bit cells corresponding to the spread 912 is known, the memory device 200 may calculate the number of multi-bit cells corresponding to the spread 911.

The programming unit 250 may set a target threshold voltage state of the multi-bit cells based on the threshold voltage state and the second data page identified by the result of the first internal read operation. For example, the target threshold voltage state of the multi-bit cell in which the second data page “1” is to be programmed among the multi-bit cells identified as corresponding to the spread 911 by the result of the first internal read operation is the spread 921. The target threshold voltage state of the multi bit cell in which the second data page “0” is to be programmed among the multi bit cells corresponding to the distribution 911 may be the distribution 922. The target threshold voltage state of the multi-bit cell in which the second data page "1" of the multi-bit cells corresponding to the spread 912 is to be programmed is the spread 923, and the second data of the multi-bit cells corresponding to the spread 912. The target threshold voltage state of the multi-bit cell in which page " 0 " is to be programmed may be a distribution 924.

The programming unit 250 may set the spread 922 to the second threshold voltage state and the spread 924 to the third threshold voltage state among the set target threshold voltage states. The programming unit 250 may generate the number of multi-bit cells having a second threshold voltage state and the number of multi-bit cells having a third threshold voltage state as third index information. The programming unit 250 may simultaneously program the second data page and the third index information into the multi-bit cells. The programming unit 250 may program each of the multi bit cells such that the threshold voltage of each of the multi bit cells corresponds to the target threshold voltage state.

The second group 920 shows the distribution of threshold voltages of the multi-bit cells after the second data page has been programmed. Multi-bit cells programmed with data "11" correspond to spread 921, multi-bit cells programmed with data "10" correspond to spread 922, and multi-bit cells programmed with data "01" spread. Corresponding to 923, multi-bit cells programmed with data “00” may correspond to spread 924.

The memory device 200 may identify a threshold voltage state of the multi-bit cells by performing a second internal read operation, and set a target threshold voltage state of the multi-bit cells based on the identified threshold voltage state and the third data page. .

The third group 930 shows the distribution of threshold voltages of the multi-bit cells after the third data page has been programmed.

Multi-bit cells programmed with data "111" correspond to spread 931, multi-bit cells programmed with data "110" correspond to spread 932, and multi-bit cells programmed with data "101" spread Corresponding to 933, multi-bit cells programmed with data “100” may correspond to spread 934. Multi-bit cells programmed with data "011" correspond to spread 935, multi-bit cells programmed with data "010" correspond to spread 936, and multi-bit cells programmed with data "001" spread Corresponding to 937, multi-bit cells programmed with data “000” may correspond to spread 938.

The memory device 200 generates, as index information, the number of multi-bit cells corresponding to the spread 912, the number of multi-bit cells corresponding to the spread 922, and the number of multi-bit cells corresponding to the spread 924. can do. The memory device 200 may determine the number of multi-bit cells corresponding to the spread 932, the number of multi-bit cells corresponding to the spread 934, the number of multi-bit cells corresponding to the spread 936, and the spread 938. The number of corresponding multi-bit cells may be generated as index information. The memory device 200 may calculate cell information of all the dispersions by using the cell information of the seven distributions 912, 922, 924, 932, 934, 936, and 938.

For example, the memory device 200 may determine the number of multi-bit cells that are simultaneously programmed, the number of multi-bit cells corresponding to the spread 912, the number of multi-bit cells corresponding to the spread 922, and the spread 932. The number of multi-bit cells corresponding to the spread 931 may be calculated based on the number of corresponding multi-bit cells.

After the programming operation is performed on three data pages, the memory device 200 may select the optimal read voltage levels 941, 942, 943, 944, 947, 945, 946, and 947 using index information. have. For example, the memory device 200 may select the read voltage level 947 as an optimal read voltage level between the spread 937 and the spread 938 based on the number of multi-bit cells corresponding to the spread 938. have.

10 is a diagram illustrating a memory data reading method according to another embodiment of the present invention.

Referring to FIG. 10, the memory data read method reads data from a memory cell array using a first read voltage level (S1010).

The memory data reading method generates first index information based on the read data (S1020).

The memory data read method reads second index information stored in a memory cell array (S1030).

The memory data reading method compares the first index information and the second index information (S1040). The memory data reading method determines whether the first index information is the same as the second index information in step S1040. The memory data read method may determine whether to generate a second read voltage level based on a comparison result of the first index information and the second index information.

If the first index information is the same as the second index information, the memory data reading method may output the read data (S1060).

If the first index information is different from the second index information, the memory data read method generates a second read voltage level (S1050).

The memory data read method may read data from the memory cell array using the generated second read voltage level (S1010).

Embodiments of the present invention can be applied to a memory device that stores data by changing a threshold voltage of a memory cell. Examples of this kind of memory device may include flash memory, electrically erasable programmable read only memory (EEPROM), and the like.

Memory data reading method according to embodiments of the present invention is implemented in the form of program instructions that can be executed by various computer means may be recorded on a computer readable medium. The computer readable medium may include program instructions, data files, data structures, etc. alone or in combination. Program instructions recorded on the media may be those specially designed and constructed for the purposes of the present invention, or they may be of the kind well-known and available to those having skill in the computer software arts. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tape, optical media such as CD-ROMs, DVDs, and magnetic disks, such as floppy disks. Magneto-optical media, and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, flash memory, and the like. Examples of program instructions include not only machine code generated by a compiler, but also high-level language code that can be executed by a computer using an interpreter or the like. The hardware device described above may be configured to operate as one or more software modules to perform the operations of the present invention, and vice versa.

The flash memory device and / or the memory controller according to the embodiments of the present invention may be implemented using various types of packages. For example, a flash memory device and / or a memory controller according to embodiments of the present invention may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack ( TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed Stack Package (WSP), and the like.

The flash memory device and the memory controller may constitute a memory card. In this case, the memory controller may be configured to communicate with an external (eg, host) via one of various interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, IDE, and the like.

The flash memory device is a nonvolatile memory device that can maintain stored data even when power is cut off. With the increasing use of mobile devices such as cellular phones, PDA digital cameras, portable game consoles, and MP3Ps, flash memory devices may become more widely used as code storage as well as data storage. Flash memory devices can also be used for home applications such as HDTV, DVD, routers, and GPS.

The computing system according to the embodiments of the present invention includes a microprocessor, a user interface, a modem such as a baseband chipset, a memory controller, and a flash memory device electrically connected to a bus. The flash memory device will store, via the memory controller, N-bit data (N is an integer greater than or equal to 1) processed / to be processed by the microprocessor. When the computing system according to the embodiments of the present invention is a mobile device, a battery for supplying an operating voltage of the computing system will be further provided.

Those skilled in the art that the computing system according to the embodiments of the present invention may further be provided with an application chipset, a camera image processor (CIS), a mobile DRAM, and the like. Self-explanatory The memory controller and the flash memory device may, for example, constitute a solid state drive / disk (SSD) that uses nonvolatile memory to store data.

As described above, the present invention has been described by way of limited embodiments and drawings, but the present invention is not limited to the above embodiments, and those skilled in the art to which the present invention pertains various modifications and variations from such descriptions. This is possible.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the claims below but also by the equivalents of the claims.

1 is a diagram illustrating a memory device 100 according to an embodiment of the present invention.

2 is a diagram illustrating a memory device 200 according to another embodiment of the present invention.

3 is a diagram illustrating a memory device 300 according to another exemplary embodiment of the present invention.

4 is a diagram illustrating an example of an operation of the memory device 100 of FIG. 1.

5 is a diagram illustrating another example of an operation of the memory device 100 of FIG. 1.

FIG. 6 is a diagram illustrating still another example of the operation of the memory device 100 of FIG. 1.

7 is a diagram illustrating a memory device 700 according to another embodiment of the present invention.

FIG. 8 is a diagram illustrating another example of the memory device 700 of FIG. 7.

9 is a diagram illustrating an example of an operation of the memory device 200 of FIG. 2.

10 is a diagram illustrating a memory data reading method according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

110: memory cell array

120: reader

130: control unit

Claims (21)

A memory cell array including a plurality of memory cells; A read unit configured to read data from the memory cell array using a first read voltage level and to generate first index information based on the read data; And A control unit that reads second index information stored in the memory cell array and determines whether to generate a second read voltage level based on a result of comparing the first index information and the second index information. Memory device comprising a. The method of claim 1, The control unit Generating a second read voltage level based on a difference between the first index information and the second index information when a difference between the first index information and the second index information is equal to or greater than a reference value; The reading part And update the data from the memory cell array using the generated second read voltage level, and update the first index information based on the updated data. The method of claim 2, Error control code decoder to decode the read data to produce output data More, The control unit And setting the reference value based on an error correction range or an error correction capability of the error control code decoder. The method of claim 1, The reading part And counting the number of memory cells having a threshold voltage higher than the first read voltage level based on the read data, and generating the calculated number of memory cells as the first index information. The method of claim 4, wherein The control unit And setting the voltage level higher than the first read voltage level as the second read voltage level when the first index information is greater than the second index information. The method of claim 4, wherein The control unit And setting the voltage level lower than the first read voltage level as the second read voltage level when the first index information is smaller than the second index information. The method of claim 4, wherein The control unit And adjusting a difference between the first read voltage level and the second read voltage level based on a difference between the first index information and the second index information. The method of claim 4, wherein The control unit And set the second read voltage level such that a difference between the first read voltage level and the second read voltage level is not greater than a maximum value. The method of claim 1, The memory cell array A data storage unit in which the data is stored; And Index storage unit for storing the second index information corresponding to the stored data Including, The memory device is A programming unit configured to program the data into the data storage unit and program the second index information into the index storage unit. The memory device further comprising. The method of claim 1, A page buffer to store the read data More, The control unit And determining whether to output data stored in the page buffer based on a result of the comparison between the first index information and the second index information. The method of claim 1, Code memory to store read voltage level codes More, The control unit And determining whether to store a read voltage level code corresponding to the first read voltage level in the code memory based on a comparison result of the first index information and the second index information. The method of claim 11, The reading part And a read voltage level corresponding to a read voltage level code stored in the code memory to the first read voltage level. The method of claim 1, The control unit Set an offset based on a shape of a distribution of threshold voltages of the memory cells, adjust the second index information based on the offset, and based on a comparison result of the first index information and the adjusted second index information To determine whether to generate the second read voltage level. The method of claim 1, The control unit And determine whether to generate a second read voltage level separately for each of the plurality of memory cells. The method of claim 1, Each of the plurality of memory cells is a multi-bit cell capable of storing multi-bit data, The memory device is Programming to generate the second index information by counting the number of memory cells having a first threshold voltage state based on a first data page, and programming the first data page and the second index information to the plurality of memory cells. part More, The controller adjusts the second read voltage level such that a difference between the first index information and the second index information is equal to or less than a reference value, The programming unit generates third index information by counting the number of memory cells having a second threshold voltage state based on the second index information and the second data page, and generates the second data page and the third index information. A memory device for programming to a plurality of memory cells. Reading data from the memory cell array using the first read voltage level; Generating first index information based on the read data; Reading second index information stored in the memory cell array; Comparing the first index information and the second index information; And Determining whether to generate a second read voltage level based on the comparison result Memory data reading method comprising a. The method of claim 16, Determining whether to generate the second read voltage level is Generating a second read voltage level based on a difference between the first index information and the second index information when a difference between the first index information and the second index information is equal to or greater than a reference value; The memory data read method is Updating the data from the memory cell array using the generated second read voltage level; And Updating the first index information based on the updated data Memory data read method comprising more. The method of claim 16, Generating the first index information And calculating the number of memory cells having a threshold voltage higher than the first read voltage level based on the read data, and generating the calculated number of memory cells as the first index information. The method of claim 16, Storing information related to the first read voltage level when a difference between the first index information and the second index information is less than a reference value; Memory data read method comprising more. The method of claim 16, Generating the second index information by counting the number of memory cells having a first threshold voltage state based on a first data page; Programming the first data page and the second index information in the memory cell array; Generating third index information by counting the number of memory cells having a second threshold voltage state based on the second index information and the second data page; And Programming the second data page and the third index information into the memory cell array. Memory data read method comprising more. A computer-readable recording medium in which a program for executing the method of any one of claims 16 to 20 is recorded.

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