KR20090069861A - Method for programming a nonvolatile memory device - Google Patents

Abstract

A method for programming a nonvolatile memory device is provided to prevent program disturbance generated in a memory cell by applying a low voltage to a word line. A ground voltage(0V) is applied to a bit line selected among a plurality of bit lines in order to pre-charge a channel of a memory cell connected to an unselected bit line. A power voltage(Vcc) is applied to the unselected bit line. The ground voltage is applied to a gate of a second selecting transistor. A program voltage is applied to a word line selected among a plurality of word lines in order to perform a program operation. A pass voltage(Vpass) is applied to a rest unselected word line except for a second unselected word line and a third unselected word line based on the selected word line. A first decouple voltage is applied to the third unselected word line.

Description

Program method of nonvolatile memory device {METHOD FOR PROGRAMMING A NONVOLATILE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and in particular, to a method of programming a nonvolatile memory device, in particular self boosting a NAND flash memory device having a string structure in which a plurality of memory cells are connected in series. It is about a method.

A NAND flash memory device comprises a unit string consisting of a plurality of memory cells connected in series and a selection transistor for selecting the memory cells. The NAND flash memory device mainly includes a memory stick and a universal serial bus driver. Increasingly, the field of application is being expanded to replace hard disks.

1 is an equivalent circuit diagram illustrating a memory cell array of a NAND flash memory device according to the prior art, and FIG. 2 is a cross-sectional view illustrating a unit string ST shown in FIG. 1.

1 and 2, a cell array of a NAND flash memory device according to the prior art includes a drain select transistor DST (hereinafter referred to as a first select transistor) and a source select transistor SST (hereinafter referred to as a second). And a string consisting of a plurality of memory cells MC0 to MC31 connected in series between the first and second selection transistors DST and SST. In addition, the first and second selection transistors DST and SST and the memory cells MC0 to MC31 are arranged in a matrix form of rows and columns, and the first and second selection transistors DST and SST arranged in the same rows are formed. It is selected by each selection line DSL and SSL. In addition, the memory cells MC0 to MC31 arranged in the same rows are respectively selected by the corresponding word lines WL0 to WL31. In addition, bit lines BL0 and BL1 are connected to the drain of the first select transistor DST, and a source of the second select transistor SST is connected to the common source line CSL.

In a program operation of a NAND flash memory device according to the related art having such a structure, a self-boosting method is applied to a cell to be programmed (hereinafter referred to as a program cell) and a cell dependent on the same word line (hereinafter referred to as a prohibited cell). This prevents program operation from happening. The self-boosting method according to the related art blocks a program operation by applying a ground voltage to a bit line connected to a string including a program cell and applying a power supply voltage to a bit line connected to the string including a inhibit cell.

Referring to Figure 3 describes the self-boosting method according to the prior art.

3 is a conceptual diagram illustrating a self-boosting method according to the prior art.

Referring to FIG. 3, a ground voltage (0V) is applied to the gate of the second selection transistor SST to cut off the ground path of the memory cell array. In addition, the ground voltage 0V is applied to the selected bit line BL0, and the power supply voltage Vcc is applied as the program prohibition voltage (self-boosting voltage) to the unselected bit line BL1. In addition, the power supply voltage Vcc is applied to the gate of the first selection transistor DST to charge the source of the first selection transistor DST to a voltage of the "threshold voltage of the first selection transistor DST". The one select transistor DST is virtually blocked. In addition, the program voltage Vpgm is applied to the selected Nth word line WL4, and the pass voltage Vpass is applied to the unselected word lines WL0, WL1, WL2, and WL5 to WL31. The ground line 0V is applied to the word line WL3 to charge channel regions of memory cells that are dependent on the same string by charge sharing. In this state, the channel voltages of the memory cells are induced by capacitive coupling due to the high program voltage Vpgm applied to the selected Nth word line WL4. As a result, an environment in which Fowler-Nordheim (FN) tunneling cannot occur between the floating gate and the channel is formed, which causes the inhibit cell (IPC) to be initially erased. The threshold voltage of is maintained.

However, the following problems occur in the self-boosting method according to the prior art.

In the NAND flash memory device, a single level cell (SLC) has been switched from a multi level cell (MLC) to higher integration and higher capacity. Accordingly, when performing a program operation using a local self boosting method, program disturbance according to the state of the previous word line of the Nth word line WL4 for selecting the program cell PC. ) Phenomenon occurs.

Referring to FIG. 3, when the program operation is performed on the N-th word line WL4 in a mode in which a program operation is sequentially performed from the first word line WL0 in a local self-boosting manner, N− If the first word line WL3 is programmed and the cells connected to the N-2 th previous word line WL2 are programmed in the erased state, the program is performed in the cell connected to the N-3 th word line WL1. A disturbance phenomenon occurs. The reason for this is that the N-2 th word line WL2 is a program state, and even though the pass voltage Vpass is applied, the boosting voltage is locally reduced, and the channel boosting state of the N-3 th word line WL1 is also N-2th. This is because it is lowered due to the channel boosting of the word line WL2.

FIG. 4 shows that word lines WL20 to WL28 fail frequently after the word line WL19 when the local self-boosting method according to the related art is applied. 5 shows that a failure occurs in the N-th word line WL1.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and provides a program method of a nonvolatile memory device capable of preventing program disturbance occurring in a previous third non-selected word line based on a selected word line. Its purpose is to.

According to an aspect of the present invention, a string including a first and second select transistors and a plurality of memory cells connected in series therebetween, and a plurality of bits connected to the first select transistor, are provided. A program method of a non-volatile memory device having a line, a common source line connected to the second selection transistor, and a plurality of word lines for selecting the memory cells, respectively, the method comprising: grounding a selected bit line among the bit lines; Applying a voltage, applying a power supply voltage to unselected bit lines, and applying a ground voltage to a gate of the second select transistor to precharge a channel of memory cells connected to the unselected bit line; The program voltage is applied to the selected word line among the word lines, and is based on the selected word line among the unselected word lines. A pass voltage is applied to the remaining unselected word lines except for the second and third unselected word lines, and a first decouple voltage lower than the pass voltage is applied to the third unselected word lines to perform a program operation. It provides a program method of a nonvolatile memory device comprising the step of performing.

According to the present invention having the above-described configuration, during a program operation of the nonvolatile memory device, a voltage lower than a pass voltage applied to other non-selected word lines is applied to the third unselected word line based on the selected word line. The application may prevent program disturbances occurring in the memory cells dependent on the third unselected word line.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. Explain. In addition, parts denoted by the same reference numerals throughout the specification represent the same components.

Example

FIG. 6 is an equivalent circuit diagram of a memory cell array of a nonvolatile memory device, which is illustrated as an example to explain a program method of a nonvolatile memory device according to an exemplary embodiment of the present invention.

As shown in FIG. 6, the memory cell array of the nonvolatile memory device according to the embodiment of the present invention is the same as the cell array structure of the NAND flash memory device illustrated in FIGS. 1 and 2, and thus, a detailed description thereof. Will be replaced by the above description.

Hereinafter, a program method of a nonvolatile memory device according to the present invention will be described.

First, the program method according to the present invention proceeds after performing the erase operation as in the prior art. The erase operation is an operation of emitting and removing electrons stored in the floating gate to the substrate, and the erase operation may be performed in blocks. When an erase voltage of approximately 20 V is applied to the bulk (substrate) and a ground voltage (0 V) is applied to a word line connected to all cells, the voltage is stored in the floating gate by an electric field caused by an erase voltage in the opposite direction to the program operation. The electrons are erased and holes are injected. By such an erase operation, the cell initially has a threshold voltage of about -1V to -3V.

Subsequently, the implemented program operation is based on the Increment Step Pulse Program (ISPP) method, which repeatedly executes the program operation and the verify operation by a set number of times, and grounds the bit line connected to the string including the program cell PC. By applying a voltage (0V) and applying a program voltage of approximately 18V to 20V to a word line connected to the gate of the program cell PC, a high voltage between the channel of the program cell PC and the control gate of the program cell PC is applied. The FN tunneling due to the voltage difference causes electrons present in the channel region to be injected into the floating gate to change the threshold voltage of the program cell PC to a positive voltage (about 1V to 3V).

A program method according to an embodiment of the present invention will be described in detail with reference to FIG. 6 as follows.

Referring to FIG. 6, the ground voltage 0V is applied to the gate of the second selection transistor SST, and the power supply voltage Vcc is applied to the common source line CSL. At the same time, the ground voltage 0V is applied to the selected bit line BL0 (hereinafter referred to as the selection bit line), and the selected word line (hereinafter referred to as the selection word line) is connected to the gate of the program cell PC. In order to prevent the inhibit cell IPC from being programmed among the cell dependent on the word line, the power supply voltage Vcc, which is a program inhibit voltage, is applied to the bit line BL1 connected to the string including the inhibit cell IPC. . At the same time, a power supply voltage Vcc is applied to the gate of the first selection transistor DST.

Next, the program voltage Vpgm is applied to the Nth select word line WL4 among the word lines WL0 to WL31, and the Nth select word line WL4 among the unselected word lines WL0 to WL3 and WL5 to WL31. The word line in which the program operation is performed in front of the current Nth selected word line WL4 in the mode in which the program operation is sequentially performed from the first word line-first word line WL0 to the last word line WL31 in order. The pass voltage Vpass is applied to the remaining unselected word lines WL0, WL3, WL5 to WL31 except for the N-2nd unselected word line WL2 and the N-3rd unselected word line WL1. The program operation is performed by applying a first decouple voltage lower than the pass voltage Vpass to the N-3 th unselected word line WL1. In addition, a second decouple voltage lower than the first decouple voltage is applied to the N-2 th unselected word line WL2. At this time, the memory cell connected with the N-th unselected word line WL3 is in a program state, and the memory cell connected with the N-second unselected word line WL2 is in an erased state. Here, the first decouple voltage is a 3 ~ 7V voltage, the second decouple voltage is a ground voltage (0V). In addition, the pass voltage Vpass is 8-12V, and the program voltage Vpgm is 18-20V.

Meanwhile, the method for preventing program disturbance by applying a voltage applied to the N-3 th unselected word line WL1 to a voltage lower than the pass voltage Vpass has been described. In the case where 32 memory cells are sequentially connected in series from SST to the first selection transistor DST, the N-3rd unselected word line WL1 is the fourth to 28th memory of the 32 memory cells. The effect is great when one of the word lines WL4 to WL28 connected to the cells MC4 to MC28 is applied.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In particular, in the present invention, the unit string consisting of 32 memory cells has been described as an example, but for convenience of description, the number of memory cells constituting the unit string is not limited. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1 is an equivalent circuit diagram showing a memory cell array of a NAND flash memory device according to the prior art.

FIG. 2 is a cross-sectional view illustrating a memory cell array of the NAND flash memory device shown in FIG. 1. FIG.

3 is an equivalent circuit diagram illustrating a program method of a NAND flash memory device according to the prior art.

4 and 5 are diagrams for explaining a program failure due to a disturbance caused by a program method of a NAND flash memory device according to the prior art.

6 is an equivalent circuit diagram illustrating a memory cell array of a NAND flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

MC0 ~ MC31: Memory Cell

WL0 ~ WL31: Word line

BL0, BL1: Bit Line

DST: drain select transistor (first select transistor)

SST: source select transistor (second select transistor)

Claims (7)

A string including first and second select transistors and a plurality of memory cells connected in series between the first and second select transistors, a plurality of bit lines connected to the first select transistor, a common source line connected to the second select transistor, A program method of a nonvolatile memory device having a plurality of word lines for selecting the memory cells, respectively, A memory cell connected to the unselected bit line by applying a ground voltage to a selected bit line among the bit lines, applying a power supply voltage to unselected bit lines, and applying a ground voltage to a gate of the second select transistor Precharging the channel of interest; And The program voltage is applied to the selected word line among the word lines, and the pass voltage is applied to the remaining unselected word lines except for the previous second and third unselected word lines based on the selected word line among the unselected word lines. Applying a first decouple voltage lower than the pass voltage to the third unselected word line to perform a program operation; Program method of a nonvolatile memory device comprising a. The method of claim 1, And applying a second decouple voltage lower than the first decouple voltage to the second non-select word line. The method of claim 2, And the second decoupled voltage is a ground voltage (0V). The method of claim 1, The first decoupled voltage is 3V to 7V program method of the non-volatile memory device. The method of claim 1, The pass voltage is a program method of a nonvolatile memory device of 8 ~ 12V. The method of claim 1, A nonvolatile memory cell connected to a first non-selected word line positioned between the selected word line and the second non-selected word line is in a program state, and a memory cell connected to the second non-selected word line is in an erased state Program method of memory device. The method of claim 1, When the string has a structure in which 32 memory cells from the second select transistor to the first select transistor are sequentially connected in series, the third unselected word line is selected from the fourth memory cell of the 32 memory cells from 28. A method of programming a nonvolatile memory device corresponding to any one of non-selected word lines connected to a first memory cell.

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