KR20090056184A - Organic light emitting display and manufacturing method for the same - Google Patents

Abstract

An organic electroluminescent display device and a manufacturing method thereof are provided to prevent the lowering of an output saturation characteristic of a driving transistor by preventing the external light from being inputted to a semiconductor layer of the driving transistor. A sub pixel includes a switching transistor, a capacitor, a driving transistor, and an OLED(Organic Light Emitting Diode). The switching transistor is positioned in a first area on a substrate(110). The capacitor is positioned in the second area on the substrate. The driving transistor and the organic light emitting diode are positioned in a third area on the substrate. The driving transistor includes a first electrode(113b), a semiconductor layer(111), a second electrode(113a), an insulating layer and a gate. The first electrode is positioned in the center of the third region. One side of the semiconductor layer contacts the first electrode. The semiconductor layer is formed with the band type in order to surround the first electrode. The second electrode contacts the other side of the semiconductor layer. The insulating layer is positioned on the first electrode, the semiconductor layer and the second electrode. The gate is positioned on the insulating layer to cover the semiconductor layer.

Description

Organic Light Emitting Display and Manufacturing Method for the Same

The present invention relates to an organic light emitting display device and a manufacturing method thereof.

Recently, the importance of the flat panel display (FPD) is increasing with the development of multimedia. In response, such as liquid crystal display (LCD), plasma display panel (PDP), field emission display (FED), organic light emitting device (Organic Light Emitting Device), etc. Various flat panel display devices are put into practical use.

In particular, the organic light emitting display device has a high response speed, low power consumption, and self emitting light. In addition, since the organic light emitting display device has no problem in viewing angle, it has advantages as a moving image display medium regardless of its size. In addition, since the organic light emitting display device can be manufactured at a low temperature and can be simply manufactured by using a conventional semiconductor process technology, it has attracted attention as a next generation flat panel display device.

Meanwhile, in the conventional top emission type inverted organic light emitting display device, a cathode of an organic light emitting diode is first formed on a driving transistor so that the cathode potential is the same as the drain potential of the driving transistor.

In such a structure, a field effect is applied to the semiconductor layer region of the driving transistor due to light incident from the outside, and thus the output saturation characteristic of the driving transistor is deteriorated. do.

An object of the present invention for solving the above problems of the background art is to prevent the problem of deterioration in output output characteristics of the top emission type inverted organic light emitting display device.

According to the above-described problem solving means, the present invention provides a sub transistor including a switching transistor located in a first region defined on a substrate, a capacitor located in a second region, a driving transistor located in a third region, and an organic light emitting diode. The driving transistor includes a first electrode positioned at the center of the third region, a semiconductor layer positioned in a strip shape such that one side contacts the first electrode and surrounds the first electrode, and the other side of the semiconductor layer. An organic light emitting display device comprising: a second electrode in contact with a first electrode and spaced apart from the first electrode; an insulating layer disposed over the first electrode, the semiconductor layer, and the second electrode; and a gate positioned over the insulating layer to cover the semiconductor layer. to provide.

The first electrode of the driving transistor may have a rectangular shape.

The subpixel further includes a passivation layer positioned on the gate and a planarization layer positioned on the passivation layer, wherein the insulating layer, the passivation layer, and the planarization layer may include a first contact hole patterned to expose the first electrode in the center region of the third region. Can be.

The gate of the driving transistor may be located below the region located in the center region of the semiconductor layer in the outer region of the semiconductor layer.

The organic light emitting diode is disposed on the planarization layer and is connected to the first electrode of the driving transistor exposed through the first contact hole, the organic light emitting layer is disposed on the cathode, and the organic light emitting layer is disposed on the organic light emitting layer. It may include a connected anode.

The cathode of the organic light emitting diode may be positioned to cover all of the first electrode, the semiconductor layer, and the second electrode of the driving transistor on the planarization film.

The switching transistor includes: a first electrode connected to a data line on a substrate; a second electrode surrounded by three surfaces of the first electrode; an insulating film positioned to cover the first electrode and the second electrode; It may include a gate connected to the scan line.

The capacitor includes one end connected to the gate of the driving transistor and extending to the second electrode of the switching transistor, an insulating film positioned to cover the one end, and the other end disposed on the insulating film and connected to the second power line and connected to the second electrode of the driving transistor. It may include.

On the other hand, in another aspect, the present invention, the step of defining a first region, a second region and a third region in a sub-pixel located on the substrate; And forming a switching transistor in the first region, forming a capacitor in the second region, and forming a driving transistor in the third region, wherein the driving transistor comprises a first electrode having a rectangular shape located at the center of the third region. A semiconductor layer positioned in a rectangular band so that one side contacts the first electrode and surrounds the first electrode, a second electrode in contact with the other side of the semiconductor layer and spaced apart from the first electrode, and the first electrode and the semiconductor layer And an insulating film positioned over the second electrode and a gate positioned over the insulating layer to cover the semiconductor layer.

The gate of the driving transistor may be located below the region located in the center region of the semiconductor layer in the outer region of the semiconductor layer.

The present invention has the effect of preventing the problem of deterioration of the output segmentation characteristics of the top emission type inverted organic light emitting display device. In addition, the number of masks used when manufacturing the top emission type inverted organic light emitting display device may be reduced.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

1 is a schematic plan view of an organic light emitting display device according to an embodiment of the present invention.

As illustrated in FIG. 1, the organic light emitting display device may include a display unit 120 on which a plurality of sub pixels P are positioned on the substrate 110. The plurality of sub pixels P located on the substrate 110 are vulnerable to moisture or oxygen.

Thus, the sealing substrate 130 may be provided, and the adhesive member 140 may be formed on the outer substrate 110 of the display unit 120 to encapsulate the substrate 110 and the sealing substrate 130. Meanwhile, the plurality of sub pixels P may be driven by the driver 150 positioned on the substrate 110 to represent an image.

The driver 150 may include a scan driver for supplying scan signals to the plurality of sub pixels P and a data driver for supplying data signals to the plurality of sub pixels P. Referring to FIG.

Here, the driver 150 is only schematically illustrated as an example that the scan driver and the data driver are formed on one chip, and the scan driver and the data driver may be located separately from the substrate 110 or the outside of the substrate 110. have.

Hereinafter, a circuit configuration of the sub pixel P shown in FIG. 1 will be described.

2 is an exemplary circuit configuration of a subpixel.

As illustrated in FIG. 2, the subpixel may include a switching transistor S1 having a gate connected to the scan line SCAN and a first electrode connected to the data line. In addition, the driving transistor T1 may include a gate connected to the second electrode of the switching transistor S1 and a second electrode connected to the second power line VSS. In addition, a capacitor Cst having one end connected to the gate of the driving transistor T1 and the other end connected to the second power line VSS may be included. The organic light emitting diode D may further include an organic light emitting diode D having an anode connected to the first power line VDD and a cathode connected to the first electrode of the driving transistor T1.

Here, although the switching transistor S1 and the driving transistor T1 included in the subpixel are illustrated as N-Type for explaining an example of the embodiment, the present invention is not limited thereto.

In the circuit configuration of the sub-pixel as described above, the first electrode of the driving transistor T1 and the cathode of the organic light emitting diode D may be electrically connected through the first contact hole Contact1.

For this reason, the organic light emitting diode D included in the organic light emitting display device according to the exemplary embodiment of the present invention may have an inverted structure in which a cathode is positioned at a lower portion and an anode is positioned at an upper portion thereof.

Hereinafter, the structure of the subpixel will be described by attaching a plan view and a cross-sectional view of the subpixel based on the circuit configuration of the subpixel.

FIG. 3A is a plan view of the subpixel, FIG. 3B is a sectional view to A-A of FIG. 3A, FIG. 4A is a plan view of the subpixel, and FIG. 4B is a sectional view to B-B of FIG. 4A.

3A to 4B illustrate a cross-sectional view of a partial region for convenience of description, or a configuration to cover a structure located below the second power line VSS and scan line SCAN. Only outlined or omitted.

Referring to FIG. 3A, the subpixel Pixel may include a switching transistor positioned in a first area Area1 defined on a substrate (not shown). In addition, it may include a capacitor located in the second area (Area2). In addition, the semiconductor device may include a driving transistor and an organic light emitting diode positioned in the third region Area3.

As described with reference to FIG. 2, the switching transistor positioned in the first area Area1 includes a first electrode having one end connected to the data line DATA, a second electrode having three surfaces surrounded by the first electrode, and a first electrode. An insulating layer may be disposed to cover the electrode and the second electrode, and a gate may be disposed on the insulating layer and connected to the scan line SCAN.

As described with reference to FIG. 2, the capacitor positioned in the second area Area2 includes one end connected to the gate of the driving transistor and connected to the gate of the driving transistor, an insulating film positioned to cover the one end, and an insulating film on the insulating film. And the other end connected to the second power line and connected to the second electrode of the driving transistor. Here, one end connected to the gate of the driving transistor may be electrically connected to each other through the second contact hole Contact2 positioned in the fourth region Area4 as shown in the drawings, but is not limited thereto.

As described with reference to FIG. 2, the driving transistor positioned in the third region Area3 includes a first electrode positioned at the center, a second electrode connected to the second power line and the other end of the capacitor, and one end of the capacitor. And a gate positioned on the first electrode and the second electrode. Here, the second electrode of the driving transistor and the other end of the capacitor may be electrically connected to each other through the third contact hole Contact3 positioned in the fourth region Area4 as shown in the drawings, but is not limited thereto.

Meanwhile, although not shown, an organic light emitting diode may be positioned above the driving transistor positioned in the third region Area3. This will be described in more detail with reference to FIG. 3B below.

Referring to FIG. 3B, the driving transistor positioned in the third region Area3 is the first electrode 113b positioned in the center of the third region Area3 positioned on the substrate 110 as shown in FIG. 3B. It may include. In addition, one side may contact the first electrode 113b and include a semiconductor layer 111 positioned in a band shape to surround the first electrode 113b. In addition, the second electrode 113a may be in contact with the other side of the semiconductor layer 111 and spaced apart from the first electrode 113b. In addition, the insulating layer 114 may be disposed on the first electrode 113b, the semiconductor layer 111, and the second electrode 113a. In addition, the gate 115 may be disposed on the insulating layer 114 to cover the semiconductor layer 111.

Next, an organic light emitting diode positioned in the third region Area3 is disposed on the planarization layer 116b and connected to the first electrode 115 of the driving transistor exposed through the first contact hole Contact1 ( 117). In addition, the organic light emitting layer 118a, 118b, or 118c may be disposed on the cathode 117. In addition, the display panel may include an anode 119 positioned on the organic light emitting layers 118a, 118b, and 118c and connected to the first power line (not shown).

Here, the first electrode 113b of the driving transistor may have a rectangular shape as shown in FIG. 3A. Accordingly, the semiconductor layer 111 and the second electrode 113a having one side in contact with the first electrode 113b may also have a rectangular shape. Accordingly, as illustrated in FIG. 3B, which is an A-A region of FIG. 3A, regions GA1 and GA2 occupied by the gate 115 of the driving transistor may be formed to cover all of the semiconductor layers 111.

Here, the gate 115 of the driving transistor may be located below the region located in the center region of the semiconductor layer 111 in the outer region of the semiconductor layer 111. In other words, in the gate 115 of the driving transistor, the first impurity region 112b and the semiconductor layer 111 and the second electrode 113a are in contact with the semiconductor layer 111 and the first electrode 113b. The central region located between the second impurity regions 112a may be formed to be adjacent to the lower portion than the outer region.

Here, FIG. 3B is a view in which the AA region, which is a partial region, is cut to help structural understanding of the driving transistor and the organic light emitting diode. However, as shown in FIG. 3B, the subpixel Pixel shown in FIG. The passivation layer 116a may be further disposed on the passivation layer 116a and the planarization layer 116b may be further disposed on the passivation layer 116a.

Unlike FIG. 3B, FIG. 4B is a view cut to B-B based on the first contact hole Contact1 of the third area Area3 of FIG. 4A.

Referring to FIG. 4B, the subpixel Pixel further includes a passivation layer 116a disposed on the gate 115 and a planarization layer 116b positioned on the passivation layer 116a, and includes an insulating layer 114 and a passivation layer ( 116a and the planarization layer 116b may include a first contact hole Contact1 patterned to expose the first electrode 113b in the center area of the third area Area3.

As described above, the first contact hole Contact1 may be formed for electrical connection between the first electrode 113b of the driving transistor and the cathode 117 of the organic light emitting diode.

As a result, the organic light emitting diode positioned in the third region Area3 is positioned on the planarization layer 116b and exposed through the first contact hole Contact1 as shown in FIG. 3B. The cathode 117 connected to the 113b, the organic light emitting layers 118a, 118b and 118c disposed on the cathode 117, and the first power wiring (not shown) located on the organic light emitting layers 118a, 118b and 118c. The anode 119 connected to) may be formed in sequence.

3A and 4A, the cathode 117 of the organic light emitting diode described above may include the first electrode 113b, the semiconductor layer 111, and the second electrode of the driving transistor on the planarization layer 116b. May be positioned to cover all of 113a).

Herein, the structure of the organic light emitting layer illustrated in FIG. 4B described above may be described in more detail.

“118a” included in the organic light emitting layers 118a, 118b, and 118c may be a lower common layer, “118b” may be a light emitting layer, and “118c” may be an upper common layer.

Here, the lower common layer 118a may include an electron injection layer and an electron transport layer, and the upper common layer 118c may include a hole injection layer and a hole transport layer.

The electron injection layer included in the lower common layer 118a serves to facilitate the injection of electrons, and may use Alq3 (tris (8-hydroxyquinolino) aluminum), PBD, TAZ, spiro-PBD, BAlq, or SAlq. It is not limited to this.

The electron injection layer may form an organic material and an inorganic material constituting the electron injection layer by vacuum deposition.

The electron transport layer included in the lower common layer 118a serves to facilitate electron transport and is selected from the group consisting of Alq3 (tris (8-hydroxyquinolino) aluminum), PBD, TAZ, spiro-PBD, BAlq, and SAlq. It may be made of any one or more, but is not limited thereto.

The electron transport layer may be formed using an evaporation method or a spin coating method. The electron transport layer may also serve to prevent holes injected from the cathode 117 from passing through the emission layer 118b to the anode 119. In other words, it may serve as a hole blocking layer to efficiently bond holes and electrons in the emission layer.

The hole injection layer included in the upper common layer 118c may play a role of smoothly injecting holes from the anode 119 into the light emitting layer 118b, and may include cupper phthalocyanine (CuPc) and PEDOT (poly (3,4)). It may consist of one or more selected from the group consisting of -ethylenedioxythiophene), PANI (polyaniline) and NPD (N, N-dinaphthyl-N, N'-diphenyl benzidine), but is not limited thereto.

The hole injection layer described above may be formed using an evaporation method or a spin coating method, but is not limited thereto.

The hole transport layer included in the upper common layer 118c serves to facilitate the transport of holes, NPD (N, N-dinaphthyl-N, N'-diphenyl benzidine), TPD (N, N'-bis- ( 3-methylphenyl) -N, N'-bis- (phenyl) -benzidine), s-TAD and MTDATA (4,4 ', 4 "-Tris (N-3-methylphenyl-N-phenyl-amino) -triphenylamine) It may be made of one or more selected from the group consisting of, but is not limited thereto.

The hole transport layer may be formed using an evaporation method or a spin coating method, but is not limited thereto.

As described above, the hole injection layer or the electron injection layer may further include an inorganic material, the inorganic material may further include a metal compound. The metal compound may include an alkali metal or an alkaline earth metal. Metal compound including an alkali metal or alkaline earth metal LiQ, LiF, NaF, KF, RbF, CsF, FrF, BeF 2, MgF 2, CaF 2, SrF 2, BaF any one selected from the group consisting of ₂ and RaF ₂ or more But it is not limited thereto.

The inorganic material included in the electron injection layer facilitates hopping of electrons injected from the cathode into the light emitting layer 118b and serves to improve luminous efficiency by balancing holes and electrons injected into the light emitting layer 118b. Can be.

The inorganic material in the hole injection layer may reduce the mobility of holes injected from the anode to the light emitting layer 118b, thereby improving the luminous efficiency by balancing the holes and electrons injected into the light emitting layer 118b.

The light emitting layer 118b described above may be formed of a material emitting red, green, blue, and white light, and may be formed using phosphorescent or fluorescent materials.

When the light emitting layer 118b is red, it includes a host material including carbazole biphenyl (CBP) or mCP (1,3-bis (carbazol-9-yl), and PIQIr (acac) (bis (1-phenylisoquinoline) acetylacetonate Phosphorescent light containing a dopant including any one or more selected from the group consisting of iridium), PQIr (acac) (bis (1-phenylquinoline) acetylacetonate iridium), PQIr (tris (1-phenylquinoline) iridium) and PtOEP (octaethylporphyrin platinum) It may be made of a material, alternatively may be made of a fluorescent material including PBD: Eu (DBM) 3 (Phen) or perylene, but is not limited thereto.

When the light emitting layer 118b is green, the light emitting layer 118b may include a host material including CBP or mCP, and may be made of a phosphor including a dopant material including Ir (ppy) 3 (fac tris (2-phenylpyridine) iridium). Alternatively, the composition may be made of a fluorescent material including Alq3 (tris (8-hydroxyquinolino) aluminum), but is not limited thereto.

When the light emitting layer 118b is blue, the light emitting layer 118b may include a host material including CBP or mCP, and may be formed of a phosphor including a dopant material including (4,6-F2ppy) 2Irpic.

Alternatively, it may be made of a fluorescent material including any one selected from the group consisting of spiro-DPVBi, spiro-6P, distilbenzene (DSB), distriarylene (DSA), PFO-based polymer and PPV-based polymer, but It is not limited.

The structure of the organic light emitting layer is not limited to FIG. 4B, and at least one of the electron injection layer, the electron transport layer, the hole transport layer, and the hole injection layer included in the lower common layer 118a and the upper common layer 118c may be omitted. It may be.

Hereinafter, a method of manufacturing an organic light emitting display device according to an embodiment of the present invention will be described. However, the cross-sectional view taken up to B-B of FIG. 4A described above will be mainly described in order to increase the ease of explanation, but also refer to FIGS. 3A to 4A for better understanding.

5A through 5C are schematic process diagrams for describing a method of manufacturing an organic light emitting display device according to an embodiment of the present invention.

In the method of manufacturing an organic light emitting display device according to an exemplary embodiment of the present invention, as shown in FIG. 3A or FIG. 4A, the first area Area1 and the first area in the subpixel Pixel on the substrate 110 are formed. The second area Area2 and the third area Area3 are defined.

Thereafter, a switching transistor is formed in the first area Area1. A capacitor is formed in the second area Area2. A driving transistor is formed in the third region Area3.

However, the steps of forming the switching transistor, the capacitor, and the driving transistor are provided for the sake of understanding by dividing the first area (Area1), the second area (Area2), and the third area (Area3) by different processes. Since this is not the case, the description is given in the form of adding description to the process of the driving transistor section below.

As shown in FIG. 5A, the substrate 110 is prepared. The substrate 110 may be made of glass, plastic, metal, or the like, and although not shown, a buffer layer may be positioned on the substrate 110.

The semiconductor layer 111 is formed in a band shape on the substrate 110. The semiconductor layer 111 may include amorphous silicon or crystallized polycrystalline silicon. The semiconductor layer 111 may include a first impurity region 112b and a second impurity region 112a including p-type or n-type impurities.

A rectangular first electrode 113b is formed in the center of the third region Area3 so as to contact one side of the semiconductor layer 111, and is in contact with the other side of the semiconductor layer 111 and spaced apart from the first electrode 113b. The second electrode 113a is formed. One end of the capacitor may be formed in the second area Area2, and the second electrode and the first electrode of the switching transistor extending from one end of the capacitor and one end of the capacitor may be formed in the first area Area1.

The first and second electrodes 113b and 113a may be formed of a single layer or multiple layers. When the first electrode and the second electrode 113b, 113a are a single layer, molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) ) And copper (Cu) may be made of any one or an alloy thereof. In addition, when the first electrode and the second electrodes 113b and 113a are multilayered, a double layer of molybdenum / aluminum-neodymium and a triple layer of molybdenum / aluminum / molybdenum or molybdenum / aluminum-neodymium / molybdenum may be used.

As such, the first electrode 113b and the second electrode 113a may be formed, and at least one end of the data line, the first electrode of the switching transistor, and the capacitor may be formed.

Meanwhile, the data line positioned in the non-pixel area except for the sub-pixel area may be formed as a single layer or multiple layers. If the data wiring is a single layer, in the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) It may be made of any one or an alloy thereof. In addition, when the data line is a multilayer, it may be composed of a double layer of molybdenum / aluminum-neodymium, a molybdenum / aluminum / molybdenum, or a triple layer of molybdenum / aluminum-neodymium / molybdenum.

Next, as illustrated in FIG. 5B, an insulating layer 114 is formed on the first electrode 113b, the semiconductor layer 111, and the second electrode 113a positioned on the substrate 110. The insulating layer 114 may be a silicon oxide layer SiOx, a silicon nitride layer SiNx, or a multilayer thereof, but is not limited thereto.

The gate 115 is formed on the insulating film 114 to cover the semiconductor layer 111. In this case, the gate 115 may be located below the region located in the central region of the semiconductor layer 111 in the outer region of the semiconductor layer 111.

Here, the gate 115 is made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) It may be made of any one or an alloy thereof. In addition, the gate 115 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multilayer made of any one or alloys thereof. In addition, the gate 115 may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum, but is not limited thereto.

Meanwhile, the gate 115 may be formed and the other end of the gate and the capacitor of the switching transistor may be formed, but is not limited thereto. Here, the gate of the switching transistor may be patterned to be connected to the scan line, and the other end of the capacitor may be patterned to be connected to the second power line.

In this case, the scan wirings positioned in the non-pixel regions except for the sub-pixels include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium ( Nd) and copper (Cu) may be made of any one or an alloy thereof. In addition, the scan wiring is any one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multilayer of one or an alloy thereof. In addition, the scan line may be a double layer of molybdenum / aluminum-neodymium or molybdenum / aluminum, but is not limited thereto.

Next, as shown in FIG. 5C, the passivation layer 116a is formed on the gate 115 and the planarization layer 116b is formed on the passivation layer 116a. In this case, the insulating layer 114, the passivation layer 116a, and the planarization layer 116b may form a first contact hole Contact1 that is exposed to expose the first electrode 113b in the center region of the third region Area3. have.

Here, the first contact hole Contact1 may be formed for electrical connection between the first electrode 113b of the driving transistor and the cathode 117 of the organic light emitting diode.

Thereafter, the cathode 117 of the organic light emitting diode is formed on the planarization layer 116b to be connected to the first electrode 113b of the driving transistor. Although not shown, an anode connected to the organic light emitting layer and the first power line may be sequentially formed on the cathode 117.

As described above, when the upper emission type inverted organic light emitting display device has the same structure as the exemplary embodiment of the present invention, the phenomenon that external light is incident on the semiconductor layer region of the driving transistor can be prevented by using the driving transistor. It is possible to prevent the problem that the output saturation characteristics of the deterioration. In addition, the number of masks used when manufacturing the top emission type inverted organic light emitting display device may be reduced.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

1 is a schematic plan view of an organic light emitting display device according to an embodiment of the present invention;

2 is an exemplary circuit configuration of a subpixel.

3A is a plan view of a subpixel;

3B is a cross-sectional view taken along the line A-A of FIG. 3A.

4A is a plan view of a subpixel;

4B is a cross-sectional view taken along the line B-B in FIG. 4A.

5A through 5C are schematic process diagrams for describing a method of manufacturing an organic light emitting display device according to an embodiment of the present invention.

<Explanation of symbols on main parts of the drawings>

110 substrate 111 semiconductor layer

113a: second electrode 113b: first electrode

114: insulating film 115: gate

116a: protective film 116b: planarization film

117: cathode 119: anode

Claims (10)

A subpixel including a switching transistor positioned in a first region defined on a substrate, a capacitor positioned in a second region, a driving transistor positioned in a third region, and an organic light emitting diode, The driving transistor, A first electrode positioned at the center of the third region, a semiconductor layer in which one side contacts the first electrode, and is positioned in a band so as to surround the first electrode, and the other side of the semiconductor layer is in contact with the first electrode An organic light emitting display including a second electrode spaced apart from an electrode, an insulating layer positioned over the first electrode, the semiconductor layer, and the second electrode, and a gate positioned over the insulating layer to cover the semiconductor layer Device. The method of claim 1, The first electrode of the driving transistor, Rectangular organic light emitting display device. The method of claim 1, The sub pixel is, Further comprising a passivation layer positioned on the gate and a planarization layer positioned on the passivation layer, The insulating layer, the passivation layer, and the planarization layer include a first contact hole patterned to expose the first electrode in a central region of the third region. The method of claim 3, The gate of the driving transistor, And a region located in the center region of the semiconductor layer is lower than a region located in the outer region of the semiconductor layer. The method of claim 3, The organic light emitting diode, A cathode on the planarization layer and connected to the first electrode of the driving transistor exposed through the first contact hole, an organic emission layer on the cathode, and an organic light emitting layer on the organic light emitting layer and on a first power line An organic light emitting display device comprising a connected anode. The method of claim 5, The cathode of the organic light emitting diode, The organic light emitting display device is disposed on the planarization layer so as to cover all of the first electrode, the semiconductor layer, and the second electrode of the driving transistor. The method of claim 1, The switching transistor, A first electrode connected to a data line on the substrate, a second electrode surrounded by three surfaces of the first electrode, the insulating film positioned to cover the first electrode and the second electrode, and on the insulating film An organic light emitting display device, the organic light emitting display device comprising a gate connected to a scan line. The method of claim 1, The capacitor, One end connected to a gate of the driving transistor and extending to the second electrode of the switching transistor, the insulating film positioned to cover the one end, and a second electrode of the driving transistor connected to a second power line on the insulating film. An organic light emitting display device comprising a second end connected to the organic light emitting display device. Defining a first region, a second region, and a third region in a subpixel located on the substrate; And Forming a switching transistor in the first region, forming a capacitor in the second region, and forming a driving transistor in the third region, The driving transistor, A rectangular first electrode positioned at the center of the third region, a semiconductor layer positioned in a rectangular band so that one side contacts the first electrode and surrounds the first electrode, and a second side of the semiconductor layer And a second electrode spaced apart from the first electrode, an insulating film positioned over the first electrode, the semiconductor layer, and the second electrode, and a gate positioned over the insulating film to cover the semiconductor layer. A method of manufacturing an organic light emitting display device. The method of claim 9, The gate of the driving transistor, And a region located in the center region of the semiconductor layer is lower than a region located in the outer region of the semiconductor layer.

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