KR20090047775A - A nonvolatile memory device - Google Patents

Abstract

The present invention provides a nonvolatile memory device. The device includes a tunnel insulating film formed on a semiconductor substrate, a charge storage film formed on the tunnel insulating film, a blocking insulating film formed on the charge storage film, and a control gate electrode formed on the blocking insulating film, wherein the blocking insulating film is formed by successive stacking. And a first blocking insulating film, a second blocking insulating film, and a third blocking insulating film, wherein an energy band gap of the second blocking insulating film is greater than an energy band gap of the first blocking insulating film and the third blocking insulating film.

Flash memory, charge storage film, blocking insulating film

Description

Nonvolatile Memory Device {A NONVOLATILE MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly to nonvolatile memory devices.

The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile memory device.

A nonvolatile memory device is a semiconductor device in which stored information is maintained without disappearing even when power supply is interrupted. A flash memory device, which is a representative nonvolatile memory device, may store information depending on whether charge is charged in a floating gate interposed between a control gate and a semiconductor substrate.

In the case of an erase operation of a nonvolatile flash memory having a SONOS (Doped Silicon / Oxide / Nitride / Oxide / Silicon) structure and a floating gate, a back tunneling current flows to decrease the speed of the erase operation. Seems to be characteristic. In an erase operation, it is necessary to reduce the back tunneling current and to increase the retention time of the nonvolatile memory device in a programmed state.

One object of the present invention is to provide a nonvolatile memory device having a reduced back tunneling current.

Another object of the present invention is to provide a nonvolatile memory device having an increased retention time.

A nonvolatile memory device of the present invention includes a tunnel insulating film formed on a semiconductor substrate;

A charge storage film formed on the tunnel insulating film, a blocking insulating film formed on the charge storage film, and a control gate electrode formed on the blocking insulating film,

The blocking insulating film may include a first blocking insulating film, a second blocking insulating film, and a third blocking insulating film that are sequentially stacked, and an energy band gap of the second blocking insulating film may include energy of the first blocking insulating film and the third blocking insulating film. Greater than the bandgap.

In one embodiment of the present invention, the charge storage layer may be an insulator or a conductive floating gate holding a charge trap site.

In one embodiment of the present invention, the dielectric constant of the second blocking insulating film may be less than the dielectric constant of the first blocking insulating film and the third blocking insulating film.

In one embodiment of the present invention, the trap density of the second blocking insulating film may be smaller than the trap density of the first blocking insulating film and the third blocking insulating film.

In example embodiments, the blocking insulating layer may further include at least one fourth blocking insulating layer such that materials having different energy band gaps are alternately disposed on the third blocking insulating layer.

In one embodiment of the present invention, the first blocking insulating film and the third blocking insulating film may include at least one of a metal oxide film, a metal nitride film, and a metal oxynitride film.

In one embodiment of the present invention, the second blocking insulating film may include at least one of a silicon oxide film, a metal oxide film, a metal nitride film, and a metal oxynitride film.

In one embodiment of the present invention, the charge storage layer may include at least one of silicon nitride film, metal quantum dot, silicon quantum dot, metal, doped silicon, doped germanium.

In one embodiment of the present invention, the floating gate may include at least one of N-type conductive polysilicon, P-type conductive polysilicon, metal, doped germanium.

In one embodiment of the present invention, the metal may include at least one of a pure metal and a metal mixture.

In one embodiment of the present invention, the control gate electrode may have a structure of a barrier metal and a high work function metal stacked in sequence.

In one embodiment of the present invention, the high work function metal may have a work function of 4.5 eV or more.

In one embodiment of the present invention, the barrier metal may include at least one of a metal nitride film, a silicon nitride film, a combination thereof to prevent a reaction between the high work function metal and the blocking insulating film.

In example embodiments, the control gate electrode may further include at least one of a high work function metal and a doped polysilicon interposed between the barrier metal and the blocking insulating layer.

In one embodiment of the present invention, the control gate electrode may comprise at least one of doped silicon and metal, pure metal, and metal containing one after another.

In one embodiment of the present invention, the first blocking insulating film may be made of the same material as the third blocking insulating film and may have the same energy band gap.

 According to the present invention, a region composed of a plurality of blocking insulating films and having a large energy band gap can be inserted in the middle of the blocking insulating film to extend the retention time of the nonvolatile memory device, and reduce the back tunneling current during the erase operation. You can increase the speed.

In order to achieve the above technical problem, the present invention provides a nonvolatile memory device.

A charge trap flash memory includes a charge storage film that is an insulator interposed between a control gate and a semiconductor substrate. A tunnel insulating layer may be provided between the charge storage layer and the semiconductor substrate, and a blocking insulating layer may be provided between the charge storage layer and the control gate. The charge storage film has a trap site capable of storing charge, and whether charge is charged in the capture site determines the information stored in the charge capture flash memory.

The charge trap flash memory has an advantage of reducing the parasitic capacitance and the coupling coefficient of the control gate compared to the flash memory having the floating gate. In addition, the charge trapping flash memory must remain stored in the charge storage film for a predetermined time (retention time).

During an erase operation of a charge trapping flash memory having a SONOS (Silicon / Oxide / Nitride / Oxide / Silicon) cell structure, a back tunneling current may be generated through the blocking insulating layer to decrease the erase operation speed. In order to solve this problem, an electric field applied to the high-k dielectric layer may be reduced by using a high-k dielectric layer as the blocking insulating layer. Specifically, a charge trapping flash memory having a TANOS (TaN / Al 2 O 3 / Nitride / Oxide / Silicon) cell structure has been proposed. The back tunneling current flowing through the high dielectric insulating film can adjust the amount of FN tunneling by adjusting the energy band appropriately.

As the aluminum oxide film (Al 2 O 3) is used as the high dielectric film, the electric field applied to the high dielectric film may be reduced, and thus the back tunneling current flowing through the high dielectric film may be reduced. In addition, the back tunneling current may be further reduced by using a conductive material (eg, TaN, WN, TiN, CoSix, polysilicon) having a high work function of 4.5 eV or more as the control gate electrode. .

On the other hand, the high dielectric insulating film as the blocking insulating film may include a bulk trap density, the bulk trap density can reduce the retention time of the charge storage film, it is possible to reduce the reliability of the charge trapping flash memory. To overcome this, a plurality of blocking insulating films are used. Specifically, the back tunneling current may be adjusted by appropriately adjusting the energy band gaps of the plurality of blocking insulating layers.

A flash memory having a floating gate structure includes a charge storage layer, which is a conductor interposed between a control gate and a semiconductor substrate. A tunnel insulating layer may be provided between the charge storage layer and the semiconductor substrate, and a blocking insulating layer may be provided between the charge storage layer and the control gate. The charge storage layer may include a floating gate. The floating gate may be a conductive material. Whether or not charge is stored in the floating gate determines information stored in the flash memory. The back tunneling current can be adjusted by appropriately adjusting the energy band gaps of the plurality of blocking insulating films.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed contents may be thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

1A and 1B illustrate a NAND nonvolatile memory device according to example embodiments. FIG. 1B is a cross-sectional view taken along line II ′ of FIG. 1A.

1A and 1B, a NAND nonvolatile memory device according to embodiments of the present invention includes a semiconductor substrate 100 having a cell region. An isolation layer 300 is disposed on the semiconductor substrate 100. The device isolation layer 100 defines active regions ACT. The active regions ACT are arranged side by side in a first direction. A string select line SSL and a ground select line GSL cross the active domains ACT side by side, and a plurality of word lines WL are between the string select line SSL and the ground select line GSL. It traverses side by side the active regions of ACT. The string select line SSL, the ground select line GSL, and the word lines WL extend side by side in a second direction perpendicular to the first direction. The string select line SSL, the word lines WL, and the ground select line GSL may be included in a cell string group. The cell string group may be repeatedly arranged in mirror symmetry along the first direction.

Impurity regions 200 corresponding to a source and a drain may be disposed in the string selection line SSL, the plurality of word lines WL, and the active regions ACT on both sides of the ground selection line GSL. Can be. The impurity region 200 on both sides of the word line WL and the word line WL constitutes a cell transistor, and the impurity region 200 on both sides of the ground select line GSL and the ground select line GSL Configure the ground select transistor. The string select line SSL and the impurity region 200 at both sides of the string select line SSL constitute a string select transistor.

The word line WL includes a tunnel insulation layer 110, a charge storage layer 120, a blocking insulation layer 150, and a control gate electrode 160 that are sequentially stacked on the semiconductor substrate 100. A hard mask pattern (not shown) may be disposed on the control gate electrode 160. The ground select line GSL and the string select select line SSL may have the same structure as the word line WL. However, the line widths of the string select line SSL and the ground select line GSL may be different from the line widths of the word line WL. In particular, the line widths of the string select line SSL and the ground select line GSL may be larger than that of the word line WL. The layers in the ground and string select lines GSL and SSL corresponding to the tunnel insulating layer 110, the charge storage layer 120, and the blocking insulating layer 150 may be used as gate insulating layers of the ground and string select transistors. .

The tunnel insulating layer 110, the charge storage layer 120, and the blocking insulating layer 150 may extend onto an adjacent semiconductor substrate. The plurality of word lines WL may share the tunnel insulating layer 110, the charge storage layer 120, and the blocking insulating layer 150. In addition, the ground and string select lines GSL and SSL may also share the extended tunnel insulation layer 110, the charge storage layer 120, and the blocking insulation layer 150. The cell spacers (not shown) may be disposed on sidewalls of the control gate electrode 160. The cell spacer (not shown) may be positioned on the extended blocking insulating layer 150.

The blocking insulating layer 150 may include a first blocking insulating layer 150a, a second blocking insulating layer 150b, and a third blocking insulating layer 150c.

2A and 2B are diagrams illustrating a NOR nonvolatile memory device according to example embodiments. FIG. 2B is a cross-sectional view taken along the line III-III ′ of FIG. 1A.

2A and 2B, a NOR nonvolatile memory device according to example embodiments of the inventive concept includes a semiconductor substrate 100 having a cell region. The device isolation layer 300 may include a semiconductor substrate 100. ) Is placed. The device isolation layer 300 defines active regions 500, 510, and 520. The first active regions 500 are arranged side by side in the first direction. Source strapping active regions 510 are regularly arranged in the first direction between the first active regions 500. Second active regions 520 crossing the first active region 500 are arranged side by side in a second direction. The second active regions 520 serve as source lines.

A pair of word lines WL are disposed to cross the upper portions of the first active regions 500 and the source strapping active regions 510 and travel in a second direction. Active regions located on both sides of the pair of word lines become drains of the transistor, and active regions between the pair of word lines become the source of the transistor. The drain-in of the transistor is electrically connected through a bit line and a bit line contact plug 540.

In addition, the sources of the transistors are electrically connected to neighboring sources in a second direction through the second active region 520. Thus, the second active region 520 serves as a source line. A source contact 530 is formed at a position where the second active region 520 and the source strapping active region 510 cross each other.

The word line WL includes a tunnel insulation layer 110, a charge storage layer 120, a blocking insulation layer 150, and a control gate electrode 160 that are sequentially stacked on the semiconductor substrate 100.

The tunnel insulation layer 110, the charge storage layer 120, and the blocking insulation layer 150 may extend in a second direction, and the word line WL may be formed in the tunnel insulation layer 110 and the charge storage layer 120. , And the blocking insulating layer 150 may be shared. The spacer (not shown) may be positioned on the extended blocking insulating layer 150.

The blocking insulating layer 150 may include a first blocking insulating layer 150a, a second blocking insulating layer 150b, and a third blocking insulating layer 150c.

FIG. 3 is a cross-sectional view taken along line II-II ′ of FIG. 1A for describing a charge trapping nonvolatile memory device according to an exemplary embodiment of the present invention. 4A to 4D are diagrams illustrating a flat band energy band diagram of a nonvolatile memory device according to an embodiment of the present invention.

3, 4A to 4D, the device includes a tunnel insulating film 110 formed on the semiconductor substrate 100, a charge storage film 120 formed on the tunnel insulating film 110, and the charge storage film ( A blocking insulating layer 150 formed on the blocking insulating layer 150 and a control gate electrode 160 formed on the blocking insulating layer 150 are included. In addition, an isolation layer 300 defining an active region ACT may be formed on the semiconductor substrate 100. The charge storage layer 120 may not be separated for each unit cell. The blocking insulating layer 150 may include a first blocking insulating layer 150a, a second blocking insulating layer 150b, and a third blocking insulating layer 150c that are sequentially stacked. The first blocking insulating layer 150a and the third blocking insulating layer 150c may be made of the same material. In addition, an energy band gap E _{g2 of} the second blocking insulating layer 150b is an energy band gap E _g1 , E _{g3 of} the first blocking insulating layer 150a and the third blocking insulating layer 150c. Greater than) An isolation layer 300 is disposed on the semiconductor substrate 100 to define active regions ACT. This device may have a structure in which the charge storage layer 120 is not separated for each unit cell.

The semiconductor substrate 100 may include one selected from the group consisting of a single crystal silicon film, a silicon on insulator (SOI), a silicon film on a silicon germanium (SiGe) film, a silicon single crystal film on an insulating film, and a polysilicon film on an insulating film. have.

The tunnel insulating layer 110 may include at least one of a silicon oxide layer, a silicon oxynitride layer (SiON), and a high dielectric material. The high dielectric material may include at least one of an aluminum oxide layer (Al 2 O 3), a hafnium oxide layer (HfO 2), a hafnium aluminum oxide layer (HfAlO), a hafnium silicon oxide layer (HfSiO), a zirconium oxide layer (ZrO 2), or a tantalum oxide layer (Ta 2 O 5). . The silicon oxide film may be a thermal oxide film.

The charge storage layer 120 may be formed of a material having traps capable of storing charge. The charge storage layer 120 may include a dielectric layer. The charge storage layer 120 may include at least one of a silicon nitride film, a metal quantum dot, a silicon quantum dot, a metal, doped silicon, and doped germanium. The metal may comprise at least one of pure metals and metal mixtures. The charge storage layer 120 may include nano crystalline silicon, nano crystalline silicon germanium, nano crystalline metal, german quantum dot, and metal quantum dot. It may include one or a stacked structure thereof selected from the group having a metal quantum dot, a silicon quantum dot. The charge storage layer 120 may have metal trap sites through metal doping. Alternatively, the charge storage layer 120 may form a deep trap site within an energy band of the charge storage layer through a wet oxidation process after formation of the charge storage layer.

The blocking insulating layer 150 includes a first blocking insulating layer 150a, a second blocking insulating layer 150b, and a third blocking insulating layer 150. The first blocking insulating layer 150a is disposed on the charge storage layer 120, the second blocking insulating layer 150b is disposed on the first blocking insulating layer 150a, and the third blocking insulating layer 150c. ) Is disposed on the second blocking insulating layer 150b. The first blocking insulating layer 150a and the third blocking insulating layer 150c are made of the same material. In addition, the energy band gaps E _g1 and E _{g3 of} the first blocking insulating layer 150a and the third blocking insulating layer 150c are smaller than the energy band gap E _g2 of the second blocking insulating layer 150b. . The blocking insulating layer 150 may have a dielectric constant and a charge trap. The charge trap density of the blocking insulating layer 150 may increase in proportion to the dielectric constant.

  In an embodiment, the dielectric constant of the second blocking insulating layer 150b may be smaller than that of the first blocking insulating layer 150a and the third blocking insulating layer 150c and the second blocking insulating layer 150b. ) May be smaller than the charge trap density of the first blocking insulating layer 150a and the third blocking insulating layer 150c. The charge trap densities of the first blocking insulating layer 150a, the second blocking insulating layer 150b, and the third blocking insulating layer 150c may be proportional to the dielectric constant.

The first blocking insulating layer 150a and the third blocking insulating layer 150c may include at least one of a metal oxide film, a metal nitride film, and a metal oxynitride film. The metal oxide layer may include at least one of a hafnium silicon oxide layer (HfSiO), a zirconium oxide layer (ZrO 2), a hafnium aluminum oxide layer (HfAlO), a hafnium oxide layer (HfO 2), and an aluminum oxide layer (Al 2 O 3).

The second blocking insulating layer 150b may include at least one of a silicon oxide film, a metal oxide film, a metal nitride film, and a metal oxynitride film. The metal oxide layer may include at least one of a hafnium silicon oxide layer (HfSiO), a zirconium oxide layer (ZrO 2), a hafnium aluminum oxide layer (HfAlO), a hafnium oxide layer (HfO 2), and an aluminum oxide layer (Al 2 O 3). May be formed by ALD, CVD, PVD processes.

After forming the first blocking insulating film 150a, the second blocking insulating film 150b, and the third blocking insulating film 150c, an annealing process or a plasma processing process including at least one of O 2, N 2 and NH 3 is performed. This can be done. For example, the charge trap density of the first blocking insulating layer 150a, the second blocking insulating layer 150b, and the third blocking insulating layer 150c may be reduced by the above process.

 The control gate electrode 160 may be a conductive material having a large work function of 4.5 eV or more. For example, it may include at least one of TaN, polysilicon, W, WN, TiN, and CoSix. The control gate electrode 160 may include another conductive material. Specifically, the control gate electrode 160 may have a structure of a barrier metal and a high work function metal that are sequentially stacked. The high work function metal may have a work function of 4.5 eV or more. The barrier metal may include at least one of a metal nitride film, a silicon nitride film, and a combination thereof that prevents a reaction between the high work function metal and the blocking insulating film. The control gate electrode 160 may further include at least one of a high work function metal and a doped polysilicon interposed between the barrier metal and the blocking insulating layer 150. The control gate electrode 160 may include at least one of a doped silicon and a metal, a pure metal, and a metal content that are sequentially stacked.

Referring to FIG. 4A, the energy band gap E _g2 of the second blocking insulating layer 150b is larger than the band gaps E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c. The conduction band of the second blocking insulating layer 150b is higher than the conduction bands of the first and third blocking insulating layers 150a and 150c, and the valence band of the second blocking insulating layer 150b is the first and the second. 3 may be higher than the valence band of the blocking insulating layers 150a and 150c.

Referring to FIG. 4B, the energy band gap E _g2 of the second blocking insulating layer 150b is larger than the band gaps E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c. The conduction band of the second blocking insulation film 150b is higher than the conduction bands of the first and third blocking insulation films 150a and 150c, and the valence band of the second blocking insulation film 150b is the first and third blocking insulation film 150a. It may be lower than the valence band of 150c.

Referring to FIG. 4C, the energy band gap E _g2 of the second blocking insulating layer 150b is larger than the band gaps E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c. The conduction band of the second blocking insulation film 150b is lower than the conduction bands of the first and third blocking insulation films 150a and 150c, and the valence band of the second blocking insulation film 150b is the first and third blocking insulation film 150a. It may be lower than the valence band of 150c.

Referring to FIG. 4D, the blocking insulating layer 150 may further include a fourth blocking insulating layer 150d to alternate two materials having different energy band gaps. The fourth blocking insulating layer 150d is made of the same material as the second blocking insulating layer 150b. Accordingly, the energy band gap E _g4 of the fourth blocking insulating film is equal to the energy band gap E _g2 of the second blocking insulating film. In addition, according to a modified embodiment of the present invention, the blocking insulating film 150 may further include the fourth blocking insulating film 150d and the fifth blocking insulating film (not shown). The fourth blocking insulating layer 150d may be formed of the same material as the second blocking insulating layer 150b, and the fifth blocking insulating layer 150d may be formed of the same material as the first blocking insulating layer 150a.

FIG. 5 is a diagram illustrating an energy band diagram when a negative erase voltage V ₀ is applied to a nonvolatile memory device according to the present invention. However, the charge stored in the charge storage film 120 is a diagram illustrating a state in which all of the charges are removed by the erase voltage V ₀ applied from the outside.

Specifically, when a negative erase voltage is applied to the control gate electrode 160 with respect to the semiconductor substrate 100, an electric field is generated in the tunnel insulating film 110, the charge storage film 120, and the blocking insulating film 150, respectively. . Each electric field can be calculated by the capacitor voltage distribution model. The back tunneling current flowing through the blocking insulating layer 150 may depend on the electric field of the blocking insulating layer 150. Specifically, the back tunneling current may be adjusted by adjusting the structure, band gap, thickness, and dielectric constant of the blocking insulating layer 150.

Each electric field can be given by

은 유전율을 의미한다. Here, the subscripts i and j may be 1 to 5. Subscript 1 refers to the tunnel insulating film 110, subscript 2 to the charge storage film 120, subscript 3 to the first blocking insulating film 150a, subscript 4 to the second blocking insulating film 150b, subscript 5 to the third blocking It means the insulating film 150d. t means thickness,

Means permittivity.

For example, when the thicknesses of the first blocking insulating film 150a and the third blocking insulating film 150c having a large dielectric constant are increased, the respective electric fields of the first blocking insulating film 150a and the third blocking insulating film 150c decrease. You can. However, the first blocking insulating layer 150a and the third blocking insulating layer 150c may have a high charge trap density due to a high dielectric constant. In addition, the charges trapped in the trap can easily move to an external electric field. Accordingly, there is a limit in increasing thicknesses of the first blocking insulating film and the third blocking insulating film 150a and 150c having a large dielectric constant.

On the other hand, if the difference between the work function of the third blocking insulating layer 150c and the control gate electrode 160 is increased, the threshold energy for generating the back tunneling phenomenon increases, thereby reducing the back tunneling current. Unlike the present invention, when the energy band gap of the second blocking insulating film 150b is smaller than the energy band gap of the third blocking insulating film 150c and the first blocking insulating film 150c, electrons or holes are formed in the second blocking film. It can accumulate in the energy well of the insulating film 150b. Therefore, the energy band gap of the second blocking insulating layer 150b is preferably larger than the energy band gap of the third blocking insulating layer 150c and the first blocking insulating layer 150a.

According to an embodiment of the present invention, the first blocking insulating layer 150a and the third blocking insulating layer 150c may have a dielectric constant and a trap density greater than that of the second blocking insulating layer 150b. The charge trapped by the first blocking insulating film 150a cannot easily pass through the second blocking insulating film 150b by an external electric field, thereby improving reliability.

FIG. 6 is a cross-sectional view taken along the line II-II 'of FIG. 1A for explaining a floating gate type nonvolatile memory device according to another embodiment of the present invention. In the present embodiment, description of portions overlapping with the embodiments described with reference to FIGS. 3 and 4 will be omitted.

Referring to FIG. 6, the device includes a tunnel insulating film 110 formed on the semiconductor substrate 100, a charge storage film 120 formed on the tunnel insulating film 110, and a blocking formed on the charge storage film 120. An insulating film 150 and a control gate electrode 160 formed on the blocking insulating film 150 are included. In addition, an isolation layer 300 defining an active region ACT may be formed on the semiconductor substrate 100. The charge storage layer 120 may have a structure that is separated for each unit cell.

The charge storage layer 120 may be a floating gate, and the charge storage layer 120 may include a conductive material. The floating gate may include at least one of an N-type conductive polysilicon, a P-type conductive polysilicon, a metal, a doped silicon, and a doped germanium.

The control gate electrode 160 may include at least one of polysilicon, a metal, a metal silicide, a metal compound, and a stacked structure thereof doped with a conductive material.

7A to 7C are diagrams illustrating a flat band energy band diagram of a nonvolatile memory device according to another exemplary embodiment of the present invention. 7A to 7C are energy band diagrams when polysilicon doped with the charge storage layer 120 is used and polysilicon doped with the control gate electrode 160 is used.

Referring to FIG. 7A, the energy band gap E _g2 of the second blocking insulating layer 150b is larger than the band gaps E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c. The conduction band of the second blocking insulating layer 150b is higher than the conduction bands of the first and third blocking insulating layers 150a and 150c, and the valence band of the second blocking insulating layer 150b is the first and the third. It may be higher than the valence bands of the blocking insulating layers 150a and 150c.

Referring to FIG. 7B, the energy band gap E _g2 of the second blocking insulating layer 150b is larger than the band gaps E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c. The conduction band of the second blocking insulation film 150b is higher than the conduction bands of the first and third blocking insulation films 150a and 150c, and the valence band of the second blocking insulation film 150b is the first and third blocking insulation film 150a. It may be lower than the valence band of 150c.

Referring to FIG. 7C, the energy band gap E _g2 of the second blocking insulating layer 150b is larger than the band gaps E _g1 and E _{g3 of} the first and third blocking insulating layers 150a and 150c. The conduction band of the second blocking insulation film 150b is lower than the conduction bands of the first and third blocking insulation films 150a and 150c, and the valence band of the second blocking insulation film 150b is the first and third blocking insulation film 150a. It may be lower than the valence band of 150c.

Referring back to FIG. 7A, according to a modified embodiment of the present invention, the blocking insulating layer 150 may further include a fourth blocking insulating layer (not shown) such that materials having different energy band gaps are alternated. The fourth blocking insulating layer may be made of the same material as the second blocking insulating layer 150b. Accordingly, the energy band gap of the fourth blocking insulating layer may be the same as the energy band gap E _g2 of the second blocking insulating layer. In addition, according to another modified embodiment of the present invention, the blocking insulating film 150 may further include the fourth blocking insulating film and the fifth blocking insulating film (not shown). The fourth blocking insulating film may be made of the same material as the second blocking insulating film 150b, and the fifth blocking insulating film may be made of the same material as the first blocking insulating film 150a.

Meanwhile, according to one embodiment of the present invention, the nonvolatile memory device disclosed in the above embodiments may be included in an electronic system. The electronic system will be described in detail with reference to the drawings.

8 is a block diagram illustrating an electronic system having a nonvolatile memory device according to example embodiments.

Referring to FIG. 9, the electronic system 1300 may include a controller 1310, an input / output device 1320, and a memory device 1330. The controller 1310, the input / output device 1320, and the memory device 1330 are coupled to each other through a bus 1350. The bus 1350 corresponds to a path through which data travels. The controller 1310 may include at least one of at least one microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing functions similar thereto. The input / output device 1320 may include at least one selected from a keypad, a keyboard, a display device, and the like. The memory device 1330 is a device for storing data. The memory device 1330 may store data and / or instructions executed by the controller 1310. The memory device 1330 may include at least one selected from the nonvolatile memory devices described in the above embodiments. The electronic system 3100 may further include an interface 1340 for transmitting data to or receiving data from the communication network. The interface 1340 may be in a wired or wireless form. For example, the interface 1340 may include an antenna or a wired / wireless transceiver.

The electronic system 1300 may be implemented as a mobile system, a personal computer, an industrial computer, or a system that performs various functions. For example, the mobile system may be a personal digital assistant (PDA), a portable computer, a web tablet, a mobile phone, a wireless phone, a laptop computer, a memory card. , A digital music system or an information transmission / reception system. If the electronic system 1300 is a device capable of performing wireless communication, the electronic system 1300 may be used in a communication interface protocol such as a third generation communication system such as CDMA, GSM, NADC, E-TDMA, WCDAM, CDMA2000, etc. Can be.

Next, a memory card according to embodiments of the present invention will be described in detail with reference to the drawings.

9 is a block diagram illustrating a memory card having a nonvolatile memory device according to example embodiments.

Referring to FIG. 9, the memory card 1400 includes a nonvolatile memory device 1410 and a memory controller 1420. The nonvolatile memory device 1410 may store data or read stored data. The nonvolatile memory device 1410 includes at least one of the nonvolatile memory devices disclosed in the embodiments. The memory controller 1420 reads stored data in response to a read / write request of a host, or controls the flash memory device 1410 to store data.

1A and 1B are diagrams illustrating a NAND nonvolatile memory device according to an embodiment of the present invention. FIG. 1B is a cross-sectional view taken along line II ′ of FIG. 1A.

2A and 2B are diagrams illustrating a NOR nonvolatile memory device according to an embodiment of the present invention. FIG. 2B is a cross-sectional view taken along the line III-III ′ of FIG. 1A.

FIG. 3 is a cross-sectional view taken along line II-II 'of FIG. 1A to illustrate a nonvolatile memory device according to an embodiment of the present invention.

4A to 4D are diagrams illustrating a flat band energy band diagram of a nonvolatile memory device according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating an energy band diagram when a negative erase voltage V ₀ is applied to a nonvolatile memory device according to the present invention.

FIG. 6 is a cross-sectional view taken along line II-II 'of FIG. 1A to illustrate a nonvolatile memory device according to an embodiment of the present invention.

 7A to 7C are diagrams illustrating a flat band energy band diagram of a nonvolatile memory device according to an embodiment of the present invention.

8 is a block diagram illustrating an electronic system having a nonvolatile memory device according to example embodiments.

9 is a block diagram illustrating a memory card having a nonvolatile memory device according to example embodiments.

Claims (16)

A tunnel insulating film formed on the semiconductor substrate; A charge storage layer formed on the tunnel insulating layer; A blocking insulating film formed on the charge storage film; And It includes a control gate electrode formed on the blocking insulating film, The blocking insulating film includes a first blocking insulating film, a second blocking insulating film, and a third blocking insulating film that are sequentially stacked, The energy band gap of the second blocking insulating film is greater than the energy band gap of the first blocking insulating film and the third blocking insulating film. The method of claim 1, And the charge storage layer is an insulator or a conductive floating gate that holds charge trap sites. The method of claim 2, And a dielectric constant of the second blocking insulating layer is smaller than that of the first blocking insulating layer and the third blocking insulating layer. The method of claim 2, And a trap density of the second blocking insulating film is smaller than a trap density of the first blocking insulating film and the third blocking insulating film. The method of claim 2, The blocking insulating film  And at least one fourth blocking insulating layer on the third blocking insulating layer such that materials having different energy band gaps are alternated. The method of claim 2, And the first blocking insulating film and the third blocking insulating film include at least one of a metal oxide film, a metal nitride film, and a metal oxynitride film. The method of claim 2, And the second blocking insulating film includes at least one of a silicon oxide film, a metal oxide film, a metal nitride film, and a metal oxynitride film. The method of claim 2,  And the charge storage layer comprises at least one of a silicon nitride layer, a metal quantum dot, a silicon quantum dot, a metal, a heavily doped silicon, and a doped germanium. The method of claim 2, The floating gate includes at least one of an N-type conductive polysilicon, a P-type conductive polysilicon, a metal, and a doped germanium. The method of claim 8, And said metal comprises at least one of a pure metal and a metal mixture. The method of claim 2, The control gate electrode A nonvolatile memory device comprising a barrier metal and a high work function metal stacked one after another. The method of claim 11, The high work function metal has a work function of 4.5 eV or more. The method of claim 11, And the barrier metal includes at least one of a metal nitride film, a silicon nitride film, and a combination thereof that prevents a reaction between the high work function metal and the blocking insulating film. The method of claim 11, And the control gate electrode further comprises at least one of a high work function metal and a doped polysilicon interposed between the barrier metal and the blocking insulating layer. The method of claim 2, And the control gate electrode comprises at least one of doped silicon and a metal, a pure metal, and a metal containing one after another. The method of claim 1, And the first blocking insulating layer is made of the same material as the third blocking insulating layer, and has the same energy band gap.

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