KR20090046841A - Power Management in Data Processing Devices with Masters and Slaves - Google Patents

Abstract

An apparatus 2, such as an integrated circuit, comprising a master unit 8, 10 and a slave unit 6, 18, 20 connected by an interconnect 14 is disclosed. In addition to the usual data signal 22 and address signal 24 delivered in a transaction, a usage signal 26 is also specified which specifies the time interval until the next transaction is delivered to the slave unit. The local slave power controller 34 switches to the low power mode in response to such usage signal 26 and returns to the mode of operation at the appropriate time to respond to the next transaction that must be received first.

Interconnect, Master, Slave, Transaction, Data Processing Unit

Description

POWER MANAGEMENT IN A DATA PROCESSING DEVICE HAVING MASTERS AND SLAVES}

The present invention relates to the field of data processing apparatus. In particular, the present invention relates to the management of power consumption inside such devices.

Power consumption of system-on-chip integrated circuits and devices such as mobile phones and computers is an important concern. Even for non-portable devices, reducing power consumption is important because reducing power consumption reduces costs, simplifies the design of cooling, packaging, and power generation facilities, increasing reliability.

Known power management schemes are divided into two main groups. First and foremost, the most common kind is a heuristic power management scheme, such as idle timeouts, for example, turning off the display after a period of inactivity or down the CPU clock. The second kind is by using a stochastic or markov model, for example, attempting to predict when the device is not in use and stopping it. This kind of approach involves adaptive frequency and voltage scaling controlled at the operating system level.

An overview of known power management approaches is provided in "A Survey of Design Techniques For System Level Dynamic Power Management" by Luca Benini et al, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Volume 8, No. 3, June 2002. You can find it.

The problem with all of the above schemes is that it is easy to induce some power-delay trade off, i.e. these schemes save power but increase latency. Power management is particularly difficult in system-on-chip systems that include many processing units and peripherals. For example, shared peripherals such as memory are used by special processors at special time intervals, but may be required at low latency by other processors during that interval. Known schemes, such as the AMBA 3 AXI power management channel and IEEE 802.11 wireless protocol, rely on one power manager to solve such system power problems. These centralized approaches do not scale well to larger systems. The integration of power management signaling, which is difficult to route to the main communication bus, presents additional overhead and challenges.

Data processing apparatus according to an aspect of the present invention,

One or more master units,

One or more slave units,

An interconnect connected to the at least one master unit and the at least one slave unit to route transactions, including data transfer transactions, along a wiring path between the at least one master unit and the at least one slave unit; ,

A transaction that is received by at least one slave unit of the one or more slave units is 1 that specifies usage prediction that indicates when a next transaction is passed to the at least one slave unit of the one or more slave units. Contains more than one usage signal,

At least one slave unit of the one or more slave units, in response to the one or more usage signals, selects the at least one slave unit of the one or more slave units before the next transaction is expected to be received. A local slave power controller which transitions to a first slave power state in the second slave power state and switches the at least one slave unit of the one or more slave units to a second slave power state at a suitable time for servicing the next transaction. Wherein the first slave power state has lower power consumption than the second slave power state, and wherein the first slave power state has a response latency longer than the second slave power state. Have

The technique attempts to manage power with reduced power delay tread-off by making it possible to almost accurately indicate the period of time during which devices are deactivated to be signaled at the micro-architectureal level. This eliminates the need for complex and inaccurate heuristic and / or predictive models. This technique delegates power management to individual slaves and masters. It can be easily scaled because it does not require a complex central power controller involved.

In a preferred embodiment, power management signals may be routed along with other communication signals to mitigate implementation and scalability, although more generally the usage signals may have their own routing / bus. have. The wiring path may be a combined bus with various signals routed together or several separate buses with their own routing. Including power management signaling as part of standard communications helps with scalability.

Usage signals may be generated and changed (mediated) at different points between the transaction being initialized and the target for that transaction. One important source of usage signals is the master unit issuing the transaction, because the master unit will be able to accurately identify when it was next to issue a transaction to the slave and organize appropriate usage signals with that transaction. . Another suitable point for inserting or changing usage signals would be at the level of the interconnect, which would have information relating to the state of the device as a whole, for example due to an arbitration decision made within the interconnect, It may be determined that the use of is unlikely to be repeated for a longer period of time than indicated by the master initiating the transaction.

The interconnect in a preferred embodiment provides the ability for each transaction from a plurality of master units to mediate between usage signals, thereby providing an arbitrated usage signal that is delivered to the target slave device. The interconnect is in a position that considers previous usage information and previous transactions for the slave as well as information related to the current transaction in determining which usage signal to send to the target slave device.

The level of sophistication provided to the slave unit may vary, and preferably the slave unit will have a plurality of low power states with respective power consumption and response latency, and typically, the smaller the power consumption, the more the response latency will be. Gets bigger Depending on the interval before the next transaction is expected to arrive, the slave unit can select an appropriate power-down mode to enter, for example, it takes a long time to enter and exits when the interval for the next transaction is short. Entering a long time deep power-down mode may not be worthwhile, but simply stopping the clock for that short period of time to save some power may be worthwhile.

In addition, the local slave power controller, which can be advantageously shared by a plurality of slave units, can select a low power state depending on the current state of the slave unit as well as the interval for the next transaction, for example, to connect with a particular transaction. There may be some other state variable associated with the associated slave unit, such as servicing some other activity that is not scheduled, which could allow the slave unit to power down to a special low power mode indicated at intervals for the next transaction. Indicates no.

The above is useful because it is described in terms of only one slave unit incorporating a suitable local slave power controller, but this technique is a system in which multiple slave units include each local slave power controller in response to usage signals. It will be appreciated that it is readily scalable and advantageous at. Likewise, this technique is well suited for systems containing a large number of properly configured master units for generating usage signals.

According to a preferred technique, at least one slave unit of the one or more slave units upon receiving a transaction from one master unit of the one or more master units is received by the one master unit of the one or more master units. One or more delays that issue an acknowledgment, wherein the receipt notification indicates when at least one slave unit of the one or more slave units completes the transaction for one master unit of the one or more master units; Includes prediction signals,

One master unit of the one or more master units may, in response to the one or more delayed prediction signals, select one master unit of the one or more master units in a first interval at an interval before the completion of the transaction is expected. A local master power controller for transitioning to a master power state and transitioning one of said one or more master units to a second master power state at an appropriate time for completion of said transaction; The master power state has a lower power consumption than the second master power state, and the first master power state has a longer response latency than the second master power state.

Intelligent and deterministic power down of the slave units in accordance with the usage signals can be extended back to the master units. The receipt notification signal returned from the slave unit (possibly reusing the use signal line / connection) upon receipt of the transaction may indicate how long it takes for the slave unit to complete the transaction, so that the master unit may not complete the transaction. There is a possibility to enter a low power mode while waiting, for example to enter latency when servicing a memory fetch.

The present technology and usage signals are not only used to control the power mode of the master and slave involved in a given transaction, but also reduce power consumption by triggering one or more arbitration circuits in the path between the slave and the master. You can also do something to get into. This may include a portion of the interconnect, where it is known that the portion of the interconnect will be idle for a determined period of time, such as indicated by usage signals. This can further save power.

The signals used may represent a delay in a variety of different ways, but a useful trade off between the number of signals used to be provided and the delay range that can be indicated is where a large number of encodings are used. It is. The lowest non-zero representable value may be selected to correspond to the lowest valid inactive interval of any of the slaves that may be communicating since it is not worth delivering a potential power down interval less than the lowest valid inactive interval available.

If the time until the next transaction is unclear, it can also be conveyed by the usage signals, and the local slave power controller can respond to it and switch to a low power consumption mode if desired. The slave unit will recognize that some latency will be associated with such an indeterminate time interval because it is impossible to preferentially power up at the appropriate time for the next transaction.

The manner in which the source of use signals can select which use signal to claim may vary. In one form of embodiment, the usage designation register may be associated with the master unit or may be writable under software control to a value that specifies which usage signal should be generated in connection with a transaction occurring in the master unit. This provides a great deal of flexibility in the way the signals used are specified, but in return some software intervention is required. Software programming of such usage values can be done at power up or at system initialization.

As an alternative, or in addition to the use of a register to designate the usage signals, the usage signal value may be encoded in a program instruction executed in a processor that functions as a master and initiates a transaction. Thus, knowing when the next transaction initiated by the program occurs, each transaction can have its own usage signal associated with what was determined at the time the software was automatically written by the compiler.

Another option or addition is to use an operating system program that monitors system parameters, such as thread activity, by specifying the appropriate program command to associate usage values with transactions being issued to the slave. In order to determine what value to use.

In addition to passing information about the interval for the next transaction, use signals to use local shutdown, global shutdown, local sleep, global sleep, local clock stop, global clock stop, local clock rate specification, global clock rate specification. Power commands, such as, low operating voltage mode, low leakage mode, wake up and / or interval extension, and the like. Usage signals are already routed through the interconnect, providing a convenient vehicle for delivering power commands around the system.

It will be appreciated that the present technology may be applied to a wide variety of different shaped devices. This technique is particularly well suited for use in integrated circuits or multichip modules, but is also scalable to printed circuit boards having a plurality of connected integrated circuits, for example, a particularly low power slave would be off-chip memory, It would be desirable to power this down using the usage signal technique described above.

The interconnect can take many forms, including a dedicated connection between one master unit and one slave unit, such as between the processor core and the cache memory, but the technique can be used, for example, by ARM Limited, Cambridge, UK. It is scalable and particularly applicable in the context of interconnects that provide more general point-to-point connections, such as the provided AXI interconnect system.

In another aspect, the invention includes data transfer transactions along a wiring path between at least one master unit, at least one slave unit, and at least one master unit and at least one slave unit, A method of processing data using an interconnect connected to said at least one master unit and said at least one slave unit to route transactions, said data processing method comprising:

A transaction received by at least one slave unit of the one or more slave units, wherein the transaction specifies one usage prediction that indicates when a next transaction is passed to at least one slave unit of the one or more slave units; Generating the above usage signal;

In response to the one or more usage signals using a local slave power controller of at least one of the one or more slave units, the next transaction may be received by the at least one slave unit of the one or more slave units. Transitioning to a first slave power state in an interval before it is expected, and transitioning at least one slave unit of the one or more slave units to a second slave power state at an appropriate time to service the next transaction. The first slave power state has a lower power consumption than the second slave power state, and the first slave power state has a response latency longer than the second slave power state.

In another aspect, the data processing apparatus according to the present invention,

One or more master unit means,

One or more slave unit means,

Connected to the one or more master unit means and the one or more slave unit means to route transactions, including data transfer transactions, along a wiring path between the one or more master unit means and the one or more slave unit means. With interconnect means,

The transaction received by at least one slave unit means of the one or more slave unit means is one that specifies usage prediction that indicates when a next transaction is delivered to at least one slave unit means of the one or more slave unit means. More than use signal,

At least one slave unit means of the one or more slave unit means, in response to the one or more usage signals, expects at least one slave unit means of the one or more slave unit means to receive the next transaction. Local to transition to a first slave power state in an interval before the transition, and to transition at least one slave unit means of the one or more slave unit means to a first slave power state at an appropriate time for servicing the next transaction. And slave power controller means, wherein the first slave power state has a lower power consumption than the second slave power state, and the first slave power state has a longer response latency than the second slave power state. Has

In another aspect, the present invention provides a transaction comprising data transfer transactions along a wiring path between at least one master unit, at least one slave unit, at least one master unit and at least one slave unit. An interconnect connected to said at least one master unit and said at least one slave unit to route traffic, wherein a transaction received by at least one slave unit of said at least one slave unit is at least one of said at least one slave unit; Providing a slave unit for use inside a device including one or more usage signals specifying usage prediction that indicates when to deliver the next transaction to the two slave units, wherein the slave unit comprises:

In response to the one or more usage signals, transitioning at least one slave unit of the one or more slave units to a first slave power state at an interval before the next transaction is expected to be received, And a local slave power controller for transitioning at least one slave unit of the slave units to a second slave power state at a suitable time for servicing the next transaction, wherein the first slave power state is selected from the second slave power state. It has a lower power consumption than the slave power state, and the first slave power state has a longer response latency than the second slave power state.

In another aspect, the present invention includes data transfer transactions along a wiring path between at least one master unit, at least one slave unit, and at least one master unit and at least one slave unit, Providing a master unit for use within an apparatus having an interconnect connected to the at least one master unit and the at least one slave unit to route transactions, wherein the master unit comprises:

One or more usage signals received by at least one slave unit of the one or more slave units and specifying usage prediction that indicates when to deliver a next transaction to at least one slave unit of the one or more slave units. And a transaction generator configured to generate a transaction.

In another aspect, the present invention includes data transfer transactions along a wiring path between at least one master unit, at least one slave unit, and at least one master unit and at least one slave unit, Providing an interconnect for use inside a device having an interconnect connected to said at least one master unit and said at least one slave unit to route transactions, said interconnect comprising:

One or more usage signals received by at least one slave unit of the one or more slave units and specifying usage prediction that indicates when to deliver a next transaction to at least one slave unit of the one or more slave units. And a signal connection configured to carry the transaction.

Embodiments of the present invention will be described by the following examples with reference to the accompanying drawings.

1 is a schematic diagram of an apparatus utilizing power management techniques.

FIG. 2 is a diagram schematically illustrating parallel signals carried over an interconnect in connection with a transaction between a master and a slave.

3 is a diagram schematically illustrating an example of encoding of use signals.

4 is a diagram schematically illustrating a slave unit incorporating a local slave power controller.

5 schematically illustrates a local slave power controller.

6 is a flowchart schematically illustrating the operation of a local slave power controller.

7 is a schematic view of a master unit incorporating a local master power controller.

8 is a flow chart schematically illustrating the operation of a local master power controller.

9 is a schematic diagram illustrating an interconnect incorporating a usage signal arbitration function.

10 is a flowchart schematically illustrating use signal arbitration.

1 shows an apparatus 2 in the form of a printed circuit board incorporating an integrated circuit 4 and a slave subsystem 6. The integrated circuit 4 may be a multi chip module, a system on chip integrated circuit or a standard integrated circuit. The integrated circuit includes a master unit 8, a processor core 10 also functioning as a master, and a cache memory 12 connected to the processor core 10. The cache memory 12 functions as a slave to the processor core 10 and also functions as a master for the interconnect 14. Between the processor core 10 and the cache memory 12 is a dedicated interconnect 16 that carries usage signals in accordance with the techniques presented below, as described below. Interconnect 14 is a variant of the AXI interconnect in this embodiment, which incorporates intermediary functionality and point-to-point connectivity for connectivity in accordance with known AXI techniques. The interconnect 14 extends beyond this known functionality by providing usage signals in accordance with the present technology which sends an indication when the slave unit receives its next transaction, such as one of the slaves 18, 20, 6. The slave subsystem 6 acts as a slave to the interconnect 14, but in essence one that requires more signal routing and is used or not depending on the transaction involved. There is more than a related functional element. The slave subsystem 6 may be a memory system with some local memory and additionally some higher rank memory, such as a hard disk drive that is required when local memory cannot service a particular transaction.

2 schematically illustrates the signal formation of a transaction carried by interconnect 14. These signals include a data signal 22, an address signal 24, and a use signal 26. The address signal 24 and the data signal 22 may follow known AXI systems and protocols, and may be routed and arbitrated (individually or together) in accordance with these known system protocols. Usage signal 26 may be added to this transaction and follow the same routing to be affected by the same routing arbitration and delay. The use signal 26 alternatively has its own routing and arbitration separately. The usage signal 26 conveys information, when known, that specifies when the next transaction, starting from its master and delivered to its target slave unit, occurs. This information powers itself down to the appropriate power-down mode and preferentially slaves itself back up at the appropriate time to service the next transaction without incurring undesirable latency. Can be used by.

3 schematically shows an example of encoding in which a 3-bit usage signal is used, for example. This encoding is algebraic for the first and second values but not all. The first value specifies an unexpected interval and indicates that the slave should be active. The last encoding may be interpreted by the slave in a variety of other ways, such as indicating an indeterminate interval, initiating a sleep mode with no preferential powerup. Among these extreme behaviors, encoding represents the interval for the next transaction, represented by a number of minimum supported power down intervals, such as four clock cycles, in the case of a typical AXI interconnect implementation. There is no need to provide granularity less than this smallest gap.

4 schematically shows a slave unit 28. It incorporates a number of functional blocks 30, 32 that process the received transaction in a substantially conventional manner as expected for the AXI transaction and in accordance with the functionality provided by the slave unit 28. In addition, by installing a local slave power controller 34 in response to the status information and usage signals delivered from the function block 30, how many times the power-down mode should be entered and after the received transaction has been serviced It is determined whether it is appropriate to enter one of the power down modes of the power down mode. When the slave unit 28 is powered down, it supplies the appropriate clock control signals and / or voltage control signals to the function blocks 30, 32 to initiate this power down and then to initiate the preferential power up. The local slave power controller 34 may also be shared by a plurality of slave units.

5 schematically illustrates the local slave power controller 34 in more detail. The usage signals are supplied to the power control logic 36 with state variables representing one or more aspects of the current state of the slave unit 28. These signals are used in combination to determine how long the slave unit 28 should be in power down mode. As such, the appropriate timer value is loaded into timer 28, which elapses time (e.g., until a wake-up signal is generated that is required for priority wake-up and communicated to power control logic 36). Count down) in units of minimum power down interval. The clock control signal and voltage control signal generated by the power control logic 36 to enter the appropriate power down mode can have a variety of different effects. The clock signal can be stopped or slowed to another value. The voltage can be lowered or turned off. The system can be placed in a low leakage mode or some other voltage manipulation made to reduce power. Various power down modes are known, but any can be used.

6 is a flow diagram schematically illustrating the control performed by the power control logic 36. In step 40, the system waits for usage signals to be received. When such signals are received, the process at step 42 selects the power down mode that should be entered depending on the length of the interval until the next transaction and the current slave state. If the interval is short, it is not worth entering deep power down mode, which takes a long time to enter and exit. Likewise, the current state of slave unit 28 may be limited in the power down mode that is entered (signaled by its state variable) regardless of the indicated interval. When the power down mode is selected, a wakeup time may be determined. Because different power-down modes take many different times to escape, they require wakeups to occur before or after. In step 44, the timer 38 is loaded at intervals for the required wake up point. Step 46 checks whether the current transaction occurring with the usage signals that were detected in step 40 has been completed. If this transaction is completed, processing proceeds to step 48, in which a signal for controlling the clock and voltage appropriate for the selected power down mode is issued to switch the slave unit to the power down mode. Step 50 continuously checks whether the timer has reached the required wakeup point. If the wakeup point has been reached, processing proceeds to step 52, the wakeup is initiated at step 52, and the power control logic 36 is capable of issuing appropriate clock control and voltage control signals to respond to the next transaction. Move the slave unit 28 to the mode. The purpose of the power control logic 36 is to move the slave unit 28 to its mode of operation to prepare the next transaction only at the appropriate time for the next transaction to be received.

Although not shown in FIG. 6, the slave unit 28 may use the usage signals to send a receipt notification to the initial master indicating how much longer it will take for the slave unit 28 to complete a received transaction only. have. This receive notification signal is used by the master to power down itself if it is suitable for the reception of the completed transaction by the master unit, which first powers itself up at the appropriate time to receive the completed transaction.

7 schematically shows a master unit 54. The master unit 54 contains one or more functional blocks 56, 58 that generate transactions, such as AXI transactions, in a known manner and, in response, are programmable. In addition, a local master power controller 60 is provided inside the master unit 54. The local master power controller 60 may include one or more software recordable interval values stored in an interval register 62; Decoded signals from a field inside a program instruction giving a decoded interval on signal line 64; And when determining which usage signal 68 to generate according to the transaction sent from the master unit 54 to the slave unit, responds to the state variable signal 66 specifying the current state of the master unit 54. The usage signals will specify when the master unit 54 expects to start a transaction for the slave next. This indicated usage signal value is not absolutely guaranteed, but tends to be relatively accurate since it is determined at the microarchitecture level within the master unit 54 itself, for example, due to the occurrence of an unexpected interrupt.

The local master power controller 60 completes the transaction for a period of time justifying entry and exit from the power down mode, in response to a receive notification signal passed back from the slave via the usage signal line 68. Power down master unit 54 when the slave indicates that it does not, for example does not return the requested data. Thus, the local master power controller generates a clock control signal and a voltage control signal that are passed to function blocks 56 and 58 to enter the power down mode in master 54.

8 schematically illustrates the control performed by the local master power controller 60. The process at step 70 waits for a transaction that needs to be issued. If a transaction is issued, step 72 includes: an interval specified in usage signals that perform the transaction from the shortest interval specified by the interval register value inside register 62; Decoding interval from any program command on decoded interval signal line 64; And a dependency on any constraint specified by the state variable on state variable signal line 66. Once this determination is complete, step 74 issues usage signals on signal line 68 with the transaction. Step 76 waits for a receive notification signal to pass back from the slave indicating how long it takes for the slave to complete the transaction. If such a reception notification signal is received, processing proceeds to step 78 where a plurality of power down modes supported by the special master unit 54, for example, clock stop, clock slowing, low voltage. The low power, sleep, power down, data retention, etc., determines the power down mode used. In step 80, the interval for the required wake up time associated with the power down mode used is determined and loaded into a timer inside the local master power controller 60. In step 82, the local master power controller 60 switches the master unit 54 into a power down mode. In step 84, the local master power controller 60 waits until the timer reaches the wakeup point, at which point time processing proceeds to step 86, and the master unit 54 completes the transaction or Switch back to that mode of operation at the appropriate time for the data to be returned.

9 schematically illustrates an interconnect block 14 used in accordance with the present technology. This interconnect block 14 supports routing of addresses and data as well as control information in accordance with known AXI techniques or other techniques. The elements included in interconnect 14 to support these known functions are well known in the art and will not be described further herein. Interconnect 14, as well as its conventional elements, includes an interconnect usage signal arbitration block 88 that functions to mediate usage signals passing through interconnect 14 between masters and slaves. The timer 90 provides a time index value that increases with a minimum power down interval step, for example four clock cycles. When a usage signal is received in connection with a transaction, it indicates that these masters require a special slave that is next relevant and the stored time index value associated with the connected master is indicated by the currently received usage signal of the target slave unit. Determine whether it represents the next use before or after it. These stored time index values are held in registers 92 and 94. If the next stored usage requirement is before the one currently displayed in the received usage signals, the interconnect usage signal arbitration block 88 modifies the usage signal and replaces the interval, indicating one of the next stored usage values in registers 92 and 94. Are specified at short intervals, such as one. If the next usage indicated by the current received usage signals is before any one of those stored, it will be delivered unchanged with the transaction.

In this example, it will be appreciated that mediation between multiple masters is done within interconnect 14. As an alternative, in particular, if the slave unit had a system installed to handle overlapping transactions from multiple masters and was more complex, such as a memory controller, which had already been designed, it would be possible to arbitrate within the slave unit itself.

Interconnect 14, when providing its data and address routing functions, incorporates a variety of different parts that can be selectively powered up and powered down in response to usage signals passing through interconnect 14. The interconnect block 14 may power down that path because no special path will be required for some period of time, and whether it is additional parts or parts of itself outside of the interconnect block, and the usage signals passing through it. In response, it is possible to determine from the use signals whether they are not affected by their own local power control.

10 is a flow diagram schematically illustrating the arbitration performed by the interconnect usage signal arbitration block 88. In step 96, the interconnect usage signal arbitration block 88 waits for a transaction. If such a transaction is received, then at step 98 the next usage time derived from the related usage signals in the received transaction and the next of the other masters for previously received transactions from these other masters, such as those stored in registers 92 and 94; Compare usage time indexes. In step 100 it is determined whether any other master has shown a shorter interval for the next use. If any other master has a shorter interval, processing proceeds to step 102, whereby step 102 is bypassed, where the received usage signals respond to any additional delay imposed by the interconnect block 14 itself. Then, the interconnect block 14 is changed to show the shortest interval for any one of the masters to sense. Interconnect usage signal arbitration block 88 responds to state variable signals that specify the state of interconnect block 14 so that data and address routing blocks operating in accordance with known AXI techniques are specific to any other device within the system. Assigning a wayway, etc., and this may indicate factors that will impose a different time interval regardless of all of the above until the next transaction can actually reach the associated slave unit. In step 104, the next use time index of the master from which the transaction is received is updated in the appropriate one of the registers 92 and 94. In step 106, the arbitrated usage signals are issued to the target slave unit.

In addition to specifying a time interval for the next transaction, the usage signals used to pass back receive notification signals representing the time interval until the completion of the current transaction are conveniently and scalable to normal data. And more standard power down instructions routed through system piggy-backing to the address routing infrastructure. Examples of power down signals that may be supplied to the local slave power controller, the local master power controller, and the power controller of the interconnect block itself include, for example, local shutdown, global shutdown, local sleep, global sleep, local clock stop, global clock stop, local. There are instructions such as clock rate specification, global clock rate specification, low operating voltage mode, low liquidity mode, wake up and interval extension (this is an instruction to extend the already specified time interval until the next transaction or completion of a transaction).

Claims (52)

As a data processing device, One or more master units, One or more slave units, An interconnect connected to the at least one master unit and the at least one slave unit to route transactions including data transfer transactions along a wiring path between the at least one master unit and the at least one slave unit, One or more uses that specify a usage prediction indicating that a transaction received by at least one slave unit of the one or more slave units indicates that a next transaction is passed to the at least one slave unit of the one or more slave units. Signal, The at least one slave unit of the one or more slave units, in response to the one or more usage signals, selects the at least one slave unit of the one or more slave units before the next transaction is expected to be received. Local slave power, transitioning to a first slave power state in an interval, and transitioning the at least one slave unit of the one or more slave units to a second slave power state at an appropriate time to service the next transaction And a controller, wherein the first slave power state has a lower power consumption than the second slave power state, and wherein the first slave power state has a longer response latency than the second slave power state. Characterized in that the data processing device. The method of claim 1, And a master unit issuing a transaction provides the one or more usage signals within the transaction depending on the current state of the master unit. The method according to claim 1 or 2, And wherein said interconnect provides said one or more usage signals within said transaction depending on the current state of said data processing device. The method of claim 3, wherein The interconnect mediates between usage signals received by each transaction from a plurality of master units, so that the next transaction is delivered from any of the plurality of master units to the at least one slave unit of the one or more slave units. Indicates a case and provides arbitrated usage signals that are delivered to the at least one slave unit of the one or more slave units. The method according to any one of claims 1 to 4, The at least one slave unit of the one or more slave units has a plurality of low power states with respective power consumption and response latency that may be used as the first slave power state, and the local slave power controller is configured to perform the following operation. And which of the plurality of low power states to use as the first slave power state depending on the interval before a transaction is expected. The method of claim 5, wherein The local slave power controller also selects which of the plurality of low power states to use as the first slave power state depending on the current state of the at least one slave unit of the one or more slave units. Data processing device. The method according to any one of claims 1 to 6, And a plurality of slave units each including a local slave power controller responsive to said at least one usage signal. The method according to any one of claims 1 to 7, At least one slave unit of the one or more slave units upon receipt of a transaction from one master unit of the one or more master units issues a receipt notification to the one master unit of the one or more master units and And the reception notification includes one or more delay prediction signals indicating when the at least one slave unit of the one or more slave units completes the transaction for the one master unit of the one or more master units. and, The one master unit of the one or more master units may be configured to remove the one master unit of the one or more master units in an interval before the completion of the transaction is expected in response to the one or more delayed prediction signals. A local master power controller for transitioning to a master power state of one and transitioning said one master unit of said one or more master units to a second master power state at an appropriate time for completion of said transaction; A first master power state has lower power consumption than the second master power state, and the first master power state has a longer response latency than the second master power state Device. The method of claim 8, The at least one delay prediction signal also triggers at least one arbitration circuit element in a path between the at least one slave unit of the at least one slave unit and the at least one master unit of the at least one master unit. And enter a reduced power consumption state. The method according to any one of claims 1 to 9, The interconnect is A plurality of portions having individually controllable power states, And a local interconnect power controller for controlling each power state of the plurality of portions of the interconnect in response to the one or more usage signals. The method according to any one of claims 1 to 10, Wherein said at least one usage signal comprises a plurality of usage signals and uses algebraic encoding for at least some values of said usage prediction. The method according to any one of claims 1 to 11, The usage prediction corresponding to the lowest non-zero value represented by the one or more usage signals corresponds to the lowest valid inactive interval for one slave unit of the one or more slave units. The method according to any one of claims 1 to 12, The one or more usage signals have a value indicating an undetermined time before the next transaction, and the local slave power controller is responsive to switching the at least one slave unit of the one or more slave units to a low power consumption mode. Characterized in that the data processing device. The method according to any one of claims 1 to 13, Store a software recordable value specifying usage signals generated by one master unit of the one or more master units, and storing at least one usage assignment register associated with each one master unit of the one or more master units. Data processing apparatus characterized in that it comprises. The method according to any one of claims 1 to 14, And a processor for initiating one of the transactions in response to a program command, wherein the field with the program command specifies a value for the one or more usage signals associated with the transaction. Device. The method of claim 15, And said program command is part of an operating system program, said field being determined by said operating system program and changing depending on the current state of at least a portion of said device. The method according to any one of claims 1 to 16, And the one or more usage signals can also carry one or more power commands. The method of claim 17, The one or more power commands, Local shutdown; Global shutdown; Local sleep; Global slip; Local clock stop; Global clock stop; Local clock speed specification; Global clock rate specification; Low operating voltage mode; Low liquidity mode; Wake up; And Interval expansion And at least one of the data processing apparatus. The method according to any one of claims 1 to 18, The device, Integrated circuits; Multi-chip module; And And a printed circuit board having a plurality of connected integrated circuits. The method according to any one of claims 1 to 19, And wherein said interconnect is a point-to-point interconnect. The method according to any one of claims 1 to 19, And wherein said interconnect is a dedicated connection between one master unit and one slave unit. The method of claim 21, And said one master unit is a processor core and said one slave unit is a cache memory. The method according to any one of claims 1 to 22, And said usage signals are routed in a wiring path shared with one or more other signals forming part of said transaction. The method according to any one of claims 1 to 23, And said local power controller is shared by a plurality of slave units. The at least one master unit to route transactions, including data transfer transactions, along a wiring path between at least one master unit, at least one slave unit, and at least one master unit and the at least one slave unit And a method for processing data using an interconnect connected to the at least one slave unit, A transaction received by at least one slave unit of the one or more slave units, wherein the transaction specifies a usage prediction that indicates when a next transaction is passed to the at least one slave unit of the one or more slave units. Generating at least one usage signal; In response to the one or more usage signals using a local slave power controller of the at least one slave unit of the one or more slave units, the at least one slave unit of the one or more slave units, Transition to a first slave power state in an interval before it is expected to be received, and move the at least one slave unit of the one or more slave units to a second slave power state at an appropriate time to service the next transaction. Transitioning, wherein the first slave power state has lower power consumption than the second slave power state and the first slave power state has a response latency longer than the second slave power state. Data processing room comprising method. The method of claim 25, The one or more usage signals within the transaction are provided by the master unit depending on the current state of the master unit. The method of claim 25 or 26, And said one or more usage signals within said transaction are provided by said interconnect depending on the current state of said device. The method of claim 27, Mediate between the usage signals received by each transaction from a plurality of master units with the interconnect, so that a next transaction is added to the at least one slave unit of the one or more slave units from any of the plurality of master units; Indicating a case of delivery and providing mediated usage signals delivered to said at least one slave unit of said at least one slave unit. The method according to any one of claims 25 to 28, The at least one slave unit of the one or more slave units has a plurality of low power states with a response latency and respective power consumption that can be used as the first slave power state, and the local slave power controller is configured to perform the following operation. And which of the plurality of low power states to use as the first slave power state, depending on the interval before the transaction is expected. The method of claim 29, The local slave power controller is further configured to select which of the plurality of low power states to use as the first slave power state depending on the current state of the at least one slave unit of the one or more slave units. How to process data. The method according to any one of claims 25 to 30, And a plurality of slave units each comprising a local slave power controller responsive to said at least one usage signal. The method according to any one of claims 25 to 31, At least one slave unit of the one or more slave units upon receipt of a transaction from one master unit of the one or more master units issues a receipt notification to the one master unit of the one or more master units and The reception notification includes one or more delay prediction signals indicating when at least one slave unit of the one or more slave units completes the transaction for one master unit of the one or more master units, In response to the one or more delay prediction signals using a local master power controller of the one of the one or more master units, expecting the one of the one or more master units to complete the transaction. Transitioning to a first master power state at an interval before the following, switching the one master unit of the one or more master units to a second master power state at an appropriate time to complete the transaction, and Wherein the master power state has a lower power consumption than the second master power state, and wherein the first master power state has a response latency longer than the second master power state. The method of claim 32, The at least one delay prediction signal is further reduced by triggering at least one arbitration circuit element in a path between the at least one slave unit of the at least one slave unit and the at least one master unit of the at least one master unit. A method of processing data, characterized in that to enter the power consumption state. The method according to any one of claims 25 to 33, The interconnect includes a plurality of portions having individually controllable power states, and the method includes powering each of the plurality of portions of the interconnect in response to the one or more usage signals using a local interconnect power controller of the interconnect. Further comprising controlling a state. The method according to any one of claims 25 to 34, wherein Wherein said at least one usage signal comprises a plurality of usage signals and uses algebraic encoding for at least some values of said usage prediction. The method according to any one of claims 25 to 35, The usage prediction corresponding to the lowest non-zero value indicated by the one or more usage signals corresponds to the lowest valid inactive interval for one slave unit of the one or more slave units. The method according to any one of claims 25 to 36, The at least one usage signal has a value representing an indeterminate time before the next transaction, and the method is responsive to the value representing an indeterminate time using the local slave power controller; And switching the two slave units to the low power consumption mode. The method according to any one of claims 25 to 38, Storing a value specifying usage signals generated by the one master unit of the one or more master units in at least one usage assignment register associated with each one of the one or more master units under software control. Data processing method comprising the. The method according to any one of claims 25 to 38, Responsive to a program instruction executed by a processor that initiates one of the transactions, wherein the field with the program instruction specifies a value for the one or more usage signals associated with the transaction. Data processing method. The method of claim 39, The program command is part of an operating system program, and the field is determined by the operating system program and is changed depending on the current state of at least a portion of the apparatus. The method according to any one of claims 25 to 40, And said at least one usage signal is also capable of conveying at least one power command. 42. The method of claim 41 wherein The one or more power commands, Local shutdown; Global shutdown; Local sleep; Global slip; Local clock stop; Global clock stop; Local clock speed specification; Global clock rate specification; Low operating voltage mode; Low liquidity mode; Wake up; And Interval expansion A data processing method comprising at least one of the above. The method according to any one of claims 25 to 42, The method, Integrated circuits; Multi-chip module; And A data processing method characterized in that it is performed inside one of a printed circuit board having a plurality of connected integrated circuits. The method according to any one of claims 25 to 43, And wherein said interconnect is a point-to-point interconnect. The method according to any one of claims 25 to 43, And wherein said interconnect is a dedicated connection between one master unit and one slave unit. The method of claim 45, And said one master unit is a processor core and said one slave unit is a cache memory. The method according to any one of claims 25 to 46, And said usage signals are routed in a wiring path shared with one or more other signals forming part of said transaction. The method according to any one of claims 25 to 47, The local power controller is shared by a plurality of slave units. As a data processing device, One or more master unit means, One or more slave unit means, Connected to the one or more master unit means and the one or more slave unit means to route transactions, including data transfer transactions, along a wiring path between the one or more master unit means and the one or more slave unit means. With interconnect means, A transaction received by at least one slave unit means of the one or more slave unit means specifies a usage prediction that indicates when a next transaction is delivered to the at least one slave unit means of the one or more slave unit means. Contains more than one usage signal, At least one slave unit means of said at least one slave unit means is configured to receive said at least one slave unit means of said at least one slave unit means in response to said at least one usage signal. Transition to a first slave power state in an interval before it is expected, and transitioning said at least one slave unit means of said one or more slave unit means to a second slave power state at an appropriate time for servicing said next transaction. Local slave power controller means, wherein the first slave power state has a lower power consumption than the second slave power state, and wherein the first slave power state is longer than the second slave power state. Day characterized by having a response latency Processor. The at least one master unit to route transactions, including data transfer transactions, along a wiring path between at least one master unit, at least one slave unit, and at least one master unit and the at least one slave unit And an interconnect connected to said at least one slave unit, wherein a transaction received by at least one slave unit of said at least one slave unit delivers a next transaction to at least one slave unit of said at least one slave unit. A slave unit to be used inside a device, comprising one or more usage signals specifying usage prediction that indicates when In response to the one or more usage signals, transitioning the at least one slave unit of the one or more slave units to a first slave power state at an interval before the next transaction is expected to be received, the one A local slave power controller for transitioning said at least one slave unit of said slave unit to a second slave power state at a suitable time for servicing said next transaction, wherein said first slave power state is said first; And have a lower power consumption than the slave power state of two, and wherein the first slave power state has a response latency longer than the second slave power state. The at least one master unit to route transactions, including data transfer transactions, along a wiring path between at least one master unit, at least one slave unit, and at least one master unit and the at least one slave unit And a master unit for use inside a device having an interconnect connected to said at least one slave unit, One or more usage signals received by at least one slave unit of the one or more slave units and specifying usage prediction that indicates when to deliver a next transaction to at least one slave unit of the one or more slave units. And a transaction generator configured to generate a transaction. The at least one master unit to route transactions, including data transfer transactions, along a wiring path between at least one master unit, at least one slave unit, and at least one master unit and the at least one slave unit An interconnect used within a device having an interconnect connected to said at least one slave unit, One or more usage signals received by at least one slave unit of the one or more slave units and specifying usage prediction that indicates when to deliver a next transaction to at least one slave unit of the one or more slave units. And a signal connection configured to carry a transaction.

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