KR20090034206A - Method of constructing process block index combination, and method of signalling for the same - Google Patents

Abstract

A method of constructing a process block index combination and a signaling method therefor are provided to maximally maintain flexibility about a combination of an HARQ process block index under allowance of a system when simultaneously transmitting a plurality of HARQ process blocks. The first process block index to be transmitted through the first layer is determined among layers. The number of the second process block indexes to be transmitted through the second layer among the layers is determined. The second process block indexes are mapped on the first process block indexes. The second process block indexes are circularly mapped in determined first process indexes within the entire process block index to be transmitted through the layers as many as the number of the second process block indexes.

Description

Method of Constructing Process Block Index Combination, And Method Of Signaling For The Same}

The present invention relates to a method for indicating a process block index in a communication system using HARQ, and more particularly, to a method of efficiently configuring and signaling an index combination of process blocks transmitted through a plurality of layers during a predetermined transmission unit.

Error control algorithms used in current communication systems can be classified into two types, namely, automatic repeat request (ARQ) and forward error correction (FEC). Types of ARQ include Stop and Wait ARQ, Go-Back-N ARQ, and Selective-Repeat ARQ. Stop and Wait ARQ is a technique that transmits the next frame after confirming the correct reception of each transmitted frame (ACK signal confirmation), and Go-Back-N ARQ transmits N consecutive data frames and successfully transmits them. If this is not done, all data frames transmitted after the frame in which the error occurs are retransmitted. The selective iterative ARQ technique is a method of selectively retransmitting only an error frame.

On the other hand, HARQ (Hybrid Automatic Repeat reQuest) is a technique for controlling errors by combining retransmission and error correction, a method of maximizing the error correction code capability of the data received during retransmission. According to the characteristics of bits transmitted during retransmission, it can be divided into chase combing (CC) and incremental redundancy (IR) HARQ. Chase combining HARQ is a method to obtain gain by increasing the SNR ratio at the receiver by using the data used in the first transmission when retransmission, and IR HARQ transmits and combines redundancy bits during retransmission. In this method, a coding gain is obtained at a receiving end to improve performance.

As such, the HARQ transmission method may be classified into synchronous and asynchronous HARQ. The synchronous HARQ transmits data through a predetermined resource at a time point known to both the transmitter and the receiver at the transmitter. Therefore, it is not necessary to include a HARQ process number indicating signaling required for transmission, for example, identity of data.

However, asynchronous HARQ is a method of transmitting data by allocating resources at random times. Therefore, signaling overhead, because signaling must be included for data transmission, for example, HARQ process number must be included.

1 is a diagram illustrating an example of a structure of a control signal in a conventional synchronous and asynchronous HARQ system.

Specifically, FIG. 1 shows an example of a control signal structure used in a 3GPP communication system (see 3GPP TR 25.814), whereby a control signal in a synchronous HARQ system does not need to indicate an index of a currently transmitted process block or the like. HARQ transmission is possible using only two bits of control information. However, in the case of the asynchronous HARQ system, it can be seen that a larger number of bit information is required, including information indicating an index of a process block that is currently transmitted.

The structure of the control information shown in FIG. 1 may be represented by the following table.

In Table 1, a combination of process block indices that can be represented by a 3-bit control signal in an asynchronous HARQ system may be up to eight. The above table is a control signal for the case where the number of blocks of a process that can be transmitted per transmission unit is one. However, in the asynchronous HARQ system, the number of process blocks that can be transmitted per transmission unit may increase in various ways depending on the number of process blocks that can be transmitted simultaneously. In this case, the control signal for indicating the HARQ process number may be The number of bits increases, which increases system overhead.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is that even when the number of process blocks that can be transmitted per transmission unit increases, the combinations of the corresponding process block indexes can be efficiently constructed, thereby allowing each combination to be performed through fewer control information. To provide a way to indicate that.

In a first aspect of the present invention for solving the above problems, there is provided a method for configuring an index combination of process blocks to be transmitted through a plurality of layers per predetermined transmission unit in a communication system using a plurality of layers. do. According to an aspect of the present invention, there is provided a method of configuring a combination of process block indexes, the method comprising: a first step of determining a first process block index to be transmitted through a first layer among the plurality of layers; A second step of determining a number of second process block indices to be transmitted through a second layer among the plurality of layers, and a difference (eg, N _proc / 2) by a predetermined index from the first process block index A total process block index to transmit the second process block index as many as the determined number of second process block indexes through the plurality of layers per predetermined transmission unit except for the determined first process block index from an index having a difference). Range (N _proc And a third step of circularly mapping each of the determined first process block indexes within a range).

At this time, in the second step, the number of the second process block index may be determined such that the total number of index combinations of the whole process blocks is a power of two, and if the number of all index combinations of the whole process blocks is two If not, the method may further include adding a number of index combinations corresponding to a difference between the full index combination and a minimum power of two that may represent the full index combination. Here, the index combination addition step may be performed by using the index combination generated by determining the number of the second process block indexes in the second step so that the total number of index combinations of the entire process blocks is a power of two. It can be set by adding a corresponding number of indices.

Further, in another embodiment of the first aspect of the present invention with respect to a method for configuring an index combination of process blocks, the entire process block index is the first group index and the second process block index for the first process block index. Assume that it is divided into a second group index for. For example, when the entire process block index is represented as {0, 1, ..., (N _proc )}, the index for the first process block is {0, 1, ..., (N _proc / 2 -1)}, the index for the second process block refers to the case is set as {(N _proc / 2), (N _proc / 2 + 1), ..., (N _proc )}. In this embodiment in which the entire process block indexes are divided as described above, in the third step, the second process block index is not within the entire process block index range but within the second group index range (in the above example, (N _proc / 2) can be configured to be cyclically mapped in the index range of the size).

Meanwhile, the difference between the first process block index and the predetermined index of the second process block index by the number determined in the second step is 1/2 of the number of the entire process block indexes (N _proc / 2). Can be set to

In the first aspect of the present invention, the communication system may be an asynchronous HARQ type communication system, wherein the predetermined transmission unit may be a round trip delay time. In addition, in the first aspect of the present invention described above, the communication system may be a MIMO communication system, wherein the plurality of layers may be a plurality of transmit antennas used by a transmitting side.

Meanwhile, a second aspect of the present invention provides a method of signaling an index combination of process blocks transmitted through the plurality of layers per predetermined transmission unit in a communication system using a plurality of layers.

In one embodiment of the present invention, a table index per process block index combination in which the first process block index and the second process block index are mapped according to the method for configuring a process block index combination according to the first aspect of the present invention. And setting a table to transmit a table index corresponding to an index combination of process blocks transmitted through the plurality of layers per predetermined transmission unit among all table indexes of the table.

In another embodiment of the present invention, in the communication system using a plurality of layers, the first process block index and the second process according to the process block index combination configuration method according to the first aspect of the present invention. When a block index is mapped, a method of signaling an index combination of the process block transmitted through the plurality of layers per predetermined transmission unit is provided. To this end, in the present embodiment, transmitting the one or more first process block index information transmitted through the first layer, and the information of the second process block index, to be mapped to each of the first process block index. Transmitting.

According to the method for configuring a process block index combination as described above and a signaling method therefor, while simultaneously transmitting a plurality of HARQ process blocks, the flexibility of the combination of HARQ process block indexes can be maintained to the maximum in a system-allowed range. At the same time, the overhead of the control signal can be reduced, so that resources can be used efficiently.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The detailed description, which will be given below with reference to the accompanying drawings, is intended to explain exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced.

The following detailed description includes specific details in order to provide a thorough understanding of the present invention. However, one of ordinary skill in the art appreciates that the present invention may be practiced without these specific details. In some instances, well-known structures and devices are omitted or shown in block diagram form, centering on the core functions of each structure and device, in order to avoid obscuring the concepts of the present invention. In addition, the same components will be described with the same reference numerals throughout the present specification.

According to the present invention, when the number of HARQ process blocks transmitted per predetermined transmission unit increases as described above, an object of the present invention is to provide a method of reducing overhead of a control signal for distinguishing the HARQ process blocks. To this end, the following description will first look at various cases in which process blocks transmitted per transmission unit increase, and in this case, a method of reasonably reducing the number of corresponding process block combinations will be provided.

2 is a view for explaining a stop-and-wait HARQ scheme.

As described above, HARQ is a technique for controlling errors by combining retransmission and error correction, and maximizes error correction code capability of data received during retransmission. That is, if an error of data received at the receiving end Rx is not detected, the receiving end Rx transmits an ACK signal, and if an error is detected, the receiving end Rx transmits a NACK signal. The data transmitting end Tx receiving the ACK signal then transmits data. The data transmitting end Rx receiving the NACK signal retransmits the corresponding data having an error. In this case, the retransmitted data may change the format of the retransmitted data according to the HARQ type.

In particular, the stop-and-weight protocol as shown in FIG. 2 has a rounding delay time until the data transmitting end Tx receives ACK (ACKnowledgement) / NACK (No ACK) from the data receiving end Rx. A method of delaying and transmitting data during a time (“RTT”) is the simplest and most efficient transmission method, but the link transmission efficiency may be degraded due to the delay of the RTT.

In order to compensate for this, the following N-channel stop and weight HARQ scheme may be used.

3 illustrates an N-channel stop and weight HARQ structure.

In general, in the stop and weight HARQ method, the data receiving end may check whether the data is successfully received through an error detection code such as a cyclic redundancy check (CRC). Therefore, in the present description, for convenience of description, the above-described data unit in which an error can be detected will be referred to as a 'HARQ process block' or simply 'process block' when there is no confusion. In addition, an identification factor used for distinguishing HARQ process blocks that can be transmitted within a predetermined interval (for example, 1 RTT (round trip time)) in the system will be referred to as a 'HARQ process index'.

That is, in the typical stop and weight HARQ scheme shown in FIG. 2, the data transmission is delayed by the time (RTT) until one process block transmission is received and then an ACK / NACK is received. In the same N-channel stop-and-weight HARQ scheme, N process blocks that can be transmitted in the RTT are transmitted and then independent ACK / NACK signals are received. This can increase the link efficiency, but the number of process block indexes that can be transmitted in the RTT can be increased by N times.

Meanwhile, when the transmission bandwidth of the system is wide or when data is transmitted using multiple antennas (MIMO), a plurality of HARQ process blocks may be simultaneously transmitted.

4 is a diagram illustrating a transmission method by multiple HARQ processing.

That is, a plurality (m) of HARQ processes may transmit m HARQ process blocks at the same time. The receiving end receiving data may transmit m ACK / NACK signals for each of the m HARQ process blocks to the data transmitting end. As described above, a method of transmitting m process blocks simultaneously may be combined with an N-channel stop and weight method as shown in FIG. 3 to further improve link performance of the system.

In the case of transmitting a plurality of process blocks at the same time as described above, in the following description, each HARQ process in which each process block is transmitted will be referred to as a "layer". Such a layer may correspond to each antenna capable of simultaneously transmitting data in each band or MIMO communication system when the system bandwidth is wide in the communication system and thus transmitting a plurality of process blocks at the same time. Hereinafter, the MIMO communication system will be briefly described as an example of applying a plurality of layers as described above.

MIMO (Multi Input Multi Output) is a technique of transmitting data through multiple paths by increasing the number of antennas of a base station and a mobile terminal to two or more, and detecting a signal received in each path at a receiving end. The MIMO may be classified into various methods such as spatial diversity, transmit diversity, beamforming, spatial multiplexing of one user, and spatial multiplexing of multiple users.

Spatial diversity is a technique of transmitting the same data through a plurality of antennas, and when the CQI feedback from the terminal is low in reliability due to fading, stable operation can be performed. In addition, it is useful as a technique for coping with fading by using diversity without waiting for better channel condition when it is necessary to service delay-sensitive kinds of traffic. In addition, transmit diversity is a representative technique of the MIMO communication method and may be used when the transmitter has multiple antennas and does not know the channel state.

On the other hand, beamforming is a technique used to increase the signal to interference plus noise ratio (SINR) of a signal by applying weights according to channel conditions in multiple antennas. In the case of transmit beamforming, it is difficult to know the channel state, so separate feedback is required, and how to efficiently support it is an important element of the system design.

Meanwhile, the spatial multiplexing method for a single user and multiple users will be briefly described as follows.

5 is a diagram illustrating the concept of a spatial multiplexing (SM) and a spatial divisional multiple access (SM) method used in a MIMO communication system.

Spatial multiplexing for a single user is called SM or SU-MIMO (single user MIMO), and by using a plurality of antennas of one user in a manner as shown on the left side of FIG. It increases in proportion to the number. Meanwhile, spatial multiplexing for multiple users is called SDMA or MU-MIMO (Multi-User MIMO), and data transmission and reception are performed through a plurality of user antennas as shown in the right side of FIG. 5.

On the other hand, in the case of using the above-described MIMO scheme, a single codeword (SCW) mode in which a single codeword, which is a unit capable of error detection, is carried on multiple antennas and transmitted simultaneously, and multiple codewords are simultaneously transmitted on multiple antennas. There is an MCS (Multi CodeWord) mode.

6 is a diagram illustrating a structure of a transmitting end of a multiple codeword (MCW) MIMO system.

Specifically, M data packets are generated through M encoding (for example, turbo encoding of FIG. 6) and modulation (for example, QAM modulation of FIG. 6) to generate M codeword HARQ process blocks. . This is again mapped at the MIMO stage, and with efficient antenna signaling, the layers are combined to match the number M _t of physical antennas and transmitted to the receiver. Thereafter, the receiving end feeds back channel quality information of each antenna, so that a coding rate and a modulation scheme may be adjusted accordingly.

Meanwhile, the mapping relationship between the codeword and the physical antenna may have the following form.

7 is a diagram illustrating an example of a mapping relationship between a codeword and a physical antenna.

FIG. 7 illustrates a codeword-to-layer mapping for spatial multiplexing in DL for spatial multiplexing in downlink in 3GPP TS 36.211.

That is, in the case of rank 1, one codeword is mapped to one layer and transmitted through four antennas by a precoder. In the case of rank 2, two codewords are mapped to two layers and thus free. An example of a form mapped to four antennas by a coder is illustrated. In addition, in the case of rank 3, one codeword of two codewords is mapped to two layers by a serial-to-parallel converter (S / P), so that a total of two codewords are mapped to three layers and then to a precoder. In the case of rank 4, each of the two codewords is mapped to two layers by a serial-to-parallel converter, so that a total of four layers are mapped to four antennas by a precoder. An example is shown.

According to the definition of the process block in the MIMO communication system as described above, the plurality of layers in one embodiment of the present invention may be a plurality of transmit antennas, a plurality of codewords, or a plurality of streams. Specifically, when the number of codewords is M, this means that the number of HARQ process blocks transmitted simultaneously is M. Therefore, the layer here may correspond to a codeword. This is because the data unit that an error can detect is a codeword. However, in a system in which one codeword is mapped to one stream, a layer according to an embodiment of the present invention may mean a stream, and in a similar sense, when one codeword is transmitted to one antenna, the number of antennas Can be seen as the number of layers.

As such, the means capable of simultaneously transmitting a plurality of process blocks may be collectively referred to as a 'layer' in one embodiment of the present invention. That is, such a layer is a path through which data can be simultaneously transmitted from a transmitting end to a receiving end, and the path may be an antenna / stream / codeword described above in the MIMO communication system, as well as a plurality of resource blocks in addition to the MIMO communication system. The RB may include an RB in a system that simultaneously transmits a process block.

Hereinafter, for convenience of description, the case in which the number of process blocks transmitted within a predetermined transmission unit (for example, 1 RTT) increases according to an embodiment of the present invention simultaneously using m layers as described above. send m process blocks, It will be described on the assumption that n process blocks are independently transmitted within one RTT, such as the N channel stop and weight method. In other words, it is assumed that the number of process blocks transmitted per predetermined transmission unit is m * n. However, in each case, the number of corresponding process blocks need not be limited to a specific number, and it will be apparent to those skilled in the art that various numbers of process blocks may be transmitted according to a system.

As described above, when using m layers and using the N-channel stop and weight HARQ scheme, the number of combinations of process block indices that may occur may be expressed as follows.

Therefore, the number of bits (x) of the control signal required to represent such HARQ process block index combination can be expressed as follows.

A detailed case of indicating a HARQ process block index combination using this method will be described below.

FIG. 8 is a diagram illustrating an example of applying 16-channel HARQ stop and weight HARQ in a two-layer MIMO communication system.

Specifically, FIG. 8 illustrates an example in which a maximum of 8 HARQ process blocks can operate during one RTT in a MIMO communication system that simultaneously generates and transmits two codewords. That is, in the system illustrated in FIG. 8, up to 16 HARQ process blocks may be transmitted through two layers within 1 RTT.

In this case, when 16 HARQ process blocks are transmitted by Equation 1, a method of informing the identification factor of each process may be 256 (= 16 * 15 + 16) combinations. That is, when HARQ process blocks are transmitted to both layers, there are 240 (= 16 * 15) combinations, and when one HARQ process block is transmitted in a unit interval, an identification factor of the HARQ process block is notified. There are 16. Accordingly, as can be seen from Equation 2, the control signal bit number for the HARQ process number in the example system shown in FIG. 8 is 8 bits. Furthermore, up to eight HARQ process blocks can be operated during one RTT, and if HARQ process blocks are transmitted through up to three layers at the same time, 12720 (= 24 * 23 * 22 + 24 * 23 + 24) Since the combination must be represented, 14 bits of control signaling are required. However, when eight HARQ process blocks can operate during one RTT, and HARQ process blocks are transmitted through only one layer, only eight combinations exist, so the number of control signaling bits required to represent HARQ process blocks is 3 bits.

As described above, in a system in which at most m HARQ process blocks are transmitted at the same time through all m layers and at most n process blocks are transmitted within one RTT, the number of cases shown in Equation 1 is equal to the corresponding m and n values. As the increase, the overhead may increase in the number of bits of the control signal to indicate this. Therefore, the following description describes a method for efficiently reducing the overhead of the control signal while minimizing the flexibility in indicating each HARQ process block index combination.

Description of each embodiment of the present invention to be described below, in the transmission through the overall HARQ scheme of transmitting the HARQ process block, and retransmitting the HARQ process block, effective identification factors required for each step It is about how to configure. Specifically, in the first aspect of the present invention to be described below, it is assumed that a plurality of (m) HARQ process blocks are simultaneously transmitted in an N-channel stop and weight scheme. We propose a method of constructing a process block combination that reduces overhead by giving a specific constraint to each process block combination configuration. In addition, a second aspect of the present invention to be described later is to provide a method in which a transmitter performs signaling efficiently by using a process block combination configured as described above.

First, in a communication system using a plurality of layers, a method of configuring an index combination of process blocks to be transmitted through a plurality of layers per predetermined transmission unit according to the first aspect of the present invention will be described.

I. First Aspect-How to Configure Process Block Index Combinations

In the embodiments of the present invention to be described below, it is assumed that the number of process blocks that can be transmitted at the same time, that is, when two layers are used (m = 2). In addition, it is assumed that the number m of layers to which the process block is transmitted at the same time is informed by another arbitrary signal. Such an embodiment has a form suitable for application to a 3GPP LTE system in that the number of codewords used in the MIMO system of 3GPP LTE under discussion is 2 (Approved Report of 3GPP TSG RAN WG1 # 46bis, R1). -063613). However, the present invention does not need to be limited to using two layers as described above, and may be used even when using four or more layers by the same principle.

In addition, in the following embodiments, it is assumed that the total number of HARQ process blocks is N _proc , and the total number of such HARQ process blocks is informed by an upper layer.

Based on this, in the embodiment of the present invention, it is assumed that there is no distinction between the HARQ process block index transmitted through the first layer and the HARQ process block index transmitted through the second layer. That is, it is assumed that both HARQ process blocks transmitted through the first layer and HARQ process blocks transmitted through the second layer can be selected from {0, 1, ..., N _proc -1}.

9 is a flowchart illustrating a method of matching a process block index transmitted through two layers according to an embodiment of the present invention.

According to the present embodiment, first, in step S801, the index of the first process block transmitted through the first of two layers is determined. When the index of the first process block transmitted through the first layer is HAP _first , HAP _first may be represented as follows.

HAP _first = {x ┃x = 0, 1, ..., N _proc -1}

After determining the index of the first process block in this manner, in step S802, the number of second process block indexes transmitted through the second layer to be mapped with each of the first process block indexes as shown in Equation 3 is determined. Here, assuming that the number of second process blocks mapped per first process block index is a, a may be determined as 1, 2, ... n, where n is less than (N _proc -1) or Represent the same natural number. On the other hand, when mapping a 1st process block index and a 2nd process block index as described below, embodiment which maps a 2nd process block index from the index which is separated by ( _Nproc / 2) from the 1st process block index. In the case of a, it is preferable that a does not include a multiple of (N _proc / 2). In the above embodiment, when mapping a number of second process block index from fallen index as manil a is if it contains a multiple of (N _proc / 2) the first process from the block index (N _proc / 2), This is because the case where the first process block index and the second process block index are the same may occur.

In the present embodiment, the number a of the second process blocks mapped per first process block index may be determined according to the degree of flexibility of the HARQ process index combination between the layers and the degree of overhead of the control channel, This will be described in more detail below.

Thereafter, in step S803, the first process block index and the second process block index are mapped based on the information determined through steps S801 and S802 to form a process index combination. Specifically, the present embodiment proposes to cyclically map as many as a second process block index determined in step S802 from the index having a difference from the first process block index by a predetermined index within the entire process block index range. . In this case, the difference by the predetermined index may be any number, and in the present embodiment, it is assumed that the number N _proc of the total process block index is divided by the number of layers. However, in some cases, the number of total process block indexes N _proc divided by the number of layers may not be an integer. In such a case, the predetermined index difference in the present embodiment is that the total number of process block indexes N _proc divided by the number of layers N _proc divided by the number of layers is divided by the number of layers N _proc . It is also possible to use an integer close to the divided number. However, hereinafter, it is assumed that the number of layers used as described above is two, and for convenience, the predetermined index difference is assumed to be N _proc / 2, that is, half of the total number of process blocks.

In this case, the mapping method as in step S803 may be represented by the following equation.

HAP _second = (y ┃y = (x + (N _proc / 2) + k _HAP ) mod (N _proc ), k _HAP = 0, 1, ..., a-1}

Here, HAP _second represents a set of second process block index y mapped to a specific first process block index x of HAP _first , and k _HAP is a second process block index mapped per specific first process block index. As a variable according to the number a of k _HAP as in Equation 4 = 0, 1, ..., a-1. If a-1 is greater than (N _proc / 2) and less than (N _proc ), k _HAP = 0, 1, ..., (N _proc / 2) -1, (N _proc / 2) +1 , ..., may be set to a-1. In addition, in terms of maintaining the number of second process block indexes mapped per first process block index as a, k _HAP is k _HAP = 0, 1, ..., (N _proc / 2) -1, (N _proc / 2) +1, ..., a may be set.

As described above, a structure for mapping the first process block index and the second process block index will now be described with reference to the accompanying drawings.

FIG. 10 illustrates a form in which a process block index transmitted through a first layer and a process block index transmitted through a second layer are mapped according to an embodiment of the present invention.

As shown in FIG. 10, in the present embodiment, the first process block index transmitted through the first layer and the second process block index transmitted through the second layer are both {0, 1, .. , N _proc -1}.

Under this assumption, the specific index of the first process block index is mapped to a second process block index by Equation 4 above. For example, a first process block index 0 is the first process block index of 0 and a predetermined index, one in this example from the second process block index N _proc / 2 having a difference of N _proc / 2, a second process in FIG. 10 mapped with the block index, and the first process block index 1 to first process block index 1 and N _proc / 2 second process block index with a difference of N _proc / 2 + a of the second process block index from the first Mapped. On the other hand, when a second process block index from the second process block index N _proc / 2 + k having a difference from the specific first process block index k by N _proc / 2 exceeds the entire process block index N _proc range, FIG. As shown in 10, it is cyclically mapped from the second process block index 0 again. Such a form is apparent to those skilled in the art through Equation 4.

FIG. 10 is a view on the assumption that the number a of the second process block indexes mapped per first process block index is smaller than N _proc / 2, and in the present embodiment, when a is equal to or larger than N _proc / 2, As described above, a second index may be mapped to the second process block index mapped per first process block index except for the same index as the first process block index.

As in the present embodiment, when the first process block index and the second process block index are cyclically mapped within the entire process block index range, the number of process block index combinations transmitted through the two layers is efficiently reduced. In addition, the flexibility of process block index combinations can be increased by minimizing the number of overlapping combinations.

On the other hand, in some cases, the entire HARQ process block index combination may be represented by the number of bits having a specific size, for example, s bits. According to an embodiment of the present invention, when the entire process block index combination is to be represented by the number of bits having a specific size, the second process block index k _HAP mapped per first process block index determined in step S802 of FIG. 9. Is determined to be 2 ^s . Looking at such an embodiment in more detail as follows.

First, assume the following variable b.

b = (2 ^s ) mod (N _proc )

If the variable b defined as described above is 0, the number of cases that can be represented by the number of bits s means a multiple of the number N _proc that the first process block can have. The number of two process block indexes means that it can be determined by any particular number. Accordingly, the number of second process block indexes mapped per first process block index may be determined as (2 ^s / N _proc ). Accordingly, k _HAP in Equation 4 may be defined as follows.

k _HAP = {0, 1, ..., n}: The number of k _HAPs is and does not include a multiple of (N _proc / 2).

That is, in Equation 6, the number of k _HAPs is (2 ^s / N _proc ), and in order to prevent duplication of the first process block index and the second process block index in the present embodiment, (N _proc / 2) It does not contain the waste water.

On the other hand, when b defined according to Equation 5 is not 0, since the number that can be represented by the number of bits s means that it is not a multiple of the number N _proc that the first process block may have, This means that the specific number of second process block indexes mapped per one process block index cannot be determined. In this case, the present embodiment proposes to determine the number (k _HAP ) of the second process block indexes that can be mapped per first process block index x as follows.

For (x == 0; x <b; x ++}

k _HAP = {0, 1, ..., n}: The number of k _HAPs is

, Not including a multiple of (N _proc / 2).

For (x == b; x <(N _proc -1); x ++}

k _HAP = {0, 1, ..., n}: The number of k _HAPs is

, Not including a multiple of (N _proc / 2).

That is, Equation 7 is performed per first process block index when the first process block index x is smaller than b.

Second process block indexes are mapped, and if the second process block index x is greater than or equal to b,

Two second process block indexes are mapped, but as described above, in order to prevent duplication of the first process block index and the second process block index in the present embodiment, the k _HAP does not include a multiple of (N _proc / 2). It can be seen that it is set to not.

According to such a method, the number of second process block indexes mapped per first process block index may be adjusted so that the total process block index combination is 2 ^s . Accordingly, the mapping scheme of Equation 4 may be represented again as follows. At this time, the number of second process block indexes mapped per first process block index is not fixed to a as in Equation 4, but according to Equation 6 or 7

dog,

Dog or

You can have a dog.

HAP _second = (y ┃y = (x + (N _proc / 2) + k _HAP ) mod (N _proc )}

In addition, the mapping form of the first process block index and the second process block index in this manner is the same as in FIG. 10, except that only the number of second process block indexes mapped per first process block index is represented by Equation 6 or It has a form adjusted according to the equation (7).

Meanwhile, as described above with reference to Equation 4, as a result of assuming that the number of second process block indexes mapped per first process block index is a, the total process block index combination is shown. If the number is not a power of 2, the process block index combination corresponding to the power of 2 may be generated in the same manner as described above with reference to Equations 6 to 8, and the remaining combinations may be added using the same. . A more detailed description of such a method is as follows.

First, when the number of second process block indexes mapped per first process block index is a, the total number of process block index combinations generated is equal to a * N _proc . Therefore, to represent the total process block index combination at this time, the minimum number of bits s may be obtained as follows.

Accordingly, the process block index combination that can be represented by using the entire s bits can be obtained in the same manner as described above with reference to Equations 6 to 8, and in the present embodiment, the process block index combinations obtained as described above are used. A method of adding a corresponding number of combinations to a process block index combination derived by assuming that the number of second process block index combinations mapped per first process block index is a is provided. This minimizes the waste of signaling bits to indicate the process block index combination.

Meanwhile, a method of efficiently constructing a process block index combination when a whole process block index is grouped into an index for a first process block and an index for a second process block according to another embodiment of the present invention will be described. . Specifically, in the present embodiment, the first process block index is selected from {0, 1, ... (N _proc / 2 -1)}, and the second process block index is {(N _proc / 2), (N _proc / 2 + 1), ..., (N _proc- 1)}.

Under this assumption, first, a case is determined in which the number of second process block indexes mapped per first process block index is determined as a in step S802 of FIG. 9. In this case, a may be selected according to the degree of flexibility of the process block index combination between the layers and the degree of overhead of the control channel, and may be expressed as a = 0, 1, ..., n. In addition, n may represent a natural number less than or equal to (N _proc / 2 −1). In addition, when the entire process block index is grouped into the index for the first process block and the index for the second process block as in the present embodiment, the second process block is mapped to the first process block index as in the above-described embodiment. When selecting a index as an index, it can be seen that a problem does not occur in which the first process block index and the second process block index are the same. Therefore, in the present embodiment, unlike the above-described embodiment, there is an advantage that the constraint that a value should not include a multiple of N _proc / 2 is unnecessary.

Meanwhile, in the present embodiment, the mapping between the first process block index and the second process block index in step S803 of FIG. 9 may be performed in the following manner.

HAP _second = (y ┃y = [(x + (N _proc / 2) + k _HAP ) mod (N _proc / 2)] + N _proc / 2, k _HAP = 0, 1, ..., a-1}

Here, x represents a specific first process block index as in the above-described embodiment, and y represents a second process block index mapped to such a first process block index.

As can be seen from Equation 10, in the present embodiment, unlike the above-described embodiment, the second process block index is not cyclically mapped within the entire process block index range, but grouped for the second process block index. It can be seen that it is cyclically mapped in the index range (in the above example, {(N _proc / 2), (N _proc / 2 +1), ..., (N _proc -1)}).

As such, when the entire process block index is grouped into indexes for the first process block and indexes for the second process block, the total number of possible process block index combinations is reduced, thereby indicating the corresponding process block index combination. The advantage is that the number of signaling bits required can be further reduced.

On the other hand, in the present embodiment based on grouping of all process block indexes, there may be a case where the entire combination of process block indexes must be represented by a specific number of bits, for example, s bits. In this case, depending on whether the number of cases that can be represented by a given number of bits as described above with respect to Equation 5 is a multiple of the total number of process block indices (that is, according to the b value of Equation 5), FIG. In operation S802 of FIG. 9, the number of second process block indexes mapped per first process block index may be determined as follows.

First, when the variable b defined as in Equation 5 is 0, the number of cases that can be represented by the number of bits s means a multiple of the number N _proc that the first process block may have. The number of second process block indexes mapped per block index may be determined by any particular number as follows (2 ^s / N _proc ). Therefore, k _HAP in Equation 4 may be defined as follows.

k _HAP = {0, 1, ..., (2 ^s / N _proc ) -1}

As can be seen from Equation 11 in comparison with Equation 6, in the present embodiment in which the entire process block index is grouped into the index for the first process block and the index for the second process block, it is not based on the aforementioned grouping. It can be seen that unlike the embodiment there is no need for a restriction on k _HAP not to include multiples of {(N _proc / 2).

On the other hand, when b defined according to Equation 5 is not 0, the number of cases that can be represented by the number of bits s as described above is not a multiple of the number N _proc that the first process block index may have. Therefore, it means that the specific number of second process block indexes mapped per first process block index cannot be determined. In this case, the second process block index k _HAP that can be mapped per first process block index x in this embodiment can be determined as follows.

For (x == 0; x <b; x ++}

For (x == b; x <(N _proc -1); x ++}

As can be seen from Equation 12 compared with Equation 7, in the present embodiment in which the entire process block index is grouped into the index for the first process block and the index for the second process block, it is not based on the aforementioned grouping. It can be seen that unlike the embodiment there is no need for a restriction on k _HAP not to include multiples of {(N _proc / 2).

That is, when the b value in Equation 5 is not 0, the number of second process block indexes mapped per first process block index as shown in Equation 11 is determined as a specific number (

Can be determined. In addition, when the value of b in Equation 5 is not 0, the number of second process block indexes mapped per first process block index according to each range by dividing the range of the first process block index as shown in Equation 12. To

Dog or

You can decide by dog.

Accordingly, the entire process block index combination may be represented as in Equation 8.

In addition, in the present embodiment based on grouping of all process block indexes, when the total number of process block index combinations generated by determining a number of second process block indexes mapped per first process block index is not a power of two. The required number of bits s according to Equation 9 is obtained, and the number of bits s according to Equation 5, Equation 9, Equation 11 and Equation 12 is obtained using the index combination derived based on a number. The combination of the corresponding number of process block index combinations that can be represented may be performed. This prevents wasting of signaling bits by setting the total number of process block index combinations to be a power of two.

Hereinafter, a method of signaling a process block index combination constructed according to the first aspect of the present invention as described above will be described.

II. Second Aspect-of Process Block Index Combinations Signaling  Way

In the second aspect of the present invention, a method of signaling to the receiving side which index combination is the HARQ process block combination transmitted by the transmitting side using the HARQ process block index combination configured as described in the first aspect. see. In one embodiment of the present invention for this purpose, a process block index combination constituted according to the first aspect of the present invention is represented by a table, and signaling whether the process block index combination transmitted is a process block index combination in the table. Suggest a method. In addition, another embodiment of the present invention proposes a method in which a transmitting side directly signals to a receiving side about variables necessary to obtain a process block index combination constructed according to the first aspect of the present invention.

First Embodiment-Using a Table Signaling  Way

In the present embodiment, in a communication system using a plurality of layers, in signaling index combinations of process blocks transmitted through a plurality of layers per predetermined transmission unit, first, the same method as in the first aspect of the present invention described above is performed. The table is constructed using a combination of process block indexes to which the first process block index and the second process block index are mapped.

For example, if the total number of process block indexes N _proc is 16 and HARQ process block indexes can be transmitted through two layers at the same time, a combination of the first process block index and the second process block index ( x, y), the following table can be constructed in each case.

First, when the total process block index is not divided into the index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 1, or the entire process block index When 4 bits are represented by signaling bits, a table can be configured as follows.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,8) 4 (4,12) 8 (8,0) 12 (12,4) One (1,9) 5 (5,13) 9 (9,1) 13 (13,5) 2 (2,10) 6 (6,14) 10 (10,2) 14 (14,6) 3 (3,11) 7 (7,15) 11 (11,3) 15 (15,7)

In addition, when the entire process block index is not divided into an index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 2, or the entire process block index In the case of representing 5 bits of signaling bits, a table can be configured as follows.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,8) 8 (4,12) 16 (8,0) 24 (12,4) One (0,9) 9 (4,13) 17 (8,1) 25 (12,5) 2 (1,9) 10 (5,13) 18 (9,1) 26 (13,5) 3 (1,10) 11 (5,14) 19 (9,2) 27 (13,6) 4 (2,10) 12 (6,14) 20 (10,2) 28 (14,6) 5 (2,11) 13 (6,15) 21 (10,3) 29 (14,7) 6 (3,11) 14 (7,15) 22 (11,3) 30 (15,7) 7 (3,12) 15 (7,0) 23 (11,4) 31 (15,8)

In addition, when the entire process block index is divided into an index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 4, or the entire process block index In the case of representing 6-bit signaling bits, a table can be configured as follows.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,8) 5 (4,12) 32 (8,0) 48 (12,4) One (0,9) 6 (4,13) 33 (8,1) 49 (12,5) 2 (0,10) 7 (4,14) 34 (8,2) 50 (12,6) 3 (0,11) 8 (4,15) 35 (8,3) 51 (12,7) 4 (1,9) 20 (5,13) 36 (9,1) 52 (13,5) 5 (1,10) 21 (5,14) 37 (9,2) 53 (13,6) 6 (1,11) 22 (5,15) 38 (9,3) 54 (13,7) 7 (1,12) 23 (5,0) 39 (9,4) 55 (13,8) 8 (2,10) 24 (6,14) 40 (10,2) 56 (14,6) 9 (2,11) 25 (6,15) 41 (10,3) 57 (14,7) 10 (2,12) 26 (6,0) 42 (10,4) 58 (14,8) 11 (2,13) 27 (6,1) 43 (10,5) 59 (14,9) 12 (3,11) 28 (7,15) 44 (11,3) 60 (15,7) 13 (3,12) 29 (7,0) 45 (11,4) 61 (15,8) 14 (3,13) 30 (7,1) 46 (11,5) 62 (15,9) 15 (3,14) 31 (7,2) 47 (11,6) 63 (15,10)

In addition, when the entire process block index is divided into an index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 2, or the entire process block index When 4 bits are represented by signaling bits, a table can be configured as follows.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,8) 4 (2,10) 8 (4,12) 12 (6,14) One (0,9) 5 (2,11) 9 (4,13) 13 (6,15) 2 (1,9) 6 (3,11) 10 (5,13) 14 (7,15) 3 (1,10) 7 (3,12) 11 (5,14) 15 (7,8)

In addition, when the entire process block index is divided into an index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 4, or the entire process block index In the case of representing 5 bits of signaling bits, a table can be configured as follows.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,8) 8 (2,10) 16 (4,12) 24 (6,14) One (0,9) 9 (2,11) 17 (4,13) 25 (6,15) 2 (0,10) 10 (2,12) 18 (4,14) 26 (6,8) 3 (0,11) 11 (2,13) 19 (4,15) 27 (6,9) 4 (1,9) 12 (3,11) 20 (5,13) 28 (7,15) 5 (1,10) 13 (3,12) 21 (5,14) 29 (7,8) 6 (1,11) 14 (3,13) 22 (5,15) 30 (7,9) 7 (1,12) 15 (3,14) 23 (5,8) 31 (7,10)

In addition, when the entire process block index is divided into an index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 8, or the entire process block index In the case of representing 6-bit signaling bits, a table can be configured as follows.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,8) 16 (2,10) 32 (4,12) 48 (6,14) One (0,9) 17 (2,11) 33 (4,13) 49 (6,15) 2 (0,10) 18 (2,12) 34 (4,14) 50 (6,8) 3 (0,11) 19 (2,13) 35 (4,15) 51 (6,9) 4 (0,12) 20 (2,14) 36 (4,8) 52 (6,10) 5 (0,13) 21 (2,15) 37 (4,9) 53 (6,11) 6 (0,14) 22 (2,8) 38 (4,10) 54 (6,12) 7 (0,15) 23 (2,9) 39 (4,11) 55 (6,13) 8 (1,9) 24 (3,11) 40 (5,13) 56 (7,15) 9 (1,10) 25 (3,12) 41 (5,14) 57 (7,8) 10 (1,11) 26 (3,13) 42 (5,15) 58 (7,9) 11 (1,12) 27 (3,14) 43 (5,8) 59 (7,10) 12 (1,13) 28 (3,15) 44 (5,9) 60 (7,11) 13 (1,14) 29 (3,8) 45 (5,10) 61 (7,12) 14 (1,15) 30 (3,9) 46 (5,11) 62 (7,13) 15 (1,8) 31 (3,10) 47 (5,12) 63 (7,14)

Meanwhile, when the total number of process block indexes N _proc is 14 and HARQ process block indexes can be transmitted through two layers at the same time, a combination of the first process block index and the second process block index (x, As shown in y), the following table can be constructed in each case.

First, when the total process block index is not divided into the index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 1, the table is configured as follows. can do.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 4 (4,11) 8 (8,1) 12 (12,5) One (1,8) 5 (5,12) 9 (9,2) 13 (13,6) 2 (2,9) 6 (6,13) 10 (10,3) 14 - 3 (3,10) 7 (7,0) 11 (11,4) 15 -

In order to transmit the process block index combination as shown in Table 8, 4 bits of signaling bits are required. Can be represented. This is the same as the case in which the entire process block index is not divided into the index for the first process block and the second process block index, and the entire process block index is represented by 4 bits of signaling bits.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 4 (2,9) 8 (6,13) 12 (10,3) One (0,8) 5 (3,10) 9 (7,0) 13 (11,4) 2 (1,8) 6 (4,11) 10 (8,1) 14 (12,5) 3 (1,9) 7 (5,12) 11 (9,2) 15 (13,6)

In addition, if the total process block index is not divided into the index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 2, the table is as follows. Can be configured.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 8 (4,11) 16 (8,1) 24 (12,5) One (0,8) 9 (4,12) 17 (8,2) 25 (12,6) 2 (1,8) 10 (5,12) 18 (9,2) 26 (13,6) 3 (1,9) 11 (5,13) 19 (9,3) 27 (13,7) 4 (2,9) 12 (6,13) 20 (10,3) 28 - 5 (2,10) 13 (6,0) 21 (10,4) 29 - 6 (3,10) 14 (7,0) 22 (11,4) 30 - 7 (3,11) 15 (7,1) 23 (11,5) 31 -

In order to transmit the process block index combination as shown in Table 10, 5 bits of signaling bits are required. Therefore, when the combination remaining in Table 10 is filled according to the method according to the first aspect of the present invention as described above, Can be represented. This is the same as the case in which the entire process block index is not divided into an index for the first process block and the second process block index, and the entire process block index is represented by 5 bits of signaling bits.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 8 (2,11) 16 (6,13) 24 (10,3) One (0,8) 9 (3,10) 17 (6,0) 25 (10,4) 2 (0,9) 10 (3,11) 18 (7,0) 26 (11,4) 3 (1,8) 11 (3,12) 19 (7,1) 27 (11,5) 4 (1,9) 12 (4,11) 20 (8,1) 28 (12,5) 5 (1,10) 13 (4,12) 21 (8,2) 29 (12,6) 6 (2,9) 14 (5,12) 22 (9,2) 30 (13,6) 7 (2,10) 15 (5,13) 23 (9,3) 31 (13,7)

In addition, when the total process block index is not divided into the index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 4, the table is as follows. Can be configured.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 16 (4,11) 32 (8,1) 48 (12,5) One (0,8) 17 (4,12) 33 (8,2) 49 (12,6) 2 (0,9) 18 (4,13) 34 (8,3) 50 (12,7) 3 (0,10) 19 (4,0) 35 (8,4) 51 (12,8) 4 (1,8) 20 (5,12) 36 (9,2) 52 (13,6) 5 (1,9) 21 (5,13) 37 (9,3) 53 (13,7) 6 (1,10) 22 (5,0) 38 (9,4) 54 (13,8) 7 (1,11) 23 (5,1) 39 (9,5) 55 (13,9) 8 (2,9) 24 (6,13) 40 (10,3) 56 - 9 (2,10) 25 (6,0) 41 (10,4) 57 - 10 (2,11) 26 (6,1) 42 (10,5) 58 - 11 (2,12) 27 (6,2) 43 (10,6) 59 - 12 (3,10) 28 (7,0) 44 (11,4) 60 - 13 (3,11) 29 (7,1) 45 (11,5) 61 - 14 (3,12) 30 (7,2) 46 (11,6) 62 - 15 (3,13) 31 (7,3) 47 (11,7) 63 -

In order to transmit the process block index combination as shown in Table 12, 6-bit signaling bits are required. Can be represented. This is the same as the case in which the entire process block index is not divided into the index for the first process block and the second process block index, and the entire process block index is represented by 6 bits of signaling bits.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 16 (3,11) 32 (6,1) 48 (10,3) One (0,8) 17 (3,12) 33 (6,2) 49 (10,4) 2 (0,9) 18 (3,13) 34 (6,3) 50 (10,5) 3 (0,10) 19 (3,0) 35 (7,0) 51 (10,6) 4 (0,11) 20 (4,11) 36 (7,1) 52 (11,4) 5 (1,8) 21 (4,12) 37 (7,2) 53 (11,5) 6 (1,9) 22 (4,13) 38 (7,3) 54 (11,6) 7 (1,10) 23 (4,0) 39 (7,4) 55 (11,7) 8 (1,11) 24 (4,1) 40 (8,1) 56 (12,5) 9 (1,12) 25 (5,12) 41 (8,2) 57 (12,6) 10 (2,9) 26 (5,13) 42 (8,3) 58 (12,7) 11 (2,10) 27 (5,0) 43 (8,4) 59 (12,8) 12 (2,11) 28 (5,1) 44 (9,2) 60 (13,6) 13 (2,12) 29 (5,2) 45 (9,3) 61 (13,7) 14 (2,13) 30 (6,13) 46 (9,4) 62 (13,8) 15 (3,10) 31 (6,0) 47 (9,5) 63 (13,9)

In addition, when the entire process block index is divided into an index for the first process block and a second process block index, and the number a of the second process block indexes mapped per first process block index is 2, the table is configured as follows. can do.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 4 (2,9) 8 (4,11) 12 (6,13) One (0,8) 5 (2,10) 9 (4,12) 13 (6,7) 2 (1,8) 6 (3,10) 10 (5,12) 14 - 3 (1,9) 7 (3,11) 11 (5,13) 15 -

In order to transmit the process block index combination as shown in Table 14, four bits of signaling bits are required. Can be represented. This is the same as when the entire process block index is divided into an index for the first process block and the second process block index, and the entire process block index is represented by 4 bits of signaling bits.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 4 (1,9) 8 (3,10) 12 (5,12) One (0,8) 5 (1,10) 9 (3,11) 13 (5,13) 2 (0,9) 6 (2,9) 10 (4,11) 14 (6,13) 3 (1,8) 7 (2,10) 11 (4,12) 15 (6,7)

In addition, when the entire process block index is divided into an index for the first process block and a second process block index, and the number a of the second process block indexes mapped per first process block index is 4, the table is configured as follows. can do.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 8 (2,9) 16 (4,11) 24 (6,13) One (0,8) 9 (2,10) 17 (4,12) 25 (6,7) 2 (0,9) 10 (2,11) 18 (4,13) 26 (6,8) 3 (0,10) 11 (2,12) 19 (4,7) 27 (6,9) 4 (1,8) 12 (3,10) 20 (5,12) 28 - 5 (1,9) 13 (3,11) 21 (5,13) 29 - 6 (1,10) 14 (3,12) 22 (5,7) 30 - 7 (1,11) 15 (3,13) 23 (5,8) 31 -

In order to transmit the process block index combinations as shown in Table 16, 5-bit signaling bits are required. Therefore, when the combinations remaining in Table 16 are filled according to the method according to the first aspect of the present invention as described above, Can be represented. This is the same as the case where the entire process block index is divided into an index for the first process block and a second process block index, and the entire process block index is represented by 5 bits of signaling bits.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 8 (1,11) 16 (3,11) 24 (5,12) One (0,8) 9 (1,12) 17 (3,12) 25 (5,13) 2 (0,9) 10 (2,9) 18 (3,13) 26 (5,7) 3 (0,10) 11 (2,10) 19 (3,7) 27 (5,8) 4 (0,11) 12 (2,11) 20 (4,11) 28 (6,13) 5 (1,8) 13 (2,12) 21 (4,12) 29 (6,7) 6 (1,9) 14 (2,13) 22 (4,13) 30 (6,8) 7 (1,10) 15 (3,10) 23 (4,7) 31 (6,9)

In addition, when the entire process block index is divided into an index for the first process block and a second process block index, and the number a of the second process block indexes mapped per first process block index is 7, the table is configured as follows. can do.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,7) 16 (2,11) 32 (4,8) 48 (6,12) One (0,8) 17 (2,12) 33 (4,9) 49 - 2 (0,9) 18 (2,13) 34 (4,10) 50 - 3 (0,10) 19 (2,7) 35 (5,12) 51 - 4 (0,11) 20 (2,8) 36 (5,13) 52 - 5 (0,12) 21 (3,10) 37 (5,7) 53 - 6 (0,13) 22 (3,11) 38 (5,8) 54 - 7 (1,8) 23 (3,12) 39 (5,9) 55 - 8 (1,9) 24 (3,13) 40 (5,10) 56 - 9 (1,10) 25 (3,7) 41 (5,11) 57 - 10 (1,11) 26 (3,8) 42 (6,13) 58 - 11 (1,12) 27 (3,9) 43 (6,7) 59 - 12 (1,13) 28 (4,11) 44 (6,8) 60 - 13 (1,7) 29 (4,12) 45 (6,9) 61 - 14 (2,9) 30 (4,13) 46 (6,10) 62 - 15 (2,10) 31 (4,7) 47 (6,11) 63 -

Meanwhile, when the total number of process block indexes N _proc is 12 and HARQ process block indexes can be transmitted through two layers at the same time, a combination of the first process block index and the second process block index (x, As shown in y), the following table can be constructed in each case.

First, when the total process block index is not divided into the index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 1, the table is configured as follows. can do.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 4 (4,10) 8 (8,2) 12 - One (1,7) 5 (5,11) 9 (9,3) 13 - 2 (2,8) 6 (6,0) 10 (10,4) 14 - 3 (3,9) 7 (7,1) 11 (11,5) 15 -

In order to transmit the process block index combination as shown in Table 19, four bits of signaling bits are required. Can be represented. This is the same as when the entire process block index is divided into an index for the first process block and the second process block index, and the entire process block index is represented by 4 bits of signaling bits.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 4 (2,8) 8 (4,10) 12 (8,2) One (0,7) 5 (2,9) 9 (5,11) 13 (9,3) 2 (1,7) 6 (3,9) 10 (6,0) 14 (10,4) 3 (1,8) 7 (3,10) 11 (7,1) 15 (11,5)

In addition, if the total process block index is not divided into the index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 2, the table is as follows. Can be configured.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 8 (4,10) 16 (8,2) 24 - One (0,7) 9 (4,11) 17 (8,3) 25 - 2 (1,7) 10 (5,11) 18 (9,3) 26 - 3 (1,8) 11 (5,0) 19 (9,4) 27 - 4 (2,8) 12 (6,0) 20 (10,4) 28 - 5 (2,9) 13 (6,1) 21 (10,5) 29 - 6 (3,9) 14 (7,1) 22 (11,5) 30 - 7 (3,10) 15 (7,2) 23 (11,6) 31 -

In order to transmit the combination of the process block indexes as shown in Table 21, signaling bits of 5 bits are required. Can be represented. This is the same as the case in which the entire process block index is not divided into an index for the first process block and the second process block index, and the entire process block index is represented by 5 bits of signaling bits.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 8 (2,10) 16 (5,0) 24 (8,2) One (0,7) 9 (3,9) 17 (5,1) 25 (8,3) 2 (0,8) 10 (3,10) 18 (6,0) 26 (9,3) 3 (1,7) 11 (3,11) 19 (6,1) 27 (9,4) 4 (1,8) 12 (4,10) 20 (6,2) 28 (10,4) 5 (1,9) 13 (4,11) 21 (7,1) 29 (10,5) 6 (2,8) 14 (4,0) 22 (7,2) 30 (11,5) 7 (2,9) 15 (5,11) 23 (7,3) 31 (11,6)

In addition, when the total process block index is not divided into the index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 5, the table is as follows. Can be configured.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 16 (3,10) 32 (6,2) 48 (9,6) One (0,7) 17 (3,11) 33 (6,3) 49 (9,7) 2 (0,8) 18 (3,0) 34 (6,4) 50 (10,4) 3 (0,9) 19 (3,1) 35 (7,1) 51 (10,5) 4 (0,10) 20 (4,10) 36 (7,2) 52 (10,6) 5 (1,7) 21 (4,11) 37 (7,3) 53 (10,7) 6 (1,8) 22 (4,0) 38 (7,4) 54 (10,8) 7 (1,9) 23 (4,1) 39 (7,5) 55 (11,5) 8 (1,10) 24 (4,2) 40 (8,2) 56 (11,6) 9 (1,11) 25 (5,11) 41 (8,3) 57 (11,7) 10 (2,8) 26 (5,0) 42 (8,4) 58 (11,8) 11 (2,9) 27 (5,1) 43 (8,5) 59 (11,9) 12 (2,10) 28 (5,2) 44 (8,6) 60 - 13 (2,11) 29 (5,3) 45 (9,3) 61 - 14 (2,0) 30 (6,0) 46 (9,4) 62 - 15 (3,9) 31 (6,1) 47 (9,5) 63 -

In order to transmit the process block index combination as shown in Table 23, 6-bit signaling bits are required. Therefore, when the combination remaining in Table 23 is filled according to the method according to the first aspect of the present invention as described above, Can be represented. This is the same as the case in which the entire process block index is not divided into an index for the first process block and the second process block index, and the entire process block index is represented by 6 bits of signaling bits.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 16 (2,0) 32 (5,2) 48 (8,6) One (0,7) 17 (2,1) 33 (5,3) 49 (9,3) 2 (0,8) 18 (3,9) 34 (6,0) 50 (9,4) 3 (0,9) 19 (3,10) 35 (6,1) 51 (9,5) 4 (0,10) 20 (3,11) 36 (6,2) 52 (9,6) 5 (0,11) 21 (3,0) 37 (6,3) 53 (9,7) 6 (1,7) 22 (3,1) 38 (6,4) 54 (10,4) 7 (1,8) 23 (3,2) 39 (7,1) 55 (10,5) 8 (1,9) 24 (4,10) 40 (7,2) 56 (10,6) 9 (1,10) 25 (4,11) 41 (7,3) 57 (10,7) 10 (1,11) 26 (4,0) 42 (7,4) 58 (10,8) 11 (1,0) 27 (4,1) 43 (7,5) 59 (11,5) 12 (2,8) 28 (4,2) 44 (8,2) 60 (11,6) 13 (2,9) 29 (5,11) 45 (8,3) 61 (11,7) 14 (2,10) 30 (5,0) 46 (8,4) 62 (11,8) 15 (2,11) 31 (5,1) 47 (8,5) 63 (11,9)

In addition, when the entire process block index is divided into an index for the first process block and a second process block index, and the number a of the second process block indexes mapped per first process block index is 2, the table is configured as follows. can do.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 4 (2,8) 8 (4,10) 12 - One (0,7) 5 (2,9) 9 (4,11) 13 - 2 (1,7) 6 (3,9) 10 (5,11) 14 - 3 (1,8) 7 (3,10) 11 (5,6) 15 -

In order to transmit the process block index combination as shown in Table 25, 4 bits of signaling bits are required. Therefore, when the combination remaining in Table 25 is filled according to the method according to the first aspect of the present invention as described above, Can be represented. This is the same as when the entire process block index is divided into an index for the first process block and the second process block index, and the entire process block index is represented by 4 bits of signaling bits.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 4 (1,8) 8 (2,10) 12 (4,10) One (0,7) 5 (1,9) 9 (3,9) 13 (4,11) 2 (0,8) 6 (2,8) 10 (3,10) 14 (5,6) 3 (1,7) 7 (2,9) 11 (3, 11) 15 (5,11)

In addition, when the entire process block index is divided into an index for the first process block and the second process block index, and the number a of the second process block indexes mapped per first process block index is 5, the table is configured as follows. can do.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 8 (1,10) 16 (3,10) 24 (4,8) One (0,7) 9 (1,11) 17 (3,11) 25 (5,11) 2 (0,8) 10 (2,8) 18 (3,6) 26 (5,6) 3 (0,9) 11 (2,9) 19 (3,7) 27 (5,7) 4 (0,10) 12 (2,10) 20 (4,10) 28 (5,8) 5 (1,7) 13 (2,11) 21 (4,11) 29 (5,9) 6 (1,8) 14 (2,6) 22 (4,6) 30 - 7 (1,9) 15 (3,9) 23 (4,7) 31 -

In order to transmit the combination of the process block indexes as shown in Table 27, signaling bits of 5 bits are required. Can be represented. This is the same as the case where the entire process block index is divided into an index for the first process block and a second process block index, and the entire process block index is represented by 5 bits of signaling bits.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 8 (1,9) 16 (2,6) 24 (4,6) One (0,7) 9 (1,10) 17 (3,9) 25 (4,7) 2 (0,8) 10 (1,11) 18 (3,10) 26 (4,8) 3 (0,9) 11 (1,6) 19 (3,11) 27 (5,11) 4 (0,10) 12 (2,8) 20 (3,6) 28 (5,6) 5 (0,11) 13 (2,9) 21 (3,7) 29 (5,7) 6 (1,7) 14 (2,10) 22 (4,10) 30 (5,8) 7 (1,8) 15 (2,11) 23 (4,11) 31 (5,9)

In addition, when the entire process block index is divided into an index for the first process block and a second process block index, and the number a of the second process block indexes mapped per first process block index is 6, the table is configured as follows. can do.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0,6) 16 (2,6) 32 (5,7) 48 One (0,7) 17 (2,7) 33 (5,8) 49 - 2 (0,8) 18 (3,9) 34 (5,9) 50 - 3 (0,9) 19 (3,10) 35 (5,10) 51 - 4 (0,10) 20 (3,11) 36 - 52 - 5 (0,11) 21 (3,6) 37 - 53 - 6 (1,7) 22 (3,7) 38 - 54 - 7 (1,8) 23 (3,8) 39 - 55 - 8 (1,9) 24 (4,10) 40 - 56 - 9 (1,10) 25 (4,11) 41 - 57 - 10 (1,11) 26 (4,6) 42 - 58 - 11 (1,6) 27 (4,7) 43 - 59 - 12 (2,8) 28 (4,8) 44 - 60 - 13 (2,9) 29 (4,9) 45 - 61 - 14 (2,10) 30 (5,11) 46 - 62 - 15 (2,11) 31 (5,6) 47 - 63 -

Examples of Tables 2 to 29 are examples of a case of signaling a combination of transmitted process block indexes according to a table method when a process block is transmitted through two layers as in the first aspect of the present invention. For reference, when a process block is transmitted through one layer, examples of tables that may be used for signaling according to the present embodiment are as follows. Tables 30, 31, and 32 below are examples of cases in which the total number of process block indexes N _proc is 16, 14, and 12, respectively.

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0) 4 (4) 8 (8) 12 (12) One (One) 5 (5) 9 (9) 13 (13) 2 (2) 6 (6) 10 10 14 (14) 3 (3) 7 (7) 11 (11) 15 (15)

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0) 4 (4) 8 (8) 12 (12) One (One) 5 (5) 9 (9) 13 (13) 2 (2) 6 (6) 10 10 14 - 3 (3) 7 (7) 11 (11) 15 -

HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes HARQ process number index Allocation set of HARQ processes 0 (0) 4 (4) 8 (8) 12 - One (One) 5 (5) 9 (9) 13 - 2 (2) 6 (6) 10 10 14 - 3 (3) 7 (7) 11 (11) 15 -

In the above-described embodiment, a process block index combination constituted according to the first aspect of the present invention is represented by a table, and a method of signaling whether a process block index combination transmitted is a process block index combination in the table has been described.

In the following, a method of directly transmitting a signal to a receiving side for variables necessary to obtain a process block index combination according to the first aspect of the present invention according to another embodiment of the present invention will be described.

Second Embodiment-Variables Used in Process Index Combination Configuration Signaling  Way

In the present embodiment, in a communication system using a plurality of layers, the first process block index and the second process according to the method for configuring a process block index combination according to a specific embodiment among the embodiments according to the first aspect of the present invention. Assume a case where a block index is mapped. As described above, when the process block indexes transmitted through each layer are mapped to form a combination, a method of signaling an index combination of process blocks per predetermined transmission unit according to the present embodiment may include one or more first processes transmitted through a first layer. A process of transmitting block index information (ie, HAP _first ) and a process of transmitting information of a second process block index (ie, k _HAP ) to be mapped to each of the first process block indexes.

As such, the transmitting side signals the first side of the first process block index information and the number of second process block indexes mapped to each of the first process block indexes to the receiving side. According to the received HARQ process block index combination can be seen. A signaling method according to such an embodiment will be described below with reference to a specific example.

FIG. 11 is a diagram conceptually illustrating a structure of a signaling signal used in an embodiment of the present invention for directly signaling variables used in a process block index combination configuration.

Specifically, (a) of FIG. 11 assumes that the total number of HARQ process block indexes (N _proc ) transmitted is 16 and the number (a) of second process block indexes mapped per first process block is four. It is. In addition, (a) of FIG. 11 assumes that the entire process block index is not divided into an index for a first process block transmitted through a first layer and an index for a second process block transmitted through a second layer. .

As described above, since the entire process block index is not divided into an index for the first process block and an index for the second process block, the first process block index is transmitted through the first layer as shown in FIG. One process block index (HAP _first ) is possible in 16 cases, and it can be seen that signaling bits of 4 bits are required for this. In addition, in order to indicate four second process block indexes k _HAP mapped per first process block index as described above (that is, when a = 4), FIG. 11A illustrates two bits of signaling bits. It is shown to use.

Meanwhile, similarly to FIG. 11A, in FIG. 11B, the first process in which the total number of HARQ process block indexes N _proc transmitted is 16 and the entire process block index is transmitted through the first layer is illustrated. It is assumed that the case is not divided into the index for the block and the index for the second process block transmitted through the second layer. In FIG. 11B, the number (a) of second process block indices mapped per first process block index is one.

As such, when the number (a) of second process block indexes mapped per first process block index is 1, this means that the second process block index per first process block index is mapped one-to-one, and thus, FIG. As can be seen from), the transmitter does not necessarily signal separately the second process block index information (k _HAP ) mapped per first process block index to the receiver.

The detailed description of the preferred embodiments of the invention disclosed as described above is provided to enable any person skilled in the art to make and practice the invention. Although the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art will variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. I can understand that you can. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

According to the method for configuring a process block index combination as described above and a signaling method therefor, while simultaneously transmitting a plurality of HARQ process blocks, the flexibility of the combination of HARQ process block indexes can be maintained to the maximum in a system-allowed range. At the same time, the overhead of the control signal can be reduced, so that resources can be used efficiently.

The above description of such a method has focused on the case where the number of the plurality of layers is two, and it can be seen that it has a structure suitable to be applied to the MIMO communication system of the 3GPP LTE system. However, the method for configuring the process block index combination according to the present invention and a signaling method therefor include a plurality of signal units transmitted within a predetermined transmission unit as well as the 3GPP LTE system as described above. The same principle can be applied to a wireless communication system.

1 is a diagram illustrating an example of a structure of a control signal in a conventional synchronous and asynchronous HARQ system.

2 is a view for explaining a stop-and-wait HARQ scheme.

3 illustrates an N-channel stop and weight HARQ structure.

4 is a diagram illustrating a transmission method by multiple HARQ processing.

5 is a diagram illustrating the concept of a spatial multiplexing (SM) and a spatial divisional multiple access (SM) method used in a MIMO communication system.

6 is a diagram illustrating a structure of a transmitting end of a multiple codeword (MCW) MIMO system.

7 is a diagram illustrating an example of a mapping relationship between a codeword and a physical antenna.

FIG. 8 is a diagram illustrating an example of applying 16-channel HARQ stop and weight HARQ in a two-layer MIMO communication system.

9 is a flowchart illustrating a method of matching a process block index transmitted through two layers according to an embodiment of the present invention.

FIG. 10 illustrates a form in which a process block index transmitted through a first layer and a process block index transmitted through a second layer are mapped according to an embodiment of the present invention.

FIG. 11 is a diagram conceptually illustrating a structure of a signaling signal used in an embodiment of the present invention for directly signaling variables used in a process block index combination configuration.

Claims (10)

In a communication system using a plurality of layers, a method of configuring an index combination of process blocks to be transmitted through the plurality of layers per predetermined transmission unit, A first step of determining a first process block index to transmit on a first layer of the plurality of layers; Determining a number of second process block indices to transmit on a second layer of the plurality of layers, to be mapped to each of the first process block indices; And The plurality of second process block indexes for each of the predetermined transmission units may be equal to the number of the second process block index, except for the determined first process block index, from the index having a difference from the first process block index by a predetermined index. And a third step of recursively mapping to each of the determined first process block indexes within a range of overall process block indexes to transmit through the layer. The method of claim 1, In the second step, And the number of second process block indexes is determined such that the number of total index combinations of all the process blocks is a power of two. The method of claim 1, If the total number of index combinations of the entire process block is not the power of two, adding the number of index combinations corresponding to the difference between the total index combination and the minimum power of two that can represent the total index combination And further comprising a step. The method of claim 3, wherein The index combination addition step, In the second step, the number of indexes corresponding to the difference is determined by using the index combination generated by determining the number of the second process block indexes to be the power of two total index combinations of the entire process blocks. How to add, process block index combination configuration. The method according to any one of claims 1 to 4, The full process block index includes a first group index for the first process block index and a second group index for the second process block index, In the third step, And wherein the second process block index is circularly mapped within the second group index range. The method of claim 1, The difference between the first process block index and the predetermined index of the second process block index by the number determined in the second step is: And a half of the total number of process block indexes. The method of claim 1, The communication system is an asynchronous HARQ communication system, And the predetermined transmission unit is a round trip delay time. The method of claim 1, The communication system is a MIMO communication system, And said plurality of layers are a plurality of transmit antennas used by a transmitting side. In a communication system using a plurality of layers, a method for signaling an index combination of process blocks transmitted through the plurality of layers per predetermined transmission unit, According to any one of claims 1 to 8, according to the method for configuring a process block index combination, the table by setting a table index per process block index combination to which the first process block index and the second process block index is mapped Constructing; And Transmitting a table index corresponding to an index combination of process blocks transmitted through the plurality of layers per predetermined transmission unit among all table indexes of the table. In a communication system using a plurality of layers, when the first process block index and the second process block index are mapped according to the method for configuring a process block index combination according to any one of claims 1 to 8. A method for signaling index combinations of the process blocks transmitted through the plurality of layers per predetermined transmission unit, Transmitting one or more first process block index information transmitted on the first layer; And Transmitting information of the second process block index to be mapped with each of the first process block index.

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