KR20090017103A - Semiconductor memory apparatus - Google Patents

Abstract

A semiconductor memory device is provided to reduce a test time by securing a minimum write operation completion time in a wafer test process. A semiconductor memory device includes a pre-charge signal generating unit(10) and an output control unit(100). The pre-charge signal generating unit generates a preliminary pre-charge(pre-pcg) signal after a write command is inputted. The output control unit enables a pre-charge signal(pcg) when a clock enable signal(CKE) is disabled in a test process. The output control unit outputs the preliminary pre-charge signal as the pre-charge signal in the remaining process except for the test process.

Description

Semiconductor Memory Apparatus

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of measuring a minimum write operation completion time during a test.

In the semiconductor memory device, a write command is input after an active signal is input, and a write operation is started. After a predetermined time, the precharge signal is activated to start a precharge operation. In the precharge operation, when the precharge signal is input to the bank activated by the active command, the enabled word line is disabled, the sense amplifier is turned off, and the bit line is precharged. As a result, the operation of storing data by the semiconductor memory device is completed.

The time until the write command is input and the precharge signal is activated is called a write operation completion time tWR. In this case, when the write operation completion time is insufficient, the semiconductor memory device may not normally store data in the cell.

Semiconductor memory devices are largely divided into wafer test and package test to ensure the stability of the finished product. The package test is a test that was not performed in the wafer test.

If the write operation time is insufficient during the wafer test, the precharge signal may be delayed by one clock cycle to avoid defects. The lack of a write operation completion time means that the cell node has not been used for more than 90% of its potential. At this time, the clock used in the wafer test has a low frequency of about 30ns per cycle. Therefore, delaying the precharge signal by one cycle of the clock during wafer testing delays 30ns.

The package test uses a higher frequency clock than that used in wafer testing. For example, in a package test, if a wafer test is performed with a clock having a cycle of 5 ns, a defect may not occur even if the pre-charge signal is delayed by 10 ns. This shows that wafer testing alone does not allow for a minimum write completion time. Therefore, the same test twice during wafer and package occurs, and the package-level semiconductor memory device has a problem in that the semiconductor memory device must be reproduced because the circuit cannot be changed. In addition, the development time of the semiconductor memory device development problem occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and an object thereof is to provide a semiconductor memory device capable of reducing a test time while ensuring a minimum write operation completion time during a wafer test.

The semiconductor memory device according to the present invention includes a precharge signal generating means for generating a preliminary precharge signal after a predetermined time when a write command is input, and when the clock enable signal is disabled during the test, the precharge signal is enabled and is not a test. And output control means for outputting the preliminary precharge signal as the precharge signal.

The semiconductor memory device according to the present invention uses a clock enable signal to control the pre-charge timing to secure the minimum write completion time and reduce the time required for the test by testing the semiconductor memory device with the minimum write completion time. It can be effective.

A preferred embodiment of the semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 1, a semiconductor memory device according to an embodiment of the present invention includes a precharge signal generating means 10 and an output control means 100.

The precharge signal generating means 10 generates a precharge signal pre_pcg after a predetermined time when a write command is input. At this time, the precharge signal generating means 10 has the same configuration as in the prior art, and in the related art, the preliminary precharge signal pre_pcg has been used as the precharge signal pcg.

The output control means 100 generates an enabled precharge signal pcg when the test signal Test is enabled and the clock enable signal CKE is disabled, and when the test signal Test is disabled. The preliminary precharge signal pre_pcg is output as the precharge signal pcg regardless of the clock enable signal CKE.

As illustrated in FIG. 2, the output control means 100 includes first and second NAND gates ND11 and ND12, a first NOR gate NOR11, and a first inverter IV11.

The first NAND gate ND11 receives the preliminary precharge signal pre_pcg and the test signal Test. The first NOR gate NOR11 receives the test signal Test and the clock enable signal CKE. The first inverter IV11 receives the output signal of the first NOR gate NOR11. The second NAND gate ND12 receives the output signals of the first inverter IV11 and the first NAND gate ND11 to generate the precharge signal pcg.

The semiconductor memory device according to the embodiment of the present invention configured as described above operates as follows.

When a write command is input, the precharge signal generation stage 10 generates a precharge signal pre_pcg enabled high after a predetermined time.

In this case, the precharge signal pcg is enabled in response to the clock enable signal CKE regardless of the preliminary precharge signal pre_pcg.

Referring to FIG. 2, when the test signal Test is enabled low during the test, the first NAND gate ND11 outputs only a high level regardless of whether the preliminary precharge signal pre_pcg is enabled. . In addition, the first NOR gate NOR11 receives the test signal Test having a low level and inverts the clock enable signal CKE and outputs the inverted clock enable signal CKE. The first inverter IV11 inverts the output signal of the first NOR gate NOR11 and outputs the inverted signal. That is, when the test signal Test is low, the first NOR gate NOR11 and the first inverter IV11 maintain the level of the clock enable signal CKE as the second NAND gate ND12. ) The second NAND gate ND12 that receives the output signal of the first NAND gate ND11 having a high level inverts the output signal of the first inverter IV11 and outputs the inverted output signal.

As a result, the output control means 100 inverts the clock enable signal CKE when the test signal Test is low and outputs the precharge signal pcg as shown in FIG. 4. do. When the clock enable signal CKE is disabled low, the precharge signal pcg is enabled high.

When not in the test, that is, when the test signal Test is disabled, the first NAND gate ND11 inverts the preliminary precharge signal pre_pcg and outputs the inverted precharge signal. The first NOR gate NOR11 receives the test signal Test, which is disabled high, and outputs only a low level signal regardless of whether the clock enable signal CKE is enabled. The first inverter IV11, which receives the output signal of the first NOR gate NOR11 which is a low level, outputs a high level signal. The second NAND gate ND12 receives the output signal of the first inverter IV11 having a high level, inverts the output signal of the first NAND gate ND11, and outputs the inverted signal as the precharge signal pcg. In this case, the precharge signal pcg is input to the bank activated by the write operation to disable the enabled word line, turn off the sense amplifier, and precharge the bit line.

As a result, when not in the test, the output control means 100 outputs the preliminary precharge signal pre_pcg as the precharge signal pcg, as shown in FIG. 4.

The present invention finds the minimum write operation completion time at which the write operation of the semiconductor memory device can be completed by controlling the precharge timing with a clock enable signal input from an external device, which is not synchronized with a clock during the test. In addition, by testing the semiconductor memory device with a minimum write operation completion time, the test time for testing the semiconductor memory device may be reduced.

As a result, the present invention can monitor the enable timing of the precharge signal during the test by using a clock enable signal that is not synchronized with the clock, thereby reducing the time spent in the test while ensuring sufficient write completion time. .

In this case, the general semiconductor memory device enters a power down mode when the clock enable signal is disabled. Therefore, in the present invention, there is a need to provide a power down signal generating means for preventing the semiconductor memory device from entering the power down mode when using the clock enable signal during the test. FIG. 3 illustrates the power down signal generating means. When the test signal Test is enabled low, the power down signal generated power down signal power_down is generated regardless of whether the clock enable signal CKE is enabled. Prevents the semiconductor memory device from entering the power down mode. On the other hand, when the test signal Test is disabled high, when the clock enable signal CKE is disabled low, the semiconductor memory device powers down by generating the power down signal power_down enabled high. Allows you to enter mode. The power down signal generating means includes a second inverter IV21 and a second NOR gate NOR21. The second inverter IV21 receives the test signal Test. The second NOR gate NOR21 receives the clock enable signal CKE and an output signal of the second inverter IV21 to generate the power down signal power_down.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention;

2 is a circuit diagram of the output control means of FIG.

3 is a circuit diagram of a power down signal generating means that may be further included in a semiconductor memory device according to an embodiment of the present invention;

4 is a timing diagram of a semiconductor memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: precharge signal generating means 100: output control means

Claims (5)

Precharge signal generation means for generating a preliminary precharge signal after a predetermined time when a write command is input; And And output control means for enabling a precharge signal when the clock enable signal is disabled during the test and outputting the preliminary precharge signal as the precharge signal when the clock enable signal is disabled. The method of claim 1, The output control means And when the test signal is enabled and the clock enable signal is disabled, the precharge signal is enabled, and when the test signal is disabled, the preliminary precharge signal is output as the precharge signal. . The method of claim 2, The output control means A first NAND gate receiving the preliminary precharge signal and the test signal; A NOR gate receiving the test signal and the clock enable signal; An inverter receiving the output signal of the NOR gate, and And a second NAND gate configured to receive the first NAND gate and the output signal of the inverter and output the precharge signal. The method of claim 1, A power down signal generating means for enabling a power down signal when the clock enable signal is disabled when not in the test, and generating the power down signal disabled in the test regardless of the clock enable signal; The semiconductor memory device further comprises. The method of claim 4, wherein An inverter receiving the test signal, and And a NOR gate receiving the output signal of the inverter and the clock enable signal and generating the power down signal.

Images