KR20090015209A - Frequency generator employing a phase-locked loop architecture, also usable in a uwb device - Google Patents

Abstract

A frequency generator having phase locked loop structure for being used in ultra wideband device is provided to rapidly obtain a desired output frequency by performing coarse tuning by a frequency generator. A frequency generator(100) comprises a phase detector, a charge pump, a loop filter, a voltage control oscillator, a coarse tuner, and a frequency divider. The phase detector(110) detects a phase difference(PD) between an output frequency(FOUT) and a reference frequency(FREF). The charge pump(120) generates a control current(Ic) based on the phase difference. The loop filter(130) generates a control voltage(Vc) corresponding to the control current. The voltage control oscillator(140) performs a fine tuning based on the control voltage, and performs a coarse tuning based on a coarse tuning code outputted from the coarse tuner(150). The coarse tuner receives a tuning control code(TCC) of n bit, and generates the coarse tuning code. The frequency divider(160) divides an output frequency, and sends the divided output frequency(FOUT/N) to the phase detector.

Description

FREQUENCY GENERATOR EMPLOYING A PHASE-LOCKED LOOP ARCHITECTURE, ALSO USABLE IN A UWB DEVICE}

Embodiments of the present invention relate to a frequency generator, and more particularly, to a frequency generator employing a phase locked loop structure capable of generating a desired output frequency at high speed.

In general, a frequency generator is a device for generating a desired output frequency based on a reference frequency, and is widely used in an electronic field such as an ultra wideband technology (UWB) capable of transmitting a large amount of digital data in a short range.

Since the frequency generator is sensitive to external environments such as process, voltage and temperature (PVT), the frequency generator can coarsely control the capacitance of the variable capacitor to overcome this problem. coarse tuning method can be adopted.

However, if sparse tuning is not performed properly, the frequency generator may not be able to produce the desired output frequency at high speed or may not precisely control the output frequency.

An object of the present invention is to provide a frequency generator employing a phase locked loop structure capable of generating a desired output frequency at high speed in order to solve the problems of the prior art.

Another object of the present invention is to provide an integrated circuit including the frequency generator.

Another object of the present invention is to provide a method capable of generating a frequency for solving the above problem.

In order to achieve the above object, the frequency generator adopting the phase locked loop structure according to the present invention performs coarse tuning based on coarse tuning code (CTC) to adjust the output frequency to an approximation of the desired output frequency. And a coarse tuner that receives the n-bit tuning control code and generates the coarse tuning code having an average value of k / 2 ⁿ (0 <= k = <n) after a predetermined time elapses.

For example, the predetermined time may correspond to an initial setting time indicating a time at which the frequency generator can operate normally.

According to an embodiment of the present invention, the voltage controlled oscillator may include a coarse tuning unit including at least one variable capacitor for controlling capacitance based on the coarse tuning code.

The sparse tuner may include: an adder configured to receive the tuning control code and generate at least one carry bit, and a latch unit to latch the at least one carry bit; And a tuning code generator configured to generate the sparse tuning code based on the at least one carry bit and the latched at least one carry bit.

The adder may include a plurality of adders connected in series operating based on the output frequency. The adder may include a first adder configured to add the tuning control code and its output value to output a first carry bit, and add an output value of the first adder and its output value to output a second carry bit. It may include a second summer to.

The latch unit may latch the first and second carry bits output from the first and second summers included in the plurality of summers.

The tuning code generator may operate based on the output frequency, and may add a value of the latched first carry bit, a value of the second carry bit, and a negative value of the latched second carry bit.

For example, the sparse tuner may have an operating frequency that is faster than the operating frequency of the frequency generator.

The frequency generator may further include a phase detector for detecting a phase difference between a reference frequency and the output frequency, and the voltage controlled oscillator may fine tune the output frequency based on the phase difference.

In order to achieve the above object, the integrated circuit of the present invention performs coarse tuning based on coarse tuning code (CTC) to tune the voltage controlled oscillator and n bits to approach the output frequency to an approximation of the desired output frequency. A frequency generator employing a phase locked loop structure comprising a coarse tuner that receives a control code and generates the coarse tuning code having an average value of k / 2 ⁿ (0 <= k = <n) after a predetermined time. can do. For example, the integrated circuit may be used in an ultra wideband device.

The sparse tuner may include an adder configured to receive the tuning control code to generate at least one carry bit, a latch unit to latch the at least one carry bit, and the at least one carry bit and the latched at least one carry. It may include a tuning code generator for generating the sparse tuning code based on the bit.

In order to achieve the above object, a method of generating a frequency by adopting a phase locked loop structure according to the present invention is performed by performing coarse tuning based on coarse tuning code (CTC) to approximate an output frequency of an output frequency. And generating a sparse tuning code having an average value of k / 2 ⁿ (0 <= k = <n) after a predetermined time is received after receiving the n-bit tuning control code.

For example, the predetermined time may correspond to an initial setting time indicating a time at which the frequency generator can operate normally.

The generating of the coarse tuning code may include receiving the tuning control code to generate at least one carry bit, latching the at least one carry bit, and the at least one carry bit and the latched written down at least. Generating the sparse tuning code based on one or more carry bits.

One embodiment of the present invention can efficiently perform coarse tuning to generate a desired output frequency at high speed.

In addition, an embodiment of the present invention can improve coarse tuning to precisely control the output frequency.

Since descriptions of embodiments of the present invention are merely illustrated for structural to functional descriptions of the present invention, the scope of the present invention should not be construed as limited by the embodiments described in the present invention. That is, the embodiments of the present invention may be variously modified and may have various forms, and thus, it should be understood that the present invention includes equivalents capable of realizing the technical idea of the present invention.

On the other hand, the meaning of the terms described in the present invention should be understood as follows.

Terms such as “first” and “second” are used to distinguish one component from other components, and the scope of the present invention should not be limited by these terms. For example, the first component may be named a second component, and similarly, the second component may also be named a first component.

The term “and / or” should be understood to include all combinations that can be presented from one or more related items. That is, the meaning of “first item, second item and / or third item” not only includes the first, second or third item, but also presents from two or more of the first, second and third items. It means a combination of all possible items.

When a component is referred to as being "connected" to another component, it should be understood that there may be other components in between, although it may be directly connected to the other component. On the other hand, when a component is said to be "directly connected" to another component, it should be understood that there is no other component in between. On the other hand, other expressions describing the relationship between the components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to", should be interpreted as well.

Singular expressions described herein are to be understood to include plural expressions unless the context clearly indicates otherwise, and the terms "comprise" or "having" include elements, features, numbers, steps, operations, and elements described. It is to be understood that the present specification is intended to designate that there is a part or a combination thereof, and does not exclude in advance the possibility of the presence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof. do.

Each step described in the present invention may occur out of the stated order unless the context clearly dictates the specific order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and shall be interpreted as having ideal or overly formal meanings unless expressly defined in this application. Can't be.

1 is a block diagram illustrating a frequency generator employing a phase locked loop structure according to an embodiment of the present invention.

Referring to FIG. 1, the frequency generator 100 includes a phase detector 110, a charge pump 120, a loop filter 130, a voltage controlled oscillator 140, a coarse tuner 150, and a frequency divider. 160, and may further include a control unit 170 as needed.

The phase detector 110 detects a phase difference PD between the reference frequency FREF and the output frequency FOUT. In some embodiments, the phase detector 110 may detect a phase difference between the reference frequency FREF and the frequency FOUT / N divided by N times the output frequency FOUT.

The charge pump 120 generates the control current Ic based on the phase difference PD. For example, the charge pump 120 may increase the control current Ic when the phase difference PD is increased, and decrease the control current Ic when the phase difference PD is reduced.

The loop filter 130 generates a control voltage Vc corresponding to the control current Ic. For example, the loop filter 130 may increase the control voltage Vc when the phase difference PD is increased and decrease the control voltage Vc when the phase difference PD is reduced.

The voltage controlled oscillator 140 performs fine tuning based on the control voltage Vc, and coarse tuning based on the coarse tuning code (CTC) output from the coarse tuner 150. tuning). That is, the voltage controlled oscillator 140 performs coarse tuning based on coarse tuning code (CTC) to approach the output frequency FOUT to an approximation of the desired output frequency, and phase difference PD. Fine tuning is performed based on the above.

For example, the voltage controlled oscillator 140 may perform fine tuning and then fine tuning, and may fix the control voltage Vc to a predetermined value as necessary. Referring to FIG. 3, the operation of the voltage controlled oscillator 140 will be described later.

The coarse tuner 150 receives the n-bit tuning control code TCC and generates a coarse tuning code CTC having an average value of k / 2 ⁿ (0 <= k = <n) after a predetermined time. . For example, the predetermined time may correspond to an initial setting time indicating a time at which the frequency generator 100 can operate normally. Hereinafter, assuming that n corresponds to 8, the sparse tuner 150 will be described later with reference to FIG. 4.

The frequency divider 160 divides the output frequency FOUT and provides the divided output frequency FOUT / N to the phase detector 110.

The control unit 170 may provide a control code to the frequency divider 160 so that the frequency divider 160 may determine the division ratio, and provide a tuning control code TCC to the coarse tuner 150 to make the coarse tuner ( 150 to generate a coarse tuning code (CTC).

FIG. 2 is a circuit diagram illustrating the voltage controlled oscillator of FIG. 1.

Referring to FIG. 2, the voltage controlled oscillator 140 may include first and second capacitors 210 and 250, first and second inverters 220 and 230 forming a latch circuit, an inductor 240, The fine tuning unit 260, the coarse tuning unit 270, and a buffer 280 are included.

The first capacitor 210 has a first end connected to ground and the second end formed a circuit connected to the first end N1 of the latch circuit. The second capacitor 220 has a first end connected to ground. The second end forms a circuit connected to the second end N2 of the latch circuit.

The inductor 240 forms a circuit in which a first end is connected to the first end N1 of the latch circuit and a second end is connected to the second end N2 of the latch circuit.

The fine tuning unit 260 and the coarse tuning unit 260 form a circuit in which a first end is connected to the first end N1 of the latch circuit and a second end is connected to the second end N2 of the latch circuit. .

The fine tuning unit 260 performs fine tuning on the output frequency FOUT based on the control voltage Vc output from the loop filter 130. That is, the fine tuning unit 260 performs fine tuning on the output frequency FOUT based on the phase difference PD detected by the phase detector 110.

The sparse tuning unit 260 includes at least one variable capacitor that controls capacitance based on the sparse tuning code CTC, and performs sparse tuning on the output frequency FOUT based on the sparse tuning code CTC. do. That is, the sparse tuning unit 260 may receive a sparse tuning code CTC having an average value of k / 2 ⁿ (0 <= k = <n) (for example, having a floating point) at a high speed. The capacitance of the variable capacitor can be more precisely controlled to generate the output frequency.

For example, the sparse tuning unit 260 may include a pair of at least one variable capacitor having a first end connected to a first end N1 of the latch circuit and a second end connected to a second end N2 of the latch circuit. For example, 272 to 276 may be included, and pairs of variable capacitors 272 to 276 may be connected in series and may control capacitance by respective bits of the coarse tuning code CTC.

3 is a block diagram illustrating the coarse tuner of FIG. 1.

Referring to FIG. 3, the sparse tuner 150 includes an adder 310, a latch unit 320, a tuning code generator 330, and a divider 340, and is less than the operating frequency of the frequency generator 100. It can have a fast operating frequency.

The adder 310 receives the tuning control code TCC and generates at least one carry bit. According to an embodiment, the summer 310 may include a plurality of summers 312 and 314 connected in series operating based on the output frequency FOUT, and the first summer 312 may be The tuning control code TCC and its output value are added to output the first carry bit C1, and the second summer 314 sums the output value of the first summer 312 and its output value. The second carry bit C2 is output.

The latch unit 320 latches at least one carry bit output from the adder 310. According to an embodiment, the latch unit 320 may include a plurality of D flip-flops 322 and 324, and the first and second outputs from the first and second summers 312 and 314. The carry bits C1 and C2 are latched.

The tuning code generator 330 may generate a coarse tuning code CTC based on at least one carry bit output from the adder 310 and at least one carry bit latched by the latch unit 320. Create According to an exemplary embodiment, the tuning code generator 330 operates based on the output frequency FOUT, and the value of the latched first carry bit output from the first D flip-flop 322 and the adder 310. The negative value of the latched second carry bit output from the second D flip-flop 324 and the value of the second carry bit output from the second D may be summed.

As a result, the tuning code generator 330 may output a value having a range from -1 to 2, and after a predetermined time (eg, an initial setting time), k / 2 ⁿ (0 < A sparse tuning code CTC having an average value of = k = <n) may be generated.

4 is a block diagram illustrating an integrated circuit including the frequency generator of FIG. 1.

In FIG. 4, the integrated circuit 400 may be used for an electronic device including an ultra wideband device, but may also be used for other electronic devices.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Embodiments of the present invention presented above may have an effect including the following advantages. However, all the embodiments of the present invention are not meant to include them all, and thus the scope of the present invention should not be understood as being limited thereto.

One embodiment of the present invention can efficiently perform coarse tuning to generate a desired output frequency at high speed.

In addition, an embodiment of the present invention can improve coarse tuning to precisely control the output frequency.

1 is a block diagram illustrating a frequency generator employing a phase locked loop structure according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating the voltage controlled oscillator of FIG. 1.

3 is a block diagram illustrating the coarse tuner of FIG. 1.

4 is a block diagram illustrating an integrated circuit including the frequency generator of FIG. 1.

Claims (16)

A voltage controlled oscillator performing coarse tuning based on coarse tuning code (CTC) to approach an output frequency to an approximation of a desired output frequency; And Adopting a phase locked loop structure comprising a coarse tuner which receives the n-bit tuning control code and generates the coarse tuning code having an average value of k / 2 ⁿ (0 <= k = <n) after a predetermined time. Frequency generator. The oscillator of claim 1, wherein the voltage controlled oscillator And a sparse tuning unit including at least one variable capacitor for controlling capacitance based on the sparse tuning code. The frequency generator of claim 1, wherein the predetermined time corresponds to an initial setting time indicating a time at which the frequency generator is normally operated. The method of claim 1, wherein the sparse tuner An adder configured to receive the tuning control code and generate at least one carry bit; A latch unit for latching the at least one carry bit; And And a tuning code generator for generating the sparse tuning code based on the at least one carry bit and the latched at least one carry bit. The method of claim 4, wherein the adding unit And a plurality of summers connected in series operating based on the output frequency. The method of claim 5, wherein the adding unit A first adder for adding the tuning control code and its output value to output a first carry bit; And And a second adder configured to add the output value of the first adder and its output value to output a second carry bit. The method of claim 5, wherein the latch unit And latching first and second carry bits output from the first and second summers included in the plurality of summers. The method of claim 7, wherein the tuning code generation unit Operating based on the output frequency, summing the value of the latched first carry bit, the value of the second carry bit, and the negative value of the latched second carry bit. The method of claim 1, wherein the sparse tuner And an operating frequency faster than the operating frequency of the frequency generator. The method of claim 1, A phase detector for detecting a phase difference between a reference frequency and the output frequency, The voltage controlled oscillator performs fine tuning on the output frequency based on the phase difference. After coarse tuning based on coarse tuning code (CTC), a voltage control oscillator is used to approach the output frequency to an approximation of the desired output frequency and a n-bit tuning control code. And a frequency generator employing a phase locked loop structure comprising a sparse tuner for generating said sparse tuning code having an average value of 2 ⁿ (0 <= k = <n). 12. The integrated circuit of claim 11 wherein the integrated circuit is used in an Ultra WideBand (UWB) device. 12. The tuner of claim 11 wherein the sparse tuner is An adder configured to receive the tuning control code and generate at least one carry bit; A latch unit for latching the at least one carry bit; And And a tuning code generator for generating the sparse tuning code based on the at least one carry bit and the latched at least one carry bit. Performing coarse tuning based on coarse tuning code (CTC) to approach an output frequency to an approximation of a desired output frequency; And adopting a phase locked loop structure including receiving the n-bit tuning control code and generating the coarse tuning code having an average value of k / 2 ⁿ (0 <= k = <n) after a predetermined time has elapsed. How to generate a frequency. 15. The method of claim 14, wherein the predetermined time corresponds to an initial setting time representing a time during which the frequency generator can operate normally. 15. The method of claim 14, wherein generating the sparse tuning code Receiving at least one of the tuning control codes and generating at least one carry bit; Latching the at least one carry bit; And Generating the sparse tuning code based on the at least one carry bit and the latched at least one carry bit.

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