KR20090014603A - Memory device comprising resistive material layer and methods of operating and manufacturing the same - Google Patents

Abstract

A memory device comprising resistive material layer and methods is provided to reduce the contact area between the resistance material layer and the bottom electrode by using the minute a nano-wire as the bottom electrode. A memory device comprises a storage node(S1) and switching element(300) connected to the storage node. The storage node comprises the conductive nano-wire(210), a resistance material layer(220) and an electrode(230). The conductive nano-wire is on the substrate(200) parallel with the substrate. The resistance material layer is formed in a part phase of the nano-wire, and the electrode is formed on the resistance material layer. The switching element is the diode equipped on the electrode.

Description

Memory device comprising resistive material layer and methods of operating and manufacturing the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and to an operation and manufacturing method thereof, and more particularly, to a memory device including a resistive material layer and an operation and a manufacturing method thereof.

The memory device may be classified into a volatile memory device in which written data is erased while the power is largely cut off, and a nonvolatile memory device that is not. Recently, with the growth of Internet technology and the increase in the penetration rate of mobile communication devices, interest in nonvolatile memory devices is increasing. Non-volatile memory devices are currently widely used flash memory devices, but ferroelectric RAM (FeRAM), magnetic RAM (MRAM), Sonos (SONOS) memory devices, resistive memory devices such as RRAM (resistive random access memory) or PRAM Next-generation devices, such as phase change random access memory, are being introduced one after another, and some of them are in limited production.

RRAM and PRAM are distinguished from other nonvolatile memory devices in that they include a resistor in the storage node. The PRAM contains a phase change layer that changes from amorphous to crystalline or vice versa depending on the conditions given to the storage node. The crystalline phase change layer is heated to a temperature higher than the melting temperature (melting temperature) for a short time (hereinafter referred to as a first time) and then cooled at a high rate to change to an amorphous state. The amorphous phase change layer is heated to a temperature lower than the melting temperature and above the crystallization temperature for a longer time than the first time and then cooled to a crystalline state. The resistance of the phase change layer is high when it is amorphous and low when it is crystalline. The PRAM uses this resistance characteristic of the phase change layer to write and read bit data.

As shown in FIG. 1, a storage node of a general PRAM includes a lower electrode 10, a lower electrode contact layer 11, a phase change layer 12, and an upper electrode 13. The lower electrode contact layer 11 perpendicular to the lower electrode 10 is provided on the lower electrode 10, and the phase change layer 12 and the upper electrode 13 are sequentially provided on the lower electrode contact layer 11. do. In the storage node, when a predetermined current flows between the lower electrode 10 and the upper electrode 13, the current flows through the contact surface A1 of the lower electrode contact layer 11 and the phase change layer 12. Joule heat is generated, and the phase of a portion of the phase change layer 12 in contact with the lower electrode contact layer 11 is changed. The smaller the contact surface A1 is, the smaller the current required to change the phase of the phase change layer 12 is. Therefore, in order to lower the operating current of the PRAM, the size of the contact surface A1 should be as small as possible.

However, due to the limitation of the lithography process, it is not easy to reduce the diameter of the lower electrode contact layer 11 below the threshold value. Therefore, it is difficult to implement a memory device having a low operating current with the conventional technology.

SUMMARY OF THE INVENTION The present invention has been made in an effort to improve the above-described problems of the related art, and to provide a resistor memory device capable of reducing an operating current.

Another object of the present invention is to provide a method of operating the resistor memory device.

Another object of the present invention is to provide a method of manufacturing the resistor memory device.

In order to achieve the above technical problem, the present invention provides a storage node; And a switching device connected to the storage node, wherein the storage node comprises: conductive nanowires disposed parallel to the substrate on a substrate; A resistive material layer formed on a portion of the nanowire; And an electrode formed on the resistive material layer.

The switching element may be a diode provided on the electrode. In this case, a bit line connected to the diode and crossing the nanowire may be further provided.

The switching element may be a diode in contact with another portion of the nanowire. In this case, a bit line connected to the electrode and intersecting the nanowire may be further provided.

A plurality of resistive material layers may be provided on the nanowires, and the electrode may be provided on each of the resistive material layers.

A plurality of the nanowires may be arranged on the substrate.

The plurality of nanowires may be parallel to each other.

The nanowires may be any one of a semiconductor, a metal, and a metal oxide.

The resistance material layer may be a phase change layer or a resistance change layer having no phase change characteristic.

The resistive material layer may be provided to surround side surfaces of the nanowires on the substrate.

An insulating layer may be further provided on the substrate around the nanowires.

In order to achieve the above another technical problem, the present invention includes a storage node and a switching element connected to the storage node, the storage node, a conductive nanowire placed on the substrate in parallel with the substrate, a portion of the nanowire A method of operating a memory device having a resistive material layer formed on the resistive material layer and an electrode formed on the resistive material layer, the method comprising: maintaining the switching element in an on state; And applying a voltage between the nanowires and the electrode.

The voltage may be a write voltage for flowing a reset current between the nanowires and the electrode.

The voltage may be an erase voltage for flowing a set current between the nanowires and the electrode.

The voltage may be a read voltage applied to read data written to the storage node by measuring a resistance of the storage node.

In accordance with another aspect of the present invention, there is provided a method of manufacturing a memory device including a storage node and a switching element connected to the storage node, wherein the forming of the storage node is parallel to the substrate on a substrate. Preparing one conductive nanowire; Forming a resistive material layer on a portion of the nanowire; And forming an electrode on the resistive material layer.

The method may include forming a diode as the switching element on the electrode. In this case, the method may further include forming a bit line connected to the diode and crossing the nanowire.

And forming a diode as the switching element on another portion of the nanowire. In this case, the method may further include forming a bit line connected to the electrode and crossing the nanowire.

The nanowires may be formed of any one of a semiconductor, a metal, and a metal oxide.

The resistance material layer may be a phase change layer or a resistance change layer having no phase change characteristic.

The resistive material layer may be formed to surround a side of the nanowire on the substrate.

The method may further include forming an insulating layer on the substrate around the nanowires between preparing the nanowires and forming the resistive material layer.

According to the present invention, since the contact area between the lower electrode and the resistive material layer can be reduced by using fine nanowires as the lower electrode, the operating current of the resistive memory device can be reduced.

Hereinafter, a memory device including a resistive material layer according to a preferred embodiment of the present invention, an operation thereof, and a manufacturing method thereof will be described in detail with reference to the accompanying drawings. In this process, the thicknesses of the layers or regions illustrated in the drawings are somewhat exaggerated for clarity. Like numbers refer to like elements throughout.

2 illustrates a memory device according to an embodiment of the present invention.

Referring to FIG. 2, conductive nanowires 210 are laid down on a substrate 200. The nanowires 210 may be formed of any one of a semiconductor, a metal, and a metal oxide. For example, the nanowires 210 may be carbon nanotubes (CNTs) or nanowires made of any one of Si, Ge, and Au. The diameter of the nanowires 210 may be about several tens of nm. The resistive material layer 220 is provided on a portion of the nanowire 210. The resistive material layer 220 may be a phase change layer such as a chalcogenide layer, but may be a resistance change layer having no phase change characteristic, for example, a transition metal oxide layer. The resistive material layer 220 may be formed to surround the side surface of the nanowire 210 on the substrate 200. The electrode 230 is provided on the resistive material layer 220. The nanowires 210, the resistive material layer 220, and the electrodes 230 constitute the storage node S1.

There is a switching device 300 connected to the storage node S1. The switching element 300 may be a diode provided on the electrode 230. The bit line 240 intersecting with the nanowires 210 may be provided on the switching element 300. Although the first conductive plug 235 may be provided between the bit line 240 and the switching element 300, the bit line 240 may be disposed on the switching element 300 without the first conductive plug 235. It may be formed directly.

The first contact layer 250a may be provided on the substrate 200 to contact another portion of the nanowire 210, for example, one end. The second contact layer 250b may be further provided on the first contact layer 250a, and the first and second contact layers 250a and 250b may be connected by the second conductive plug 245. The first contact layer 250a is an optional element. That is, the second conductive plug 245 may directly contact the nanowires 210 without the first contact layer 250a. The second contact layer 250b may be formed at the same height as the bit line 240. The second contact layer 250b may be in the form of a pad or a line.

The formation position of the switching element 300 may vary. For example, as shown in FIG. 3, the switching device 300 may be positioned between the first contact layer 250a and the nanowire 210. In this case, the first conductive plug 235 is formed on the electrode 230. As in FIG. 2, the first contact layer 250a is also an optional element in FIG. 3. Although not shown, another contact layer may be further provided between the switching device 300 and the nanowires 210 in FIG. 3.

2 and 3, the shape of the resistive material layer 220 may vary. For example, as shown in FIGS. 4 and 5, the hexahedral resistive material layer 220a may be in contact with a portion of the upper surface of the nanowire 210. In this case, an insulating layer (not shown) may be provided on the substrate 200 around the nanowires 210. That is, except for a portion of the upper surface of the nanowire 210 may be buried in the insulating layer, the resistive material layer 220a may be formed on the nanowire 210 and the insulating layer around it.

In the memory device of FIGS. 2 to 5, a plurality of resistive material layers 220 and 220a may be provided on the nanowires 210, and the plurality of nanowires 210 may be arranged in parallel on the substrate 200. Can be. For example, the memory device according to another embodiment of the present invention may have a structure as shown in FIG. 6 or 7. Referring to FIG. 6, a plurality of nanowires 210 are uniformly spaced and arranged in parallel on the substrate 200 and intersect the nanowires 210 at a predetermined interval above the nanowires 210. There are a number of bit lines 240. The resistive material layer 220, the electrode 230, and the switching device 300 are sequentially stacked at the intersection point of the nanowire 210 and the bit line 240. In the structure of FIG. 7, the switching element 300 is positioned between the first contact layer 250a and the nanowire 210, and the bit line 240 is provided on the electrode 230.

A brief description of the operating method of the memory device according to the embodiments of the present invention as shown in FIG.

When a predetermined voltage is applied between the predetermined bit line 240 and the predetermined second contact layer 250b, the switching element 300 therebetween can be turned on, and the turn-on The phases of the resistive material layers 220 and 220a connected to the turned-on switching element 300 may be changed from amorphous to crystalline or vice versa. This is a data write or erase operation. In more detail, when a predetermined current flows between the nanowires 210 and the electrodes 230, Joules are caused by the current flowing through the contact surfaces of the nanowires 210 and the resistive material layers 220 and 220a. Heat may be generated and the phase of portions of the resistive material layers 220 and 220a contacting the nanowires 210 may be changed by the heat. When the predetermined voltage is a write voltage for flowing a reset current between the nanowires 210 and the electrodes 230, the phases of the resistive material layers 220 and 220a are crystalline to amorphous. Is changed. When the predetermined voltage is an erase voltage for flowing a set current between the nanowire 210 and the electrode 230, the phases of the resistive material layers 220 and 220a are changed from amorphous to crystalline. Is changed. On the other hand, by applying a read voltage between the predetermined bit line 240 and the predetermined second contact layer 250b, and measuring the electrical resistance of the storage node existing between them, to determine the data written to the storage node can do. The operation method is an operation method when the resistance material layers 220 and 220a are phase change layers, but may be similarly applied to the case where the resistance material layers 220 and 220a are resistance change layers without phase change characteristics.

8 shows a portion of a PPAM sample prepared according to an embodiment of the present invention. The structure of FIG. 8 is similar to that of FIG. Referring to FIG. 8, a resistive material layer 220 is provided on a portion of the fine nanowire 210, and another portion of the nanowire 210 is in contact with the first contact layer 250a.

In the memory devices according to example embodiments, the diameter of the nanowire 210 is only several nm to several tens of nm, so that the contact area between the nanowire 210 and the resistive material layers 220 and 220a is very small. Therefore, using the present invention, it is possible to easily reduce the operating current of the memory element using the resistor.

9 shows the voltage-resistance characteristics of a PRAM sample prepared according to an embodiment of the present invention. In FIG. 9, the voltage V is a pulse voltage applied between the bit line 240 and the second contact layer 250b, and the resistance Ω is a resistance between the bit line 240 and the second contact layer 250b. to be.

Referring to FIG. 9, at a predetermined voltage V, the resistance Ω is rapidly changed. This means that the phases of the resistive material layers 220 and 220a are changed at the predetermined voltage V, so that the resistance thereof is changed. In addition, it can be seen from FIG. 9 that the operating current of the PPAM sample according to the embodiment of the present invention is about 80 mA, compared with the operating current (0.5 to 1 mA) of a conventional PRAM having a storage node as shown in FIG. Significantly smaller.

10A to 10E illustrate a method of manufacturing a memory device according to an embodiment of the present invention.

Referring to FIG. 10A, a conductive nanowire 210 parallel to the substrate 200 is prepared on the substrate 200. The nanowires 210 may be formed by an epitaxial growth method or an etching method on another substrate and then transferred to the substrate 200 for manufacturing a memory device. The nanowires 210 may be formed of any one of a semiconductor, a metal, and a metal oxide, for example, one of carbon nanotubes (CNT), Si, Ge, and Au, and may have a diameter of about several tens of nm.

Referring to FIG. 10B, a laminate structure covering a portion of the nanowires 210 is formed on the substrate 200. The stacked structure may include a resistive material layer 220, an electrode 230, and a switching device 300 that are sequentially stacked. The switching element 300 may be a diode. The nanowires 210, the resistive material layer 220, and the electrodes 230 constitute the storage node S1. Next, a first contact layer 250a is formed on another portion of the nanowire 210, for example, one end of the nanowire 210 and the substrate 200 around the nanowire 210. Formation of the first contact layer 250a is optional.

Referring to FIG. 10C, an insulating layer 400 covering a nanowire 210, a resistive material layer 220, an electrode 230, a switching device 300, and a first contact layer 250a on a substrate 200 is provided. To form.

Referring to FIG. 10D, the insulating layer 400 is etched to form first and second contact holes H1 and H2. The first contact hole H1 exposes the switching element 300, and the second contact hole H2 exposes the first contact layer 250. When the first contact layer 250a is not formed in the step of FIG. 10B, the second contact hole H2 may expose the substrate 200 around the one end of the nanowire 210 and the surroundings thereof.

Referring to FIG. 10E, first and second conductive plugs 235 and 245 are formed in the first and second contact holes H1 and H2, respectively. Then, a bit line 240 in contact with the first conductive plug 235 and a second contact layer 250b in contact with the second conductive plug 245 are formed on the insulating layer 400.

11A to 11D illustrate a method of manufacturing a memory device according to another exemplary embodiment of the present invention.

Referring to FIG. 11A, after preparing the nanowires 210 on the substrate 200, another stacked structure covering a portion of the nanowires 210 is formed. The other stacked structure may include a resistive material layer 220 and an electrode 230 that are sequentially stacked. Thereafter, the switching element 300 and the first contact layer 250a are formed on another portion of the nanowire 210, for example, one end of the nanowire 210 and the substrate 200 around the nanowire 210. The switching element 300 may be a diode. Formation of the first contact layer 250a is optional, and may further form another contact layer (not shown) between the nanowire 210 and the switching device 300.

Referring to FIG. 11B, an insulating layer 400 covering the nanowires 210, the resistive material layer 220, the electrode 230, the switching device 300, and the first contact layer 250a is disposed on the substrate 200. To form.

Referring to FIG. 11C, the insulating layer 400 is etched to form first and second contact holes H1 ′ and H2 ′. The first contact hole H1 ′ exposes the electrode 230, and the second contact hole H2 ′ exposes the first contact layer 250a.

Referring to FIG. 11D, first and second conductive plugs 235 and 245 are formed in the first and second contact holes H1 ′ and H2 ′, respectively. Then, a bit line 240 in contact with the first conductive plug 235 and a second contact layer 250b in contact with the second conductive plug 245 are formed on the insulating layer 400.

Embodiments of the present invention described with reference to FIGS. 10A through 10E and 11A through 11D may be variously changed. For example, after preparing the nanowires 210 on the substrate 200 in FIGS. 10A and 11A, an insulating layer is formed on the substrate 200 around the nanowires 210, and then a subsequent process is performed. Memory devices such as 4 and 5 can be manufactured. Also, memory devices as shown in FIGS. 6 and 7 may be manufactured using the embodiments of the present invention described with reference to FIGS. 10A through 10E and 11A through 11D.

While many details are set forth in the foregoing description, they should be construed as illustrative of preferred embodiments, rather than to limit the scope of the invention. For example, those skilled in the art will appreciate that the structure and components of the memory device of FIGS. 2 to 7 may be changed and varied. Therefore, the scope of the present invention should not be defined by the described embodiments, but should be determined by the technical spirit described in the claims.

1 is a cross-sectional view illustrating a storage node of a phase change memory device (PRAM) according to the prior art.

2 to 7 are perspective views illustrating a memory device according to example embodiments.

8 is a scanning electron microscope (SEM) top view showing a portion of the PPAM prepared according to an embodiment of the present invention.

9 is a graph showing voltage-resistance characteristics of a PRAM manufactured according to an embodiment of the present invention.

10A to 10E are perspective views illustrating a method of manufacturing a memory device according to an embodiment of the present invention.

11A to 11D are perspective views illustrating a method of manufacturing a memory device according to another exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

200: substrate 210: nanowire

220, 220a: resistive material layer 230: electrode

235, 245 conductive plug 240 bit line

250a: first contact layer 250b: second contact layer

300: switching element H1, H1 ': first contact hole

H2, H2 ': second contact hole S1: storage node

Claims (25)

Storage node; And Including; switching element connected to the storage node; The storage node, Conductive nanowires disposed parallel to the substrate on the substrate; A resistive material layer formed on a portion of the nanowire; And And an electrode formed on the resistive material layer. The memory device of claim 1, wherein the switching device is a diode provided on the electrode. The memory device of claim 1, wherein the switching device is a diode in contact with another portion of the nanowire. The memory device of claim 2, further comprising a bit line connected to the diode and crossing the nanowire. The memory device of claim 3, further comprising a bit line connected to the electrode and crossing the nanowire. The memory device according to any one of claims 1 to 5, wherein a plurality of the resistive material layers are provided on the nanowires, and the electrodes are provided on the respective resistive material layers. The memory device of claim 6, wherein a plurality of the nanowires is arranged on the substrate. 8. The memory device of claim 7, wherein the plurality of nanowires are parallel to each other. The memory device of claim 1, wherein the nanowire is any one of a semiconductor, a metal, and a metal oxide. The memory device of claim 1, wherein the resistive material layer is a phase change layer or a resistance change layer having no phase change characteristic. The memory device of claim 1, wherein the resistive material layer is provided on the substrate to surround side surfaces of the nanowires. The memory device of claim 1, further comprising an insulating layer on the substrate around the nanowires. In the method of operating the memory device according to claim 1, Maintaining the switching element in an ON state; And And applying a voltage between the nanowire and the electrode. 15. The method of claim 13, wherein the voltage is a write voltage for flowing a reset current between the nanowire and the electrode. The method of claim 13, wherein the voltage is an erase voltage for flowing a set current between the nanowire and the electrode. The method of claim 13, wherein the voltage is a read voltage applied to read the data written to the storage node by measuring the resistance of the storage node. In the manufacturing method of a memory device comprising a storage node and a switching element connected to the storage node, Forming the storage node, Preparing a conductive nanowire parallel to the substrate on a substrate; Forming a resistive material layer on a portion of the nanowire; And Forming an electrode on the resistive material layer. 18. The method of claim 17, further comprising forming a diode as the switching element on the electrode. 18. The method of claim 17, further comprising forming a diode as the switching element on another portion of the nanowire. 19. The method of claim 18, further comprising forming a bit line connected to the diode and intersecting the nanowire. 20. The method of claim 19, further comprising forming a bit line connected to the electrode and crossing the nanowire. 18. The method of claim 17, wherein the nanowires are formed of any one of a semiconductor, a metal, and a metal oxide. 18. The memory device of claim 17, wherein the resistive material layer is a phase change layer or a resistance change layer having no phase change characteristic. The method of claim 17, wherein the resistive material layer is formed on the substrate to surround side surfaces of the nanowires. 18. The memory device of claim 17, further comprising forming an insulating layer on the substrate around the nanowires between preparing the nanowires and forming the resistive material layer. Method of preparation.

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