KR20090001080A - Method of forming fine pattern of semiconductor device - Google Patents

Abstract

A fine pattern forming method of the semiconductor device is provided to reduce the line width of pattern and improve the resolution by forming the spacer on the side wall of pattern. A first amorphous carbon film(112) and an oxide film(114) are successively formed on the semiconductor substrate(110). A second amorphous carbon film pattern is formed on the oxide film. A primary nitride film spacer(130) is formed on the side wall of the second amorphous carbon film pattern. The oxide film pattern is formed by using the primary nitride film spacer as the etching mask. The trimming etching process is performed to the first amorphous carbon film. The first amorphous carbon film pattern(112a) is formed by the trimming etching process.

Description

Method of forming a fine pattern of a semiconductor device {Method of Forming Fine Pattern of Semiconductor Device}

1A to 1G are cross-sectional views showing a fine pattern forming method of a semiconductor device according to the prior art.

2A to 2I are cross-sectional views showing a method for forming a fine pattern of a semiconductor device according to the present invention.

<Description of Symbols for Major Parts of Drawings>

10,110 semiconductor substrate 12,112 amorphous carbon film

12a, 112a, 112b, 112c: amorphous carbon film pattern 114: oxide film

114a: oxide film pattern 16: silicon oxynitride film

16a: silicon oxynitride film pattern 18,118 polysilicon film

18a, 118a: polysilicon film pattern 120: nitride film

120a: nitride film pattern 24, 28, 124: antireflection film

24a, 28a: antireflection film pattern 26, 126, 30a: photoresist pattern

30: photoresist film 130, 140: nitride film spacer

The present invention relates to a method for forming a fine pattern of a semiconductor device, and more particularly, by making the size of the pattern small by a trimming etching process, and then forming a spacer on the sidewall of the pattern, the line width of the pattern can be reduced indefinitely. It relates to a method for forming a fine pattern of a semiconductor device.

As the size of semiconductor devices becomes smaller and smaller, controlling the critical dimension of the pattern line width becomes an important problem when applying the photolithography technique. In general, the speed of a semiconductor device is faster as the critical dimension of the pattern line width, that is, the size of the pattern line is smaller, and the performance of the device is also improved.

However, due to the limitation of photolithography technology using ArF exposure equipment having a numerical aperture of 1.2 or less, it is difficult to form a line and space pattern of 40 nm or less in a single exposure process.

Therefore, before the next generation of EUV exposure technology, a first pattern having a line width twice as large as the pattern line width is formed as part of the resolution enhancement and process margin expansion of the photolithography technology, and then the same line width period is formed between the first patterns. A double exposure process technology for forming two patterns has been developed and currently applied to a semiconductor device mass production process.

On the other hand, since the double exposure process uses two different masks for patterning, the manufacturing cost and the time-to-efficiency are lower than the patterning technique using one mask, and thus the production rate is lowered. In addition, when forming a pattern having a pitch smaller than the resolution limit of the exposure equipment in the cell region, there are various disadvantages such as overlapping the processed images to obtain a pattern of a desired shape, and overlay misalignment occurs during alignment. .

In order to alleviate this drawback, double exposure and double etching techniques have been developed and are currently being applied to semiconductor device mass production processes.

1A to 1G are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the prior art, and illustrate a method of forming a fine pattern by a double exposure and a double etching technique.

Referring to FIG. 1A, an amorphous carbon film 12, a silicon oxynitride film 16, a polysilicon film 18, and a first antireflection film 24 are sequentially formed on a semiconductor substrate 10, and then a first reflection is formed. The first photoresist pattern 26 is formed on the protection film 24.

Referring to FIG. 1B, the first anti-reflection film 24 and the polysilicon film 18 are patterned using the first photoresist pattern 26 as an etching mask to form the first anti-reflection film pattern 24a and polysilicon. The film pattern 18a is formed.

Referring to FIG. 1C, after removing the first antireflection film pattern 24a and the first photoresist pattern 26, a second antireflection film 28 is formed on the entire surface of the polysilicon film pattern 18a, and then 2 A photoresist film 30 is formed on the antireflection film 28.

Referring to FIG. 1D, the second photoresist pattern 30a is formed between the polysilicon film patterns 18a by selectively etching the photoresist film 30 by an exposure and development process using an exposure mask.

Referring to FIG. 1E, a stacking pattern of the second organic anti-reflection film pattern 28a and the second photoresist pattern 30a between the polysilicon film patterns 18a using the second photoresist pattern 30a as an etching mask. To form.

Referring to FIG. 1F, the lower silicon oxynitride layer 16 is formed by using the polysilicon layer pattern 18a and the stacked pattern of the second organic antireflective layer pattern 28a and the second photoresist pattern 30a as an etching mask. Patterning is performed to form the silicon oxynitride film pattern 16a.

Referring to FIG. 1G, a two-layer stacked pattern of a silicon oxynitride layer pattern 16a and a polysilicon layer pattern 18a, a silicon oxynitride layer pattern 16a, a second organic antireflection layer pattern 28a, and a second photoresist pattern An amorphous carbon film pattern 12a is formed by patterning the lower amorphous carbon film 12 using the three-layer stacked pattern of 30a as an etching mask.

In this case, the profile of the amorphous carbon film pattern 12a formed by using the two-layer stacked pattern of the silicon oxynitride film pattern 16a and the polysilicon film pattern 18a as an etching mask, and the silicon oxynitride film pattern 16a and the second layer The profile of the amorphous carbon film pattern 12a formed by using the three-layer stacked pattern of the organic antireflection film pattern 28a and the second photoresist pattern 30a as an etching mask may be different.

In addition, although the pitch of the pattern can be reduced by the above-described double exposure and double etching techniques, the line width of the pattern cannot be reduced, so there is a limit in improving the resolution.

The present invention is to solve the problems of the prior art, in forming a fine pattern by making the size of the pattern small by the trimming etching process, and then forming a spacer on the pattern sidewall, significantly reducing the line width of the pattern It is an object of the present invention to provide a method for forming a fine pattern of a semiconductor device.

In order to achieve the above object, the present invention provides a method for forming a fine pattern of a semiconductor device comprising the following steps:

Sequentially forming a first amorphous carbon film and an oxide film on a semiconductor substrate on which an etched layer is formed,

Forming a second amorphous carbon film pattern on the oxide film;

Forming a first nitride film spacer on sidewalls of the second amorphous carbon film pattern;

Removing the second amorphous carbon film pattern, and then patterning an oxide film using the first nitride spacer as an etch mask to form an oxide film pattern;

Forming a first amorphous carbon film pattern by performing a trimming etching process on the first amorphous carbon film using the stacked pattern of the oxide pattern and the first nitride spacer as an etching mask;

Forming a second nitride film spacer on sidewalls of the first amorphous carbon film pattern;

Removing the first amorphous carbon film pattern and then patterning an etched layer using the second nitride film spacer as an etch mask to form an etched layer pattern.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2A to 2I are cross-sectional views illustrating a method for forming a fine pattern of a semiconductor device according to the present invention.

Referring to FIG. 2A, an amorphous carbon film 112 having a thickness of 1000 to 2000 GPa, an oxide film 114 having a thickness of 100 to 500 GPa, a polysilicon film 118 having a thickness of 100 to 500 GPa, a thickness of 1000 to 2000 GPa is formed on the semiconductor substrate 110. Amorphous carbon film 112, 100-500 kW thick oxide film 114, 1000-2000 kW thick amorphous carbon film 112, 100-500 kW thick nitride film (or silicon oxynitride film) 120 and 200-500 kW thick reflection The prevention film 124 is formed sequentially.

Next, a photoresist (AIM5076 of JSR, Japan JSR) was applied on the antireflection film 124 to a thickness of 1000 GPa, and then baked to form a photoresist film. Exposing to form a photoresist pattern 126 having a size of 40 nm.

In this case, in forming the photoresist pattern 126, all lithography processes, such as an KrF lithography process and an EUV lithography process, may be used in addition to the ArF lithography process.

Referring to FIG. 2B, the lower anti-reflection film 124, the nitride film 120, and the amorphous carbon film 112 are patterned by using the photoresist pattern 126 as an etching mask (not shown). The nitride film pattern 120a and the amorphous carbon film pattern 112a are formed.

Patterning of the anti-reflection film 124 and the nitride film 120 is CF ₄ , CHF ₃ , SF ₆ , Cl ₂ , N ₂ , at a pressure of 1 ~ 200mT, power 100 ~ 1000W in the etching chamber of Lam, USA or Hitachi, Japan It is carried out under plasma conditions using a gas selected from the group consisting of O ₂ , Ar and combinations thereof.

In addition, the patterning of the amorphous carbon film 112 is a gas selected from the group consisting of N ₂ , O ₂ , Ar, HBr, H ₂ and combinations thereof at a pressure of 1 to 200 mT and a power of 100 to 2000 W in the same etching chamber as described above. It is performed under the used plasma conditions.

Referring to FIG. 2C, after the anti-reflection film pattern and the nitride film pattern 120a are removed, a nitride film is deposited on the entire surface of the amorphous carbon film pattern 112a and then etched to the entire surface to form the nitride film spacer 130 on the sidewall of the amorphous carbon film pattern 112a. ).

The front etching process is performed under a plasma condition using a CF ₄ / CHF ₃ / O ₂ / Ar mixed gas at a pressure of 1 to 200 mT and a power of 100 to 1000 W in an etching chamber of US AMAT, US LAM, or Japan TEL.

Referring to FIG. 2D, the amorphous carbon film pattern 112a between the nitride film spacers 130 is etched and removed.

The etching process of the amorphous carbon film pattern 112a may be performed using a general stripper, N ₂ , O ₂ , Ar, HBr at a pressure of 1 to 200 mT and a power of 100 to 2000 W in an etching chamber of Lam, USA or Hitachi, Japan. , H ₂ and combinations thereof, are carried out under plasma conditions using a gas selected from the group consisting of.

Referring to FIG. 2E, the oxide layer 114 is patterned using the nitride spacer 130 as an etching mask to form an oxide layer pattern 114a.

Next, using the stacked pattern of the oxide film pattern 114a and the nitride spacer 130 as an etching mask to form a pattern of the lower amorphous carbon film 112, a trimming etching process for etching the sidewalls is performed to 20nm size An amorphous carbon film pattern 112b is formed.

In general, the trimming etching process is a technique applied to easily and uniformly adjust the pattern line width in a logic process. An over-etching of the lower material is over-etched with an etch barrier of the upper material having a difference in selection ratio, thereby adjusting the line width of the lower material. It is known that it can. In the conventional DRAM process, there are few examples of applying the trimming etching process.

The trimming etching process according to the embodiment of the present invention allows the sidewalls of the amorphous carbon film 112 pattern to be uniformly etched without loss of the oxide film pattern 114a and the nitride film spacer 130. The etching selectivity of the amorphous carbon film 112 is performed under a large difference. That is, in the trimming etching process, since the amorphous carbon film 112 has a higher etching selectivity with respect to the etching gas than the oxide film pattern 114a and the nitride spacer 130, the sidewalls are first etched and removed during the trimming etching process.

Preferably, the trimming etching process is selected from the group consisting of N ₂ , O ₂ , Ar, HBr, H ₂ and combinations thereof at a pressure of 1 to 200 mT and a power of 100 to 2000 W in an etching chamber of US Lam or Hitachi, Japan. It is carried out under plasma conditions using the selected gas.

In the trimming etching process, the line width of the amorphous carbon film pattern 112b is reduced to about 10 to 90%, and preferably about 40 to 60% of the line width of the red pattern of the oxide film 114a and the nitride spacer 130. Run until you have a size.

Referring to FIG. 2F, the oxide film pattern 114a and the nitride film spacer 130 on the amorphous carbon film pattern 112b are etched and removed.

The etching process of the oxide layer pattern 114a and the nitride layer spacer 130 is C ₄ F ₆ , C having good selectivity with the polysilicon layer 118 at a pressure of 1 to 200 mT and a power of 100 to 2000 W in an etching chamber of Lam, USA. ₄ F ₈ , O ₂ , Ar, and combinations thereof.

Next, the nitride film is deposited on the entire surface of the amorphous carbon film pattern 112b and then etched to form the nitride film spacer 140 on the sidewall of the amorphous carbon film pattern 112b.

The front etching process is a gas selected from the group consisting of a combination of CF ₄ , CHF ₃ , O ₂ , Ar at a pressure of 1 ~ 200mT, power 100 ~ 1000W in an etching chamber of the US AMAT, US LAM or Japan TEL. It is performed under the used plasma conditions.

Referring to FIG. 2G, the amorphous carbon film pattern 112b between the nitride film spacers 140 is etched and removed.

The etching process of the amorphous carbon film pattern 112b may be performed using a general stripper, N ₂ , O ₂ , Ar, HBr at a pressure of 1 to 200 mT and a power of 100 to 2000 W in an etching chamber of Lam, USA or Hitachi, Japan. , H ₂ and combinations thereof, are carried out under plasma conditions using a gas selected from the group consisting of.

Referring to FIG. 2H, the polysilicon layer 118 is patterned using the nitride spacer 140 as an etch mask to form a polysilicon layer pattern 118a.

The panning of the polysilicon film 118 is made of HBr, Ar, C ₂ F ₆ and combinations thereof at a pressure of 1 to 200 mT and a power of 100 to 1000 W in an etching chamber of US AMAT, US LAM, or Japan TEL. It is performed under plasma conditions using a gas selected from the group.

Next, the nitride layer spacer 140 on the polysilicon layer pattern 118a is etched and removed.

The etching process of the nitride film spacer 140 is CF ₆ , CHF ₃ , O ₂ , Ar, and combinations thereof at a pressure of 1 to 200 mT and a power of 100 to 1000 W in an etching chamber of US AMAT, US Lam, or Japan TEL. It is carried out under plasma conditions using a gas selected from the group consisting of.

Referring to FIG. 2I, an oxide layer pattern 114a is formed by patterning the lower oxide layer 114 using the polysilicon layer pattern 118a as an etching mask.

The patterning of the oxide film 114 is a gas selected from the group consisting of C ₄ F ₆ , C ₄ F ₈ , O ₂ , Ar, and combinations thereof at a pressure of 1 to 200 mT and a power of 100 to 2000 W in an etching chamber of the American LAM Corporation. It is performed under the used plasma conditions.

Next, the amorphous carbon film 112 is patterned using the oxide film pattern 114a as an etching mask to form the amorphous carbon film pattern 112c.

The amorphous carbon film 112 is patterned from a group consisting of N ₂ , O ₂ , Ar, HBr, H _2, and combinations thereof at a pressure of 1 to 200 mT and a power of 100 to 2000 W in an etching chamber of Lam, USA or Hitachi, Japan. It is carried out under plasma conditions using the selected gas.

On the other hand, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be possible to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such modifications and changes are as follows It should be regarded as belonging to the claims.

As described above, according to the present invention, since the size of the amorphous carbon film pattern is made small by the trimming etching process in forming the fine pattern, and then spacers are formed on the sidewalls of the pattern, the pattern line width can be greatly reduced. Can be greatly improved. In addition, in the present invention, the line width of the amorphous carbon film pattern can be reduced indefinitely unless the amorphous carbon film pattern is collapsed by the trimming etching process. Therefore, there is no limit to the resolution improvement.

Claims (8)

Sequentially forming a first amorphous carbon film and an oxide film on a semiconductor substrate on which an etched layer is formed, Forming a second amorphous carbon film pattern on the oxide film; Forming a first nitride film spacer on sidewalls of the second amorphous carbon film pattern; Removing the second amorphous carbon film pattern, and then patterning an oxide film using the first nitride spacer as an etch mask to form an oxide film pattern; Forming a first amorphous carbon film pattern by performing a trimming etching process on the first amorphous carbon film using the stacked pattern of the oxide pattern and the first nitride spacer as an etching mask; Forming a second nitride film spacer on sidewalls of the first amorphous carbon film pattern; Removing the first amorphous carbon film pattern, and then patterning an etched layer using the second nitride film spacer as an etch mask to form an etched layer pattern. The method of claim 1, The forming of the first nitride film spacer may include depositing a nitride film on the entire surface of the second amorphous carbon film pattern, and then applying CF ₄ , CHF ₃ , O ₂ , Ar, and the like to the pressure chamber at a pressure of 1 to 200 mT and a power of 100 to 1000 W. Method for forming a fine pattern of a semiconductor device comprising the step of etching the entire surface under a plasma condition using a gas selected from the group consisting of these. The method of claim 1, The removing of the second amorphous carbon film pattern may be performed using a stripper, or in an etching chamber at a pressure of 1 to 200 mT and a power of 100 to 2000 W, such as N ₂ , O ₂ , Ar, HBr, H _2, and the like. And etching under a plasma condition using a gas selected from the group consisting of combinations. The method of claim 1, The trimming etching process may be performed under a plasma condition using a gas selected from the group consisting of N ₂ , O ₂ , Ar, HBr, H _2, and a combination thereof at a pressure of 1 to 200 mT and a power of 100 to 2000 W in an etching chamber. A method of forming a fine pattern of a semiconductor device. The method of claim 1, The first amorphous carbon film pattern formed after the trimming etching process has a line width size reduced by 10 to 90% with respect to the line widths of the oxide film pattern and the stacked pattern of the first nitride film spacer. . The method of claim 1, The first amorphous carbon film pattern formed after the trimming etching process has a line width size reduced by 40 to 60% with respect to the line width of the oxide film pattern and the stacked pattern of the first nitride film spacer. . The method of claim 1, The forming of the second nitride film spacer may include depositing a nitride film on the entire surface of the first amorphous carbon film pattern, and then applying CF ₄ , CHF ₃ , O ₂ , Ar, and the like to the pressure chamber at a pressure of 1 to 200 mT and a power of 100 to 1000 W. Method for forming a fine pattern of a semiconductor device comprising the step of etching the entire surface under a plasma condition using a gas selected from the group consisting of these. The method of claim 1, The removing of the first amorphous carbon film pattern may include a stripper or N ₂ , O ₂ , Ar, HBr, H _2, or a combination thereof at a pressure of 1 to 200 mT and a power of 100 to 2000 W in an etching chamber. A method of forming a fine pattern of a semiconductor device, comprising etching under a plasma condition using a gas selected from the group.

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