KR20090000868A - Optical proximity effect correction method - Google Patents

Abstract

An optical proximity effect correction method is provided to perform manual OPC(Optical Proximity Correct) about a layout or OPC about a specific area in order to improve the accuracy about the layout in which left and right space are asymmetric. A test mask in which a design layout of target patterns is arranged is manufactured(400). Patterns are transferred on a wafer by using the test mask(410). Wafer line width(CD) data of the patterns is measured(420). Wafer line width error data is extracted by using a tool which measures the wafer line width error in wafer line width data and total wafer domain so that a rule file database is formed(430). The layout are modified by selecting coordinates of the layout and wafer line width error value which would be revised from the rule file database(440).

Description

Method for Optical Proximity Correction

1A to 1C are diagrams for explaining the optical proximity effect correction method according to the prior art.

2 is a view illustrating a threshold error in the conventional optical proximity effect correction.

3A to 3C are diagrams for explaining a correction limit according to a peripheral pattern of a pattern.

4 is a flowchart illustrating the optical proximity effect correction method according to the present invention.

5 to 8 are diagrams for explaining the optical proximity effect correction according to an embodiment of the present invention.

The present invention relates to a semiconductor device, and more particularly, to a light proximity effect correction method.

As the degree of integration of semiconductor devices increases, the size of patterns decreases as design rules decrease. This makes it difficult to implement patterns as designed in the design layout. One of the reasons why it is difficult to implement a pattern according to a design layout is an optical proximity effect (OPE) generated in an exposure process. The optical proximity effect (OPE) is a pattern deformation caused by an imbalance in energy intensity due to light diffraction in the exposure process. In order to solve the problem that the pattern is deformed by the optical proximity effect and to increase the resolution, an optical proximity effect correction (OPC) method is used. The optical proximity effect correction (OPC) method is a method of correcting the layout of a target pattern to be transferred to a wafer in consideration of the optical proximity effect (OPE).

Currently, the optical proximity effect correction (OPC) method is used by applying a rule-based approach or a model-based approach. The rule base approach or model base approach is a method of calibrating the layout according to the surrounding environment of the part being calibrated. Therefore, the accuracy may vary depending on the surrounding environment and how to write related models and rules. In addition, the critical dimensions (CD) of all wafers cannot be satisfied for any layout having various shapes.

1A to 1C are diagrams for explaining the optical proximity effect correction method according to the prior art. 2 is a view illustrating a threshold dimension error in conventional optical proximity correction.

1A to 1C, a rule base approach or a model base approach for optical proximity correction is calibrated with respect to the OPC target pattern 100 in the form of a line and space. (FIG. 1A). However, using this result, when applied to an actual database in which various layouts (Random layouts 120, 130) exist around the OPC target pattern 100 of FIGS. 1B and 1C, accurate optical proximity correction (OPC) ) May not be implemented. That is, the result of the wafer exposed with the reticle made by applying the actual database having the layouts 120 and 130 having various shapes may be larger than the calibration data.

Referring to FIG. 2, it can be seen that the CD error 210 value of the pattern formed on the actual wafer is greater than the critical dimension error CD of calibration data for optical proximity correction (OPC). have. However, when the optical proximity effect correction (OPC) recipe is tuned to a specific portion to improve the CD error dimension, the error dimension of other portions except for the adjustment portion may be increased. Accordingly, there is a need for a method capable of correcting a layout whose shape is not constant.

The technical problem to be achieved by the present invention is to provide an optical proximity effect correction method that can improve OPC accuracy by performing local correction on the layout to be corrected in order to correct the wafer line width in the layout arranged in various forms throughout the chip. It is.

In order to achieve the above technical problem, the optical proximity effect correction method according to the present invention, manufacturing a test mask in which the design layout of the target pattern is disposed; Transferring patterns onto a wafer using the test mask; Measuring wafer linewidth (CD) data of the patterns; Extracting the wafer line width (CD) error data using a tool for measuring the wafer line width (CD) error in the entire wafer area and the wafer line width (CD) data to form a rule file database step; And modifying the layout by selecting a coordinate of a layout to be corrected and a wafer line width (CD) error value from the rule file database.

In the present invention, after measuring the wafer line width (CD) data, a manual OPC for extracting the coordinates and correction amount of the portion having a large line width error from the measured wafer line width (CD) data results to correct the layout of the same coordinates It is preferable to further include the step of proceeding.

The target pattern preferably includes a first pattern having a uniform left and right space spacing of the pattern and a second pattern having an asymmetric space of the left and right patterns.

In the correcting of the layout, the coordinate file and the wafer line width (CD) error value may be automatically corrected from the rule file database.

In order to achieve the above technical problem, in the optical proximity effect correction method according to the present invention, in a total frame in which a main chip on which a first layout and a second layout are arranged is arranged, a wafer CD error is compared to a design database in an entire wafer area. Extracting wafer linewidth (CD) error data of a layout disposed in the main chip by using a tool that can measure the data to form a rule file database; And extracting coordinates and CD error values of the first and second layouts from the rule file database and modifying the first and second layouts.

In this invention, the space | interval of the said 1st layout and the adjacent layout are arrange | positioned symmetrically.

The second layout is arranged asymmetrically with a space spacing from the adjacent layout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

3A to 3C are diagrams for explaining a correction limit according to a peripheral pattern of a pattern.

In order to improve the resolution of the pattern transferred onto the wafer, an optical proximity effect correction method (hereinafter, OPC) is used. The OPC method is a method of obtaining and correcting a difference between a threshold CD on a database and a pattern threshold CD formed on a wafer. This OPC method may vary in accuracy depending on the surrounding environment of the layout being calibrated.

Referring to FIGS. 3A through 3C, in the case of the first layout 300, the adjacent peripheral layout 310 and the space spacing a are uniform, and thus a pattern to be transferred onto the wafer is uniformly formed so that the wafer of FIG. The line width error is also uniform, which can be corrected accurately using the OPC method. However, when the left and right space spacings b are asymmetrical like the second layout 320 and the third layout 330, the wafer line width (CD) errors 330 and 340 of the pattern transferred on the wafer become large. It cannot be calibrated accurately using the OPC method. As the space spacing between left and right of the layout is different and the OPC is concentrated on these differences, it affects the layout having a duty composed of similar line and space, and causes a line width (CD) error. It will grow big. Referring to FIG. 3C, it can be seen that a line width (CD) error of the layout 300 having a symmetrical space spacing and the asymmetric layout 320, 330 occurs. Therefore, there is a need for a method of modifying a layout of a portion having a layout asymmetrical space spacing.

4 is a flowchart illustrating the optical proximity effect correction method according to the present invention. 5 to 8 are diagrams for explaining the optical proximity effect correction according to an embodiment of the present invention. In particular, FIG. 8 is an enlarged view of the region 'X' of FIG. 7.

4 and 5, a layout of a target pattern to be transferred onto a wafer is designed to form a test mask in which the layout of the target pattern is formed as a test pattern (step 400). The target pattern 540 may include a first pattern 500 having a uniform left and right space spacing (c) of the adjacent pattern 510 and a pattern, and a left and right space spacing (d, e) of the adjacent pattern 530 and the pattern. Asymmetric second pattern 520 is included (see FIG. 5). A pattern is then formed on the actual wafer using the test mask (step 410). Next, the line width (CD) of each of the patterns formed on the wafer is measured to form wafer line width (CD) data.

Next, a manual OPC is performed on a portion of the wafer width CD data having a large line width CD error. In the manual OPC, only the target layout is corrected by determining the coordinates and the amount to be corrected for the portion where the line width (CD) error is large in the measured wafer width (CD).

This method provides accurate line width where DRAM, cell boundary, cell boundary, sense amplifier or sub wordline driver are arrayed in DRAM devices. (CD) This is the method used for correction. In other words, if the layout is repeated, the parts using the same layout in the same product family may be modified using the manual OPC. In this case, the manual OPC may be modified by the designer using a layout editor.

However, subholes, main wordline drivers (MWDs), decoders, and peripherals use a variety of layouts and vary from product to product, making them difficult to modify using these manual OPCs. This is because it is difficult to specify the exact CD error for all the layouts.

Accordingly, a rule file database is formed using a tool capable of measuring wafer CD errors relative to the design database for the entire wafer area (step 430). Using this tool, it is possible to extract a wide range of wafer line widths (CDs) in areas such as peripheral circuit areas having various layouts.

4 and 6, the width 810 of the layout 600 to be corrected is extracted by extracting and using a coordinate and a CD error value of asymmetric pattern of left and right spaces from a rule file database formed using a tool. (Step 440). The layout correction is performed by local correction for selectively correcting a pattern in which left and right spaces are asymmetric.

In this case, the layout modification method cannot be modified by the designer using the layout editor like the manual OPC. This is because the peripheral circuit region has a random layout and a large number of layouts having different patterns. Therefore, the layout is modified with the rule file database. In other words, coordinate and line width error data are fetched from the rule file database, and the target layout to be modified is automatically modified using this. The coordinate and line width error data uses data measured using a tool for measuring wafer CD errors over the entire wafer area compared to the design target database.

Referring to FIGS. 7 to 8, which illustrate specific embodiments of the layout modification method, the total frame (or reticle, X) may have a layout corresponding to the main chip (Y) and the test pattern 830 of the device. It is included. A first layout 800 and a second layout 810 are present in each main chip Y, which have the same space as the neighboring patterns 820. The area A, the area B, the area C, and the area D are the same design database.

In the layout of the main chip X arranged as described above, first, the first layout 800 and the second layout 810 may be modified. Specifically, a rule file database of layouts arranged in the main chip X is formed by using a tool capable of measuring wafer CD errors with respect to the entire wafer area relative to the design database. With this tool, it is possible to extract a wide range of wafer line widths (CDs) of various layouts, for example layouts where the space between patterns is asymmetric. Next, local correction is performed to extract and correct the coordinates and CD error values of the first layout 800 and the second layout 810 from the rule file database.

Using the rule file database, not only can the first layout 800 and the second layout 810 be selectively modified, but also the layout in the area A to the area D in the total frame X can be modified. This layout modification can define the relevant coordinate and layout correction amount in the tool that measures wafer CD errors over the entire area relative to the design database that extracts the coordinates and CD errors on the reticle basis.

As described above, according to the optical proximity effect correction method according to the present invention, a manual OPC for a layout or an OPC for a specific region may be performed to correct wafer line widths in various layouts. This can improve accuracy for layouts in which the left and right spaces are asymmetric. In addition, even in layouts having the same left and right spaces, the accuracy can be improved by independently correcting the wafer widths. In addition, the accuracy of rule base correction, model base correction, and hybrid correction can be improved.

Claims (7)

Manufacturing a test mask having a design layout of target patterns disposed thereon; Transferring patterns onto a wafer using the test mask; Measuring wafer linewidth (CD) data of the patterns; Extracting the wafer line width (CD) error data using a tool for measuring the wafer line width (CD) error in the entire wafer area and the wafer line width (CD) data to form a rule file database step; And And correcting the layout by selecting a coordinate of a layout to be corrected and a wafer line width (CD) error value from the rule file database. The method of claim 1, After measuring the wafer line width (CD) data, performing a manual OPC to extract the coordinates and the correction amount of the portion having a large line width error from the measured wafer line width (CD) data results to correct the layout of the same coordinates Optical proximity effect correction method characterized in that it further comprises. The method of claim 1, The target pattern includes a first pattern having a uniform left and right space of the pattern and a second pattern having asymmetrical left and right spaces of the pattern. The method of claim 1, The correcting of the layout may include automatically correcting the coordinates by applying coordinate and wafer line width (CD) error values from the rule file database. In the total frame on which the main chip arranged the first layout and the second layout are arranged, Extracting wafer line width (CD) error data of a layout disposed in the main chip using a tool capable of measuring wafer CD errors relative to a whole design area of the wafer to form a rule file database; And And extracting coordinates and CD error values of the first and second layouts from the rule file database and modifying the first and second layouts. The method of claim 5, And the first layout has a symmetrical spacing between adjacent layouts. The method of claim 5, And the second layout has asymmetrical spacing between adjacent layouts.

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