KR20080110232A - Liquid crystal display and driving method of thereof - Google Patents

Abstract

A liquid crystal display and a driving method thereof are provided to prevent flicker which is generated when turning on a plurality of lamp in order. A scanning inverter operates the lamps according to the lamp scanning frequency. An image detection part(131) analyzes the input image and detects the static images and moving picture input or not. A frame frequency detecting part(132) detects the frame frequency(FF) of the input image. If the input image is a static image, and the frame frequency is below 60Hz, a first inverter controller(134) promptly turning on the lamps under the n times of the frame frequency.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY AND DRIVING METHOD OF THEREOF}

1 is a pixel equivalent circuit diagram of a general active matrix liquid crystal display device.

2 is a ramp waveform diagram for explaining a scanning backlight blinking scheme.

3 is a diagram for describing flicker generation in still images having a frame frequency of less than 60 Hz.

4 is a block diagram of a liquid crystal display according to an embodiment of the present invention.

5 is a detailed block diagram of the inverter controller of FIG.

6 is an exemplary view of the image detector of FIG. 5.

FIG. 7 is an exemplary diagram of a vertical synchronization signal adjusting unit of FIG. 5. FIG.

8 is an exemplary waveform diagram of lamps flashing by a doubled ramp scanning frequency.

9 is a flowchart illustrating a control process of the inverter controller shown in FIG. 5.

10 shows panel scanning and lamp scanning in still images with a frame frequency of less than 60 Hz.

<Description of Symbols for Main Parts of Drawings>

111: system 113: timing controller

114: gamma voltage supply circuit 115: data driving circuit

116: liquid crystal display panel 117: gate driving circuit

118: backlight 120: inverter

121: inverter controller 131: image detector

132: frame frequency detector 133: vertical sync signal detector

134: first inverter control unit 135: second inverter control unit

136: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device and a driving method thereof to reduce flicker generated when a plurality of lamps are sequentially flashed along the scanning direction of the liquid crystal display panel.

The liquid crystal display displays an image by controlling the light transmittance of the liquid crystal layer through an electric field applied to the liquid crystal layer corresponding to the video signal. The liquid crystal display is a flat panel display having advantages of small size, thinness, and low power consumption, and is used as a portable computer such as a notebook PC, office automation equipment, audio / video equipment, and the like. The liquid crystal display having such a configuration is rapidly replacing the cathode ray tube (CRT) due to its thin and low power consumption.

In particular, an active matrix type liquid crystal display device in which switching elements are formed in each liquid crystal cell is advantageous in implementing a moving picture because active switching of the switching elements is possible. As the switching element used in the active matrix liquid crystal display device, a thin film transistor (hereinafter referred to as TFT) is mainly used as shown in FIG. 1.

Referring to FIG. 1, an active matrix type liquid crystal display converts digital input data into an analog data voltage based on a gamma reference voltage and supplies it to the data line DL and simultaneously supplies scan pulses to the gate line GL. The liquid crystal cell Clc is charged. To this end, the gate electrode of the TFT is connected to the gate line GL, the source electrode is connected to the data line DL, and the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and the storage capacitor Cst. It is connected to one electrode. The common voltage Vcom is supplied to the common electrode of the liquid crystal cell Clc. The storage capacitor Cst charges a data voltage applied from the data line DL when the TFT is turned on, thereby maintaining a constant voltage of the liquid crystal cell Clc. When the scan pulse is applied to the gate line GL, the TFT is turned on to form a channel between the source electrode and the drain electrode so that the voltage on the data line DL is applied to the pixel electrode of the liquid crystal cell Clc. Supply. At this time, the liquid crystal molecules of the liquid crystal cell Clc modulate the incident light by changing the arrangement by the electric field between the pixel electrode and the common electrode.

Such a liquid crystal display device is a passive light emitting device, and adjusts the brightness of the screen by using backlight lamps spaced at regular intervals on the rear surface of the liquid crystal display panel.

On the other hand, in a liquid crystal display, due to the slow response characteristics of the liquid crystal and the retention characteristics of the liquid crystal, a motion blurring phenomenon in which a screen is blurred when a moving image is implemented, or a tailing phenomenon in which an outline of an image appears to be drawn may appear. Such degradation in image quality is difficult to be completely solved even when the response speed of the liquid crystal is faster than one frame period (16.7 ms).

In order to reduce the display quality deterioration due to the slow response and retention characteristics of the liquid crystal, a conventional scanning back light blinking system has been proposed.

In the scanning backlight blinking scheme, as shown in FIG. 2, a plurality of lamps Lamp1 to Lampk are fixed at a predetermined time interval during a frame period defined as a period between rising edges of the vertical synchronization signal Vsync. It is a way to flash sequentially. When the scanning backlight blinking method is applied, the liquid crystal display emits light during a part of one frame period and blocks light during the remaining period by a plurality of lamps Lamp1 to Lampk which are sequentially flashed along the scanning direction. As a result, it is driven in a quasi-impulse manner. Therefore, the display quality deterioration due to the inherent characteristics of the liquid crystal is prevented by the scanning backlight blinking method driven by the quasi-impulse method. In the scanning backlight blinking scheme, the frame frequency representing the number of frames for one second and the lamp scanning frequency representing the number of points / lights of the same lamp for one second are set to be the same.

By the way, the scanning backlight blinking method has a great effect on improving the display quality of a moving image as described above, but when applied to a still image, it may cause a flicker to deteriorate the display quality. In particular, the flicker in this still picture is not easily recognized when digital video data synchronized to a frame frequency of 60 Hz or higher is input, but is clearly recognized when digital video data synchronized to a frame frequency of 60 Hz or lower is input. This is because, in the scanning backlight blinking scheme, the frame frequency representing the number of frames for one second and the lamp scanning frequency representing the number of dots / turnout of the same lamp for one second are set to be the same. For example, when input digital video data is input in synchronization with a frame frequency of 75 Hz, as shown in FIG. 3 (a), the same lamp is turned on in the previous frame and then turned off, and then turned on again in the next frame. While the time required is 1/75 seconds, when the input digital video data is input in synchronization with a frame frequency of 50 Hz, as shown in FIG. 3B, it is 1/50 seconds, which is relatively longer than 1/75 seconds. According to the experiment, when the time from the lighting of the same lamp to the re-lighting exceeds 1/60 seconds, it can be seen that the blinking of the lamp is easily recognized as flicker by the human eye.

As a result, the conventional liquid crystal display device drives the lamps by the scanning backlight blinking method by setting the lamp scanning frequency equal to the frame frequency irrespective of the image attribute (video / still image) or frame frequency of the input digital video data. Similarly, there was a problem that caused flicker in still images with a frame frequency of less than 60 Hz.

Accordingly, an object of the present invention is to provide a liquid crystal display device and a driving method thereof to prevent flicker generated in a still image when a plurality of lamps are sequentially flashed along the scanning direction of the liquid crystal display panel.

In order to achieve the above object, according to an embodiment of the present invention, a liquid crystal display which sequentially flashes a plurality of lamps along a scanning direction of a liquid crystal display panel, includes: a scanning inverter for driving the lamps according to a lamp scanning frequency; An image detection unit for analyzing whether the still image and the moving image are input by analyzing the input image; A frame frequency detector for detecting a frame frequency of the input image; And a first inverter controller to increase the flashing speed of the lamps by multiplying n (n is an integer of 2 or more) times the lamp scanning frequency when the input image is a still image and the frame frequency is less than 60 Hz. do.

The liquid crystal display according to the embodiment of the present invention further comprises a vertical synchronous signal adjusting unit for adjusting the vertical synchronous signal supplied to the first inverter control unit in response to the control signal generated by the frame frequency detector; The first inverter controller controls the inverter such that the lamps flash n times (n is an integer of 2 or more) for one frame by using the adjusted vertical synchronization signal and the frame frequency below 60 Hz.

The vertical synchronization signal adjusting unit may include a transistor having a base terminal to which the control signal is input, a collector terminal connected to an input terminal for supplying the vertical synchronization signal, and an emitter terminal connected to ground; And an output node connected between the collector terminal and the input terminal of the transistor.

The control signal is maintained in a high logic state when the input image is a still image and the frame frequency is less than 60 Hz.

In the liquid crystal display according to the embodiment of the present invention, when the input image is a moving image or a still image having a frame frequency of 60 Hz or more, the second display panel controls the blinking of the lamps by maintaining the lamp scanning frequency equal to the frame frequency. It further comprises an inverter control unit.

In order to achieve the above object, a driving method of a liquid crystal display device which sequentially flashes a plurality of lamps along a scanning direction of a liquid crystal display panel according to an embodiment of the present invention detects whether a still image and a moving image are input by analyzing an input image. Making; Detecting a frame frequency of the input image; Multiplying the ramp scanning frequency by n (n is an integer of 2 or more) compared to the frame frequency when the input image is a still image and the frame frequency is less than 60 Hz; And driving the lamps according to the multiplied lamp scanning frequency to increase the flashing speed of the lamps.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 10.

4 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 4, in the liquid crystal display according to the exemplary embodiment, m × n liquid crystal cells Clc are arranged in a matrix type, and m data lines D1 to Dm and n gate lines ( G1 to Gn) intersect, and a TFT is formed at the intersection thereof, a DC-DC converter 119 for generating a driving voltage of the liquid crystal display panel 116, and an analog gamma compensation voltage is generated. The scan signal is applied to the gamma voltage supply circuit 114, the data driver circuit 115 to supply data to the data lines D1 to Dm of the liquid crystal display panel 116, and the gate lines G1 to Gn. The scanning direction of the liquid crystal display panel according to the attributes and the frame frequency of the input image and the timing controller 113 for controlling the gate driving circuit 117 to be supplied, the data driving circuit 115, and the gate driving circuit 117. Lamp scanning for flashing multiple lamps sequentially accordingly Light is irradiated to the liquid crystal display panel 116 by the inverter controller 121 for adjusting the wave number, the inverter 120 for driving the backlight 118 according to the adjusted lamp scanning frequency, and the drive of the inverter 120. The backlight 118 is provided.

In the liquid crystal display panel 116, a liquid crystal layer is formed between two glass substrates. The liquid crystal display panel 116 includes m × n liquid crystal cells Clc in which m data lines D1 to Dm and n gate lines G1 to Gn are arranged in a matrix by a cross structure. Include.

The lower glass substrate of the liquid crystal display panel 116 includes data lines D1 to Dm, gate lines G1 to Gn, TFTs, pixel electrodes of the liquid crystal cell Clc connected to the TFT, and a storage capacitor Cst. ) Is formed. A black matrix, a color filter, a common electrode, and the like are formed on the upper glass substrate of the liquid crystal display panel 116. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. The driving method is formed on the lower glass substrate together with the pixel electrode. On the upper glass substrate and the lower glass substrate of the liquid crystal display panel 116, a polarizing plate having an optical axis orthogonal to each other is attached, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on the inner surface which is in contact with the liquid crystal.

The system 111 converts analog image data supplied through an interface circuit (not shown) into digital video data Ri, Gi, and Bi corresponding to the resolution of the liquid crystal display panel 116. The system 111 extracts the composite video signal using the image data from the interface circuit, and uses the extracted composite video signal to match the horizontal sync signal Hsync and the vertical sync signal according to the resolution of the liquid crystal display panel 116. Vsync), a data enable signal DE, and a dot clock DCLK. The system 111 supplies a VCC voltage to the DC-DC converter 119 and supplies an inverter DC input voltage Vinv to the inverter 120.

The DC-DC converter 119 generates a VDD voltage, a VCOM voltage, a VGH voltage, and a VGL voltage using the VCC voltage input from the system 111. The VCOM voltage is a voltage supplied to the common electrode of the liquid crystal cell Clc. The VGH voltage is supplied to the gate driving circuit 117 as the high logic voltage of the scan pulse set above the threshold voltage of the TFT, and the VGL voltage is supplied to the gate driving circuit 117 as the low logic voltage of the scan pulse set to the OFF voltage of the TFT. Supplied.

The gamma voltage supply circuit 114 divides the VDD voltage from the DC-DC converter 119 and the VSS voltage set as the base voltage GND to analog to the respective gray levels of the digital video data Ri, Gi, and Bi. Generate gamma compensation voltages.

The data driving circuit 115 converts the digital video data Ri, Gi, Bi into an analog gamma compensation voltage from the gamma voltage supply circuit 114 in response to the data control signal DDC from the timing controller 113. The analog gamma compensation voltage is supplied to the data lines D1 to Dm of the liquid crystal display panel 116 as a data voltage.

The gate driving circuit 117 generates scan pulses of the gate voltages VGH and VGL in response to the gate control signal GDC from the timing controller 113, and sequentially scans the scan pulses to the gate lines G1 to Gn. Selects a horizontal line of the liquid crystal display panel 116 to which a data signal is supplied.

The timing controller 113 realigns the digital video data Ri, Gi, and Bi from the system 111 to the liquid crystal display panel 116 to supply the data driving circuit 115 to the timing driving signals Vsync and Hsync. And control signals DDC and GDC for controlling the gate driving circuit 117 and the data driving circuit 115 by using the DCLK and DE. The gate control signal DDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output signal (GOE), and a data control signal (DDCS). This includes a source start pulse (SSP), a source shift clock (SSC), a source output signal (SOE), and a polarity signal (POL).

The backlight 118 includes a plurality of direct type lamps disposed below the liquid crystal display panel 116 so as to overlap the liquid crystal display panel 116. The lamp used for the backlight 118 may be any one of a Cold Cathode Fluorescent (CCFL), an External Electrode Flouscent (EEFL), and a Heat Cathode Fluorescent (HCFL). have. The lamps are sequentially flashed according to the scanning direction of the liquid crystal display panel 110 by driving the inverter 120 to irradiate light to the liquid crystal display panel 116.

Inverter 120 converts a DC signal supplied from the outside through a switching unit (not shown) into an AC signal, and boosts the low-voltage AC signal to a high-voltage AC signal through a transformer (not shown). Supply. The inverter 120 receives the driving voltage Vinv from the system 111 and is driven under the control of the inverter controller 121 to make the flashing speed of the lamps faster than or equal to the frame frequency.

The inverter controller 121 refers to the digital video data Ri, Gi, Bi from the system 111 and detects whether the input image is a moving image or a still image. The inverter controller 121 counts the vertical synchronization signal Vsync from the system 111 to detect the frame frequency of the input image. When the input image is a still image and the frame frequency is less than 60 Hz, the inverter controller 121 doubles the lamp scanning frequency for sequentially blinking a plurality of lamps along the scanning direction of the liquid crystal display panel 116, thereby causing the lamps to blink. Is n times n (n is an integer greater than or equal to 2) times the frame frequency. When the input image is a video or the frame frequency of the still image is 60 Hz or more, the inverter controller 121 synchronizes the flashing speed of the lamps to the frame frequency by making the lamp scanning frequency the same as the frame frequency. The inverter controller 121 will be described in detail with reference to FIGS. 5 to 8.

FIG. 5 is a detailed block diagram of the inverter controller, FIG. 6 is a diagram illustrating an example of the image detector of FIG. 5, and FIG. 7 is a diagram illustrating an example of the vertical synchronization signal adjuster of FIG. 5. 8 is an exemplary waveform diagram of lamps flashing by a lamp scanning frequency multiplied by 2 times.

Referring to FIG. 5, the inverter controller 121 refers to the input digital video data Ri, Gi, and Bi, and an image detector 131 for detecting whether an input image is a moving image or a still image, and an input vertical synchronization signal. A frame frequency detector 132 that counts (Vsync) to detect the frame frequency (FF) of the input image, and a control signal DS generated by the frame frequency detector 132 when the input image is a still image and the frame frequency is less than 60 Hz. Frame sync using the vertical sync signal adjusting unit 133 for adjusting the still image vertical sync signal Vsync (SI), and the modulated vertical sync signal MVsync (SI) and the frame frequency FF. The first inverter controller 134 multiplying the lamp scanning frequency by FF) and the lamp scanning frequency is equal to the frame frequency when the input image is a video or the frame frequency of the still image is 60 Hz or more. And a multiplexer for selecting any one of output signals of the first and second inverter controllers 134 and 135 in response to the control signal DS from the second inverter controller 135 and the frame frequency detector 132. 136: hereinafter referred to as "MUX".

The image detector 131 detects whether the input image is a moving picture or a still image with reference to the input digital video data Ri, Gi, and Bi. To this end, the image detector 131 includes first and second frame memories 131a and 131b and a comparator 131c as shown in FIG. 6.

 The first and second frame memories 131a and 131b alternately store digital video data Ri, Gi, and Bi in frame units according to a pixel clock, and alternately output and compare the stored data Ri, Gi, and Bi. The previous frame data, that is, the n-1 th frame data Fn, is supplied to the unit 131c.

The comparing unit 131c compares the n th frame data Fn from the data input bus line 131d with the n-1 th frame data Fn-1 from the first and second frame memories 131a and 131b. Based on the comparison result, it is detected whether the input image is a moving image or a still image. The comparator 131c may use a comparison cumulative value between adjacent frame data continuously supplied to ensure accuracy of detection.

The image detector 131 classifies and outputs the input vertical sync frequency Vsync into the video vertical sync frequency Vsync (MI) and the still image vertical sync frequency Vsync (SI) according to the detected video and the still image.

The image detector 131 may use other known image detection methods in addition to those shown in FIG. 6.

When the input image is a still image and the frame frequency is less than 60 Hz, the frame frequency detector 132 counts the still image vertical synchronization signal Vsync (SI) to detect the frame frequency FF of the input image. To this end, the frame frequency detector 132 may include an edge detector and a counter. The edge detector detects rising edges of the still image vertical sync signal Vsync (SI) or detects falling edges and supplies them to the counter. The counter counts the detected rising edges or falling edges for one second to detect the frame frequency FF of the input still image.

The frame frequency detector 132 generates a control signal DS for adjusting the still image vertical sync signal Vsync (SI) and supplies the same to the vertical sync signal adjuster 133 along with the detected frame frequency FF. . The frame frequency detector 132 supplies a still image vertical sync signal Vsync (SI) from the image detector 131 to the vertical sync signal adjuster 133 and the second inverter controller 135.

The vertical synchronization signal adjusting unit 133 adjusts the still image vertical synchronization signal Vsync (SI) in response to the control signal DS generated by the frame frequency detector 132 when the input image is a still image and the frame frequency is less than 60 Hz. do. To this end, as shown in FIG. 7, the vertical synchronizing signal adjusting unit 133 has a base terminal B to which the control signal DS is input, and a collector terminal C connected to an input terminal for supplying a still image vertical synchronizing signal Vsync (SI). ) And a bipolar junction transistor (hereinafter referred to as "BJT") having an emitter terminal E connected to ground GND, and an output node connected between the collector terminal C and an input terminal ( n).

As shown in FIG. 8, the control signal DS is inverted from its low potential to a high potential in response to a still image of less than 60 Hz. The BJT maintains a turn-off state when the control signal DS is in the low potential state, and then turns on in synchronization with the time when the control signal DS is inverted to the high potential state. When the BJT is turned on, the still image vertical synchronization signal Vsync (SI) maintains a low potential logic state regardless of the input. As a result, the vertical synchronization signal adjusting unit 133 outputs the modulation vertical synchronization signal MVsync (SI) as shown in FIG. 8 through the output node n by turning on the BJT when a still image of less than 60 Hz is input. The output modulated vertical synchronization signal MVsync (SI) is supplied to the first inverter controller 134 together with the frame frequency FF from the frame frequency detector 132.

When the modulated vertical synchronization signal MVsync (SI) is input, the first inverter controller 134 multiplies the lamp scanning frequency for scanning lamps by twice the frame frequency FF. For example, the first inverter controller 134 increases the lamp scanning frequency to 80 Hz when the frame frequency FF is 40 Hz, and increases the lamp scanning frequency to 100 Hz when the frame frequency FF is 50 Hz. Since the lamp scanning frequency is very related to the lamp blinking speed, that is, the flicker generation speed, the first inverter controller 134 increases the lamp scanning frequency to increase the flicker generation rate that cannot be recognized by the human eye. According to the experiment, it can be seen that when the lamp scanning frequency is multiplied more than twice the frame frequency FF as described above, the flicker due to the lamp flickering is not recognized.

Accordingly, in response to a still image of less than 60 Hz, the inverter 120 is driven according to the multiplied ramp scanning frequency to increase the flashing frequency of the lamps in a frame by twice the frame frequency as shown in FIG. 8. In addition, it is possible to effectively remove the flicker that appeared in the still image of less than 60Hz conventionally.

On the other hand, when the input image is a moving picture or the frame frequency of the still image is 60Hz or more, the second inverter controller 135 is a video vertical synchronization signal (Vsync (MI)) from the image detector 131, the frame frequency detector ( The lamp scanning frequency is controlled to be the same as the frame frequency FF by using the still image vertical synchronization signal Vsync (SI) from the 132 and the frame frequency FF from the frame frequency detector 132 as shown in FIG. 2. do. For example, the second inverter controller 135 synchronizes the lamp scanning frequency to 40 Hz and 80 Hz when the frame frequency FF of the video is 40 Hz and 80 Hz, and the lamp scanning frequency when the frame frequency FF of the still image is 80 Hz. Is synchronized to 80Hz. As such, the reason for synchronizing the lamp scanning frequency to the frame frequency (FF) in a moving image or a still image of 60 Hz or more is that the flicker is not easily recognized in comparison with a still image even when the frame frequency (FF) is less than 60 Hz. This is because the flickering frequency of the lamp is faster in synchronization with the frame frequency when the frame frequency FF is 60 Hz or more, even if it is an image.

The MUX 136 selectively outputs output signals of the first and second inverter controllers 134 and 135 in response to the control signal DS from the frame frequency detector 132. In other words, when the control signal DS is input in a high potential state in response to a still image of less than 60 Hz, the MUX 136 connects an output terminal of the first inverter controller 134 to an input terminal of the inverter 120. When the control signal DS is input to the low potential state in response to a still image of 60 Hz or more, the output terminal of the second inverter controller 135 is connected to the input terminal of the inverter 120.

FIG. 9 is a flowchart illustrating a control process of the inverter controller shown in FIG. 5. FIG. 10 is a diagram illustrating panel scanning and lamp scanning in a still image having a frame frequency of less than 60 Hz.

Referring to FIG. 9, the inverter controller 121 determines whether the input image is a moving image or a still image using the input digital video data Ri, Gi, and Bi (S91).

As a result of the determination in step S91, if the attribute of the input image is a still image, the inverter controller 121 counts an input vertical synchronization signal Vsync to detect a frame frequency of the input image.

The inverter controller 121 determines whether the detected frame frequency is less than 60 Hz. (S93)

As a result of the determination in step S93, when the detected frame frequency of the still image is less than 60Hz, the inverter controller 121 adjusts the vertical synchronization signal of the still image differently from the input vertical synchronization signal (S94).

The inverter controller 121 multiplies the lamp scanning frequency by twice the frame frequency using the modulated vertical synchronization signal and the frame frequency.

On the other hand, if the attribute of the input image is a moving image or the frame frequency of the still image detected as a result of the determination in step S91 is 60Hz or more, the inverter controller 121 sets the lamp scanning frequency to be equal to the frame frequency. (S96)

The inverter controller 121 selectively supplies a lamp scanning frequency multiplied by 2 times the frame frequency, or a lamp scanning frequency synchronized with the frame frequency, to the inverter according to the property of the input image and the frame frequency to provide lamps of the backlight. In other words, when a still image having a frame frequency of less than 60 Hz is input, the inverter controller 121 sets a lamp scanning frequency of 2 to scan a lamp as compared to the frame frequency for scanning a panel as shown in FIG. 10. By doubling, the lamp's blink rate is doubled. In addition, the inverter controller 121 synchronizes the lamp scanning frequency with the frame frequency when the moving picture or the frame frequency is 60Hz or more, thereby matching the flashing speed of the lamps with the panel scanning speed.

As described above, the liquid crystal display device and the driving method thereof according to the present invention analyze the input image to detect whether the still image and the moving image are input, and also detect the frame frequency of the input image, so that the input image is the still image and the frame frequency. When is less than 60Hz by multiplying the lamp scanning frequency twice the frame frequency to increase the flashing speed of the lamps, it is possible to effectively remove the flicker that appeared in the still image below the conventional 60Hz.

Furthermore, the liquid crystal display and the driving method thereof according to the present invention drive the lamps by synchronizing the lamp scanning frequency with the frame frequency when the input image is a moving image or a still image having a frame frequency of less than 60 Hz. The motion blur phenomenon in the video can be effectively removed.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. For example, in the exemplary embodiment of the present invention, the lamp scanning frequency is multiplied by 2 times the frame frequency, but the technical idea of the present invention is not limited thereto, and the present invention includes n (n is an integer of 2 or more) times. Of course. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

A liquid crystal display device which sequentially blinks a plurality of lamps along a scanning direction of a liquid crystal display panel, A scanning inverter for driving the lamps according to a lamp scanning frequency; An image detection unit for analyzing whether the still image and the moving image are input by analyzing the input image; A frame frequency detector for detecting a frame frequency of the input image; And When the input image is a still image and the frame frequency is less than 60Hz, the lamp scanning frequency is multiplied by n (n is an integer of 2 or more) compared to the frame frequency to provide a first inverter control unit to increase the flashing speed of the lamps Liquid crystal display device characterized in that. The method of claim 1, A vertical synchronous signal adjusting unit for adjusting a vertical synchronous signal supplied to the first inverter control unit in response to the control signal generated by the frame frequency detecting unit; And the first inverter controller controls the inverter so that the lamps flash n times (n is an integer of 2 or more) for one frame by using the adjusted vertical synchronization signal and the frame frequency less than 60 Hz. Device. The method of claim 2, The vertical synchronous signal adjusting unit, A transistor having a base terminal to which the control signal is input, a collector terminal connected to an input terminal for supplying the vertical synchronization signal, and an emitter terminal connected to ground; And And an output node connected between said collector terminal and an input terminal of said transistor. The method of claim 3, wherein And the control signal is maintained in a high logic state when the input image is a still image and the frame frequency is less than 60 Hz. The method of claim 1, When the input image is a moving image or a still image having a frame frequency of 60Hz or more, a second inverter control unit for controlling the flashing of the lamps by maintaining the lamp scanning frequency equal to the frame frequency further comprises a liquid crystal Display. A driving method of a liquid crystal display device which sequentially blinks a plurality of lamps along a scanning direction of a liquid crystal display panel, Analyzing whether the still image and the moving image are input by analyzing the input image; Detecting a frame frequency of the input image; Multiplying the ramp scanning frequency by n (n is an integer of 2 or more) compared to the frame frequency when the input image is a still image and the frame frequency is less than 60 Hz; And And driving the lamps according to the multiplied lamp scanning frequency to increase the flashing speed of the lamps. The method of claim 6, Adjusting a vertical synchronization signal supplied from a system by using the control signal generated in the frame frequency detection step; And in the ramp scanning frequency multiplying step, multiply the ramp scanning frequency by using the adjusted vertical synchronization signal and a frame frequency of less than 60 Hz. The method of claim 6, If the input image is a moving image or a still image having a frame frequency of 60Hz or more, further comprising the step of controlling the flashing of the lamp by maintaining the lamp scanning frequency equal to the frame frequency of the liquid crystal display device Driving method.

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