KR20080106695A - Chemical etchant and method of fabricating semiconductor devices using the same - Google Patents

Abstract

An etching solution and a method of manufacturing a semiconductor device using the same are provided. The manufacturing method includes preparing a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate has a support substrate having a first impurity concentration and an active layer having a second impurity concentration lower than the first impurity concentration on a main surface of the support substrate. An integrated circuit is formed on the active layer. An insulating film is formed on the integrated circuit. The second semiconductor substrate and the insulating layer are bonded to each other to form a bonding substrate. It consists of hydrofluoric acid (HF), nitric acid (HNO ₃ ), phosphoric acid (H ₃ PO ₄ ), acetic acid (CH ₃ COOH) and water, the hydrofluoric acid (HF), the nitric acid (HNO ₃ ), the phosphoric acid (H ₃ PO ₄ ), An etching solution having a volume composition ratio of the acetic acid (CH ₃ COOH) and the water of 0.8 to 1.2 Vol%, 2.8 to 3.2 Vol%, 0.25 to 3.0 Vol%, 4.0 to 7.75 Vol%, and 84.85 to 92.15 Vol%, respectively. To selectively remove the support substrate.

Description

Etching solution and method for manufacturing semiconductor device using same {Chemical etchant and method of fabricating semiconductor devices using the same}

1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to the present invention.

Figure 2 is a graph showing the etching rate of the impurity regions according to the volume composition ratio of the etching solution according to the present invention.

3A is a plan view showing a test substrate used in an experimental example of the present invention.

FIG. 3B is a graph illustrating the etching rate and uniformity of a high concentration P-type impurity region according to a change in revolution number (RPM) of a substrate in a spin type etching apparatus using an etching solution according to an embodiment of the present invention.

FIG. 3C is a graph illustrating the etching rate and uniformity of the low concentration P-type impurity region according to the change in revolution number (RPM) of the substrate in the spin type etching apparatus using the etching solution according to an embodiment of the present invention.

4 is a graph illustrating etching rates and uniformity according to concentrations of P-type impurity regions in a process of etching P-type impurity regions using an etching solution according to an exemplary embodiment of the present invention.

The present invention relates to an etching solution and a method for manufacturing a semiconductor device, and more particularly, to an etching solution capable of selectively removing any one of impurity layers having different impurity concentrations and a method for manufacturing a semiconductor device using the same.

An image sensor is a semiconductor module that converts an optical image into an electrical signal and is used to store the image signal with a storage, transmission, and display device. The image sensor may be broadly classified into a charge-coupled device (CCD) and a CMOS image sensor (CIS) based on a silicon semiconductor. On the other hand, the size of each pixel included in the image sensor is decreasing according to the trend toward miniaturization and high pixel size of the image sensor. Accordingly, the light sensitivity of the image sensor may be lowered, and it may be difficult to realize a clear image under a predetermined illuminance. As a result, in recent years, in the form of a backside illuminated image sensor (BIS) has been trying to overcome the problem of degradation of the light sensitivity.

However, performing backside illumination requires an optional etching process that reduces the thickness of the initial wafer, ie, the initial substrate, formed on the backside of the wafer, and the color filter and microlens on the back of the etched substrate. Should be formed. In this case, the initial substrate has a structure in which a first impurity layer having a first impurity concentration and a second impurity layer having a second impurity concentration lower than the first impurity concentration are sequentially stacked. 2 formed on the impurity layer. Therefore, the selective etching process may correspond to a process of removing the first impurity layer to leave the second impurity layer. The first and second impurity layers may be P-type impurity layers. That is, the concentration of the first P-type impurity layer may be higher than the concentration of the second P-type impurity layer.

The first P-type impurity layer may be selectively removed using plasma etching or ion etching. However, the plasma etch or ion etch may provide etch damage to the surface of the substrate. In addition, the substrate may be contaminated by a metal such as nickel or iron during the plasma etching or ion etching. In this case, leakage current characteristics of the junction regions formed in the substrate may be degraded.

In order to solve the disadvantages of the plasma etching process or the ion etching process, a wet etching solution suitable for selectively removing the first P-type impurity layer has been proposed. As the wet etching solution, a mixed solution of an oxidizing agent, a reducing agent and a buffer has been widely used. For example, the wet etching solution may be a mixed solution of hydrofluoric acid (HF), nitric acid (HNO ₃ ), and acetic acid (CH ₃ COOH) (hereinafter referred to as “HNA solution”). In the wet etching process using the HNA solution, the first P-type impurity layer has an etching selectivity of about 25: 1 to 100: 1 with respect to the second P-type impurity layer depending on the impurity concentration. However, in the wet etching process using the HNA solution, the first P-type impurity layer may be unevenly removed.

On the other hand, the HNA solution exhibits an etching rate of about 0.7 μm / min to 3 μm / min on a silicon substrate having a resistivity of about 0.01 μm · cm or less, but exhibits a significantly low etching rate on a silicon substrate having a specific resistance of about 0.068 μm · cm. Can be. The HNA solution may be diluted with deionized water to adjust the etch rate for the first P-type impurity layer. In this case, the etching rate of the first P-type impurity layer may be slow but spots may occur on the surface of the silicon substrate having the first P-type impurity layer, and a secondary cleaning process for removing the spots may be further performed. do. In addition, the HNA solution may be difficult to uniformly and uniformly remove the first P-type impurity layer with a high selectivity with respect to the second P-type impurity layer in a spin type etching equipment.

An object of the present invention is to provide an etching solution capable of selectively and uniformly etching one of impurity regions into which impurity ions are implanted into different doses.

Another object of the present invention is to provide a method of manufacturing a semiconductor device using an etching solution capable of selectively and uniformly etching one of the impurity regions implanted with impurity ions into different doses.

According to an aspect of the present invention for achieving the above technical problem, there is provided an etching solution capable of selectively etching any one of the impurity layers having different impurity concentrations. The etching solution consists of a mixed solution of hydrofluoric acid (HF), nitric acid (HNO ₃ ), phosphoric acid (H ₃ PO ₄ ), acetic acid (CH ₃ COOH) and water, the hydrofluoric acid (HF), the nitric acid (HNO ₃ ), Volumetric ratios of the phosphoric acid (H ₃ PO ₄ ), the acetic acid (CH ₃ COOH) and the water are 0.8 to 1.2 Vol%, 2.8 to 3.2 Vol%, 0.25 to 3.0 Vol%, 4.0 to 7.75 Vol%, and 84.85 to 92.15 Vol%.

In some embodiments of the present invention, the mixed solution is a 50% solution of hydrofluoric acid (HF), 75% solution of nitric acid (HNO ₃ ), 85% solution of phosphoric acid (H ₃ PO ₄ ) and 99.9% concentration of It may be a solution containing an aqueous solution of acetic acid (CH ₃ COOH).

According to another aspect of the present invention for achieving the above technical problem, there is provided a method for manufacturing a semiconductor device using an etching solution capable of selectively etching any one of the impurity layers having different impurity concentrations. The manufacturing method includes preparing a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate has a support substrate having a first impurity concentration and an active layer having a second impurity concentration lower than the first impurity concentration on a main surface of the support substrate. An integrated circuit is formed on the active layer. An insulating film is formed on the integrated circuit. The second semiconductor substrate and the insulating layer are bonded to each other to form a bonding substrate. It consists of hydrofluoric acid (HF), nitric acid (HNO ₃ ), phosphoric acid (H ₃ PO ₄ ), acetic acid (CH ₃ COOH) and water, the hydrofluoric acid (HF), the nitric acid (HNO ₃ ), the phosphoric acid (H ₃ PO ₄ ), An etching solution having a volume composition ratio of the acetic acid (CH ₃ COOH) and the water of 0.8 to 1.2 Vol%, 2.8 to 3.2 Vol%, 0.25 to 3.0 Vol%, 4.0 to 7.75 Vol%, and 84.85 to 92.15 Vol%, respectively. To selectively remove the support substrate.

In some embodiments of the present disclosure, the support substrate may have a first P-type impurity concentration, and the active layer may have a second P-type impurity concentration lower than the first P-type impurity concentration.

In another embodiment, prior to selectively removing the support substrate, the method may further include removing a portion of the support substrate by performing a grinding and polishing process on the support substrate.

In another embodiment, the etching solution may contain an ionic and / or nonionic surfactant.

In another embodiment, selectively removing the support substrate may be performed in a spin type etching device or a dip type etching device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Portions denoted by like reference numerals denote like elements throughout the specification.

First, a manufacturing method of an image sensor according to the present invention will be described with reference to FIGS. 1A to 1C.

1A to 1C are cross-sectional views illustrating a method of manufacturing an image sensor according to the present invention.

Referring to FIG. 1A, first and second semiconductor substrates 1 and 3 are prepared. The first semiconductor substrate 1 may include a support substrate 5 and an active layer 7 stacked on a main surface of the support substrate 5. The support substrate 5 may be a P-type silicon substrate having a first impurity concentration, and the active layer 7 may be a P-type epitaxial layer having a second impurity concentration lower than the first impurity concentration.

The support substrate 5 may be a high concentration P-type impurity region, for example, an impurity region having a boron ion concentration of about 2 × 10 ¹⁸ particles / cm ³ or more and having a resistivity of about 10 mPa · cm. The active layer 7 may be a low concentration P-type impurity region, for example, an impurity region having a boron ion concentration lower than that of the supporting substrate 5 and having a specific resistance of about 30 Pa · cm. In this case, the active layer 7 may be an impurity region having a boron ion concentration of about 4.41 × 10 ¹⁴ particles / cm ³ . On the other hand, the support substrate 5 and the active layer 7 may have a concentration variation area (TA) in which the concentration of ions implanted at their interface is continuously changed. That is, it may be difficult to accurately determine the interface between the support substrate 5 and the active layer 7.

The first semiconductor substrate 1 may be a substrate used for a backside illuminated image sensor (BIS) having a pixel region. In this case, an impurity region having a different conductivity type from that of the active layer 7 may be formed on the surface of the active layer 7 to form a photodiode (PD) in the first semiconductor substrate 1. . More specifically, when the active layer 7 is a low concentration P-type impurity region, the photodiode PD may be formed by implanting N-type impurity ions at a high concentration on the surface of the active layer 7.

The insulating film 9 is formed on the active layer 7 using a conventional process, for example, chemical vapor deposition (CVD). The insulating layer 9 may be a silicon oxide layer, and wirings 11 may be formed in the insulating layer 9. The wirings 11 are local interconnections electrically connecting pixel transistors formed in the pixel region of the rear illumination image sensor to each other, or control lines electrically connected to gate electrodes of the pixel transistors. lines).

1B and 1C, a bonding substrate 20 is formed by bonding an insulating film 9 on the first semiconductor substrate 1 and one surface of the second semiconductor substrate 3 to each other. The support substrate 5 is fabricated using a conventional grinding and polishing process, for example, a chemical mechanical polishing (CMP) process, on the support substrate 5 of the bonding substrate 20. Part of the top can be removed. In this case, the thickness of the support substrate 5 remaining may be about 50 μm.

A wet etching process may be performed to selectively remove the remaining support substrate 5. The wet etching process may be performed using a spin type etching apparatus including a spin spray method or a DI-sonic method using an etching solution, or a dip type etching method including a ultrasonic method. Can be performed with equipment. The etching solution is a solution in which hydrofluoric acid (HF), nitric acid (HNO ₃ ), phosphoric acid (H ₃ PO ₄ ), acetic acid (CH ₃ COOH) and water are mixed at a predetermined volume composition ratio (hereinafter referred to as “HNPA solution”). Can be. In one embodiment of the present invention, the HNPA solution has a volume composition ratio of hydrofluoric acid (HF), nitric acid (HNO ₃ ), phosphoric acid (H ₃ PO ₄ ), acetic acid (CH ₃ COOH) and water, respectively 0.8 to 1.2 Vol%, 2.8 To 3.2 Vol%, 0.25 to 3.0 Vol%, 4.0 to 7.75 Vol% and 84.85 to 92.15 Vol% etching solution.

The etching solution according to an embodiment of the present invention may be prepared using 50% hydrofluoric acid solution, 75% nitric acid solution, 85% phosphoric acid solution and 99.9% acetic acid solution as reagents. Can be. In this case, water may be used only in an amount already contained in the aqueous solutions. The etching solution may be mixed in a chemical mixing bottle such that the reagent reactants have the volume ratio described above. The mixing vessel may be kept stirred at all times while mixing the aqueous solutions. The sterling may be performed using an ultrasonic or magnetic stirrer.

The etching solution may be prepared by mixing hydrofluoric acid solution, nitric acid solution, phosphoric acid solution and acetic acid solution in order into the mixing vessel. In this case, the HNPA solution having a volume composition ratio of the hydrofluoric acid, the nitric acid, the phosphoric acid, and the acetic acid in a ratio of 1: 3: 1: 7 is 4.5% and 20.9 in concentrations of the hydrofluoric acid, the nitric acid, the phosphoric acid, the acetic acid, and water, respectively. %, 5.5%, 50.8% and 18.3% etching solution.

While the reagent reactants are mixed, the acids may react with each other to generate heat. Therefore, the mixing vessel may be left in the mixing vessel for a sufficient time to put the hydrofluoric acid solution and the nitric acid solution in order to completely cool the heat. Thereafter, the etching solution may be prepared by putting an aqueous solution of phosphoric acid in the mixing vessel for a sufficient time to completely cool the heat again, and mixing the acetic acid solution. In this case, the aqueous solution may be mixed while cooling the mixing vessel with a cooling tool to shorten the time for preparing the etching solution. After the mixing is finished, the etching solution may be stored in a mixing vessel at room temperature.

When the support substrate 5 and the active layer 7 are high concentration P-type impurity regions and low concentration P-type impurity regions, respectively, the support substrate 5 and the active layer 7 may be 300 in an etching process using the HNPA solution. It can have a high etching selectivity of more than 1: 1. In this case, the HNPA solution may remove the support substrate 5 and the active layer 7 at a rate of about 780 nm / min and about 2.3 nm / min, respectively. As a result, the HNPA solution can remove the support substrate 5 with a high etching selectivity of about 339: 1 compared to the active layer 7.

However, since the HNPA solution is greatly influenced by the impurity ion concentration change of the support substrate 5 and the active layer 7, the concentration variation region formed at the boundary region of the support substrate 5 and the active layer 7 ( It can be difficult to remove TA). Therefore, an etching process may be further performed to remove the concentration variation region TA in which the concentration of impurity ions continuously changes at the interface between the support substrate 5 and the active layer 7. For example, the concentration variation area TA may be removed using an etching solution having an etching rate independent of the concentration in a semiconductor substrate having an impurity concentration of 2 × 10 ¹⁸ / cm ³ or less. The etching process may be performed using a 10% potassium hydroxide (KOH) aqueous solution having an etching rate of about 100nm / min for the silicon. In this case, a part of the active layer 7 in the concentration variation area TA may also be removed.

Meanwhile, in order to smoothly etch the support substrate 5, an ionic and / or nonionic surfactant may be added to the etching solution. A chemical mechanical polishing process for buffering may be performed on the bonding substrate 20 having the active layer 7. As a result, the bonding substrate 20 may be formed of a semiconductor substrate 30 suitable for manufacturing the back illumination image sensor by removing the support substrate 5.

<Experiment examples: examples>

Figure 2 is a graph showing the etching rate of the impurity regions according to the volume composition ratio of the etching solution according to the present invention.

In FIG. 2, the horizontal axis represents the volume composition ratio of the HNPA solution, and the vertical axis represents the etching rate of the semiconductor substrate having the high concentration P-type impurity region and the low concentration P-type impurity region. In this case, the present experimental example was performed by changing the volume composition ratio of phosphoric acid and acetic acid while maintaining the volume composition ratio of hydrofluoric acid and nitric acid, which play an important role in etching the semiconductor substrate.

Data denoted by reference numeral "41" is a high concentration P-type impurity region and low concentration P-type impurity using an etching solution having a volume composition ratio of 1: 3: 1: 7 (HNPA-1317 solution) of hydrofluoric acid, nitric acid, phosphoric acid, and acetic acid, respectively. Indicates the etch rate measured for the area. Data denoted by reference numeral 43 represents an etch rate measured for the impurity regions using an etching solution in which the volume composition ratio of the acids is 1: 3: 4: 4 (HNPA-1344 solution), respectively. In addition, the data indicated by the reference numeral "45" is the etch rate measured for the impurity regions using an etching solution having a volume composition ratio of hydrofluoric acid, nitric acid, phosphoric acid and acetic acid 1: 3: 7: 1 (HNPA-1371 solution). Indicates.

The test substrate showing the measurement results of FIG. 2 includes a silicon substrate having a high concentration P-type impurity region and an epitaxial layer stacked on a main surface of the silicon substrate and having a P-type impurity region lower than the high concentration P-type impurity region. do. A silicon oxide film was formed on the epitaxial layer. The epitaxial layer was measured to have a specific resistance of about 30 Pa · cm and a boron ion concentration of about 4.41 × 10 ¹⁴ / cm ³ . The silicon substrate was measured to have a resistivity of about 10 mPa · cm and a boron ion concentration of about 8.49 × 10 ¹⁸ / cm ³ . The silicon oxide film was formed to a thickness of about 115 kPa by performing a conventional deposition process, for example, a chemical vapor deposition (CVD) process.

A silicon nitride film was deposited on the silicon oxide film, and the silicon oxide film and the silicon nitride film were sequentially patterned to expose the epitaxial layer or the silicon substrate to form a single pattern. As a result, the fabricated test substrate was fabricated to have the same impurity regions as the semiconductor substrate used in the back illumination image sensor described in FIGS. 1A to 1C of the present invention. This <Experimental Example> was carried out for 10 minutes at room temperature while the test substrate was immersed in a beaker containing an etching solution to stir the beaker.

As can be seen from the graph of FIG. 2, the etching amounts of the silicon substrate and the epitaxial layer in the HNPA-1317 solution were about 25 μm and about 0.075 μm, respectively, and the silicon substrate and the epitaxy in the HNPA-1344 solution. The etching amount of the ear layer was about 12.5 μm and about 13.25 μm, respectively. In addition, the etching amounts of the silicon substrate and the epitaxial layer in the HNPA-1371 solution were about 8.17 μm and about 9.25 μm, respectively. The etching amounts were measured by measuring thickness using a vertical scanning electron microscope (VSEM) apparatus.

In the present experimental example, as the volume composition ratio of phosphoric acid in the HNPA solution was increased and the volume composition ratio of acetic acid was lowered, the etching amount and the etching selectivity for the silicon substrate decreased. As a result, it was found that the HNPA-1317 solution has a high etching selectivity of about 333: 1 or more for the silicon substrate and the epitaxial layer, and a relatively high etching rate for the silicon substrate. Next, in order to confirm that the HNPA-1317 solution has a high etching selectivity with respect to the silicon substrate and the epitaxial layer, the volume composition ratio of phosphoric acid and acetic acid is finely adjusted in [Table 1]. The test results are shown.

As shown in Table 1, when the volume composition ratio of phosphoric acid and acetic acid was 1: 7 or more, the etching selectivity of the silicon substrate and the epitaxial layer was 1000: 1 or more. However, when the volume composition ratio of phosphoric acid is less than 1, it may be difficult to control the etching rate of the silicon substrate. Meanwhile, when the volume composition ratio of the phosphoric acid and acetic acid solution is 1.25: 6.75, the etching selectivity of the silicon substrate and the epitaxial layer is similar to the case where the volume composition ratio of the solutions is 1: 7, but the volume composition ratio is precisely controlled. It can be difficult. As a result, HNPA-1317 solution having a volume ratio of 1: 7 of phosphoric acid and acetic acid solution may be optimal in terms of etching rate and etching selectivity for the silicon substrate.

3A is a plan view showing a test substrate used in an experimental example of the present invention.

FIG. 3B is a graph illustrating the etching rate and uniformity of a high concentration P-type impurity region according to a change in revolution number (RPM) of a substrate in a spin type etching apparatus using an etching solution according to an embodiment of the present invention.

FIG. 3C is a graph illustrating the etching rate and uniformity of the low concentration P-type impurity region according to the change in revolution number (RPM) of the substrate in the spin type etching apparatus using the etching solution according to an embodiment of the present invention. 4 is a graph illustrating etching rates and uniformity according to concentrations of P-type impurity regions in a process of etching P-type impurity regions using an etching solution according to an exemplary embodiment of the present invention.

3A to 3C, the horizontal axes position the flat zone plane FZ of the test substrate 60 on the upper side and the left area L, the left center area LC, and the center area C from the left edge to the right. ), Right center region CR and right region R. As shown in FIG.

Meanwhile, in FIG. 3B, the vertical axis represents the revolution per revolution of the test substrate 60 with respect to the regions L, LC, C, CR, and R of the test substrate 60 having a high concentration P-type impurity region. The etching amount according to the change of minute (rpm) is shown. In FIG. 3C, the rotational speed RPM of the test substrate 60 is changed with respect to the regions L, LC, C, CR, and R of the test substrate 60 having a vertical axis having a P-type shallow impurity region. Represents the amount of etching. In FIGS. 3B and 3C, the data represented by the symbol "-◆-", the symbol "-■-" and the symbol "-▲-" indicate that the rotation speed of the test substrate 60 is 200 RPM, 300 RPM and 500 RPM, respectively. Etch amounts for the regions L, LC, C, CR, and R are shown. In addition, the data indicated by the symbol "-x-" and the symbol "-●-" correspond to the regions L, LC, C, CR, and R at the rotational speed of the test substrate 60 at 700 RPM and 1400 RPM, respectively. Indicates the etching amount.

The test substrate 60 showing the measurement results of FIGS. 3B and 3C was a substrate manufactured in the same manner as the test substrate described with reference to FIG. 2. On the other hand, the spin etching apparatus of the present experiment has a dispenser (dispenser) that can spray the solution on the test substrate 60. Therefore, the present experiment was performed for 10 minutes by spraying the etching solution to the central region (C) of the test substrate 60 for each RPM of the test substrate 60.

As can be seen from the graphs of FIGS. 3B and 3C, the change in the etching amount of the regions L, LC, C, CR, and R with respect to the high concentration P-type impurity region at the rotational speeds of 700 RPM and 1400 RPM is very small. Was measured. Meanwhile, at 300 RPM, the regions L, LC, C, CR, and R were etched to a thickness of about 20 μm to 35 μm, showing a relatively large amount of etching, but were etched unevenly. However, at 200 RPM, the regions L, LC, C, CR, and R were etched relatively uniformly with a thickness of about 8 μm to 10 μm.

In contrast, the regions L, LC, C, CR, and R for the low concentration P-type impurity region showed smaller etching amounts in the high concentration P-type impurity region. Therefore, in the spin type apparatus, the HNPA-1317 solution was found to have a relatively optimal etching rate and uniformity when etching the high concentration P-type impurity region at a rotation speed of 200 RPM.

4 is a graph showing the change in the etching amount of the low concentration P-type impurity region according to the impurity ion concentration using HNPA-1317 solution. 3A and 4, the horizontal axis is a top region T, a center region C, and a top region along a plane perpendicular to the flat zone plane FZ about the center region C of the semiconductor substrate 60. The lower region B is shown. On the other hand, the vertical axis represents the change in the etching amount measured by varying the impurity ion concentration in the low concentration P-type impurity region.

In Fig. 4, the data represented by the symbol "-◆-" and the symbol "-■-" are P-type low concentrations when the impurity ion concentration is about 8.5 x 10 ¹⁴ / cm ³ and about 5.10 x 10 ¹⁵ / cm ³ , respectively. The etching amount of the impurity region is shown. In addition, the data indicated by the symbol "-▲-" and the symbol "-●-" indicate that the impurity ion concentration of the low concentration P-type impurity region is about 4.80 × 10 ¹⁶ / cm ³ and about 1.6 × 10 ¹⁸ / cm ³ , respectively. Indicates the etching amount.

The test substrates showing the measurement results of FIG. 4 were substrates manufactured in the same manner as the test substrate described with reference to FIG. 2. In the experimental example of FIG. 4, a dispenser capable of dispensing HNPA-1317 solution in a central region C of a test substrate in a spin type apparatus is placed, and at a room temperature for 10 minutes at a rotational speed of 200 RPM. Was carried out. Although not shown, when the concentration of the high concentration P-type impurity region is 8.49 × 10 ¹⁸ / cm ³ , the etching amount of the top region T, the central region C, and the lower region B is about 6.7 μm and about 7.1 μm, respectively. And about 9.6 μm. As a result, the average etching amount of the high concentration P-type impurity region was about 7.8 μm. The graph of FIG. 4 is shown from the data shown in [Table 2].

As can be seen from FIG. 4 and [Table 2], the ion concentration of the low concentration P-type impurity region is 20% of the ion concentration of the high concentration P-type impurity region, that is, the impurity ion concentration of 1.60 in the low concentration P-type impurity region is 1.60. In the case of × 10 ¹⁸ / cm ³ , the average etching amount of the regions T, C, and B was reduced by about 99.6% compared to the average etching amount of the high concentration P-type impurity region. As a result, the high concentration P-type impurity region and the low concentration P-type impurity region were found to have an optimal etching selectivity when the HNPA-1317 solution was etched at 200 RPM in a spin type etching equipment. In addition, the etching uniformity was relatively high with respect to the high concentration P-type impurity region under the above conditions.

As described above, according to the present invention, an etching solution capable of selectively removing any one of impurity layers having different impurity concentrations in a semiconductor substrate is provided. In particular, the etching solution has a high etching selectivity for the high concentration P-type impurity layer and the low concentration P-type impurity layer. In addition, the etching solution can remove the high concentration P-type impurity region at high speed while maintaining uniformity even when used in the spin type etching equipment. As a result, the semiconductor devices may be manufactured by uniformly removing the high concentration P-type impurity region at a higher etching selectivity than the low concentration P-type impurity region.

Claims (7)

It consists of a mixed solution of hydrofluoric acid (HF), nitric acid (HNO ₃ ), phosphoric acid (H ₃ PO ₄ ), acetic acid (CH ₃ COOH) and water, the hydrofluoric acid (HF), the nitric acid (HNO ₃ ), the phosphoric acid (H ₃ PO ₄ ), the volume ratio of the acetic acid (CH ₃ COOH) and the water is 0.8 to 1.2 Vol%, 2.8 to 3.2 Vol%, 0.25 to 3.0 Vol%, 4.0 to 7.75 Vol%, and 84.85 to 92.15 Vol%, respectively Etch solution. The method of claim 1, The mixed solution is a 50% solution of hydrofluoric acid (HF), 75% solution of nitric acid (HNO ₃ ), 85% solution of phosphoric acid (H ₃ PO ₄ ) and 99.9% solution of acetic acid (CH ₃ COOH) solution An etching solution, characterized in that the solution containing. Preparing a first semiconductor substrate and a second semiconductor substrate, wherein the first semiconductor substrate includes a support substrate having a first impurity concentration and an active layer having a second impurity concentration lower than the first impurity concentration on a main surface of the support substrate. Equipped, Forming an integrated circuit on the active layer, An insulating film is formed on the integrated circuit, Bonding the second semiconductor substrate and the insulating layer to form a bonding substrate, It consists of hydrofluoric acid (HF), nitric acid (HNO ₃ ), phosphoric acid (H ₃ PO ₄ ), acetic acid (CH ₃ COOH) and water, the hydrofluoric acid (HF), the nitric acid (HNO ₃ ), the phosphoric acid (H ₃ PO ₄ ), An etching solution having a volume composition ratio of the acetic acid (CH ₃ COOH) and the water of 0.8 to 1.2 Vol%, 2.8 to 3.2 Vol%, 0.25 to 3.0 Vol%, 4.0 to 7.75 Vol%, and 84.85 to 92.15 Vol%, respectively. And selectively removing the support substrate using the semiconductor device. The method of claim 3, wherein The support substrate has a first P-type impurity concentration, and the active layer has a second P-type impurity concentration lower than the first P-type impurity concentration. The method of claim 3, wherein And removing the support substrate partially by performing grinding and polishing processes on the support substrate before selectively removing the support substrate. The method of claim 3, wherein The etching solution is a method of manufacturing a semiconductor device, characterized in that it contains an ionic and / or nonionic surfactant (surfactant). The method of claim 3, wherein Selectively removing the support substrate is performed in a spin type etching equipment or a dip type etching equipment.

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