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KR20080102641A - Semiconductor package including a heat spreader - Google Patents

Semiconductor package including a heat spreader Download PDF

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Publication number
KR20080102641A
KR20080102641A KR1020070049325A KR20070049325A KR20080102641A KR 20080102641 A KR20080102641 A KR 20080102641A KR 1020070049325 A KR1020070049325 A KR 1020070049325A KR 20070049325 A KR20070049325 A KR 20070049325A KR 20080102641 A KR20080102641 A KR 20080102641A
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KR
South Korea
Prior art keywords
semiconductor chip
heat spreader
insulating layer
package
metal pattern
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Application number
KR1020070049325A
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Korean (ko)
Inventor
송은석
Original Assignee
삼성전자주식회사
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Priority to KR1020070049325A priority Critical patent/KR20080102641A/en
Publication of KR20080102641A publication Critical patent/KR20080102641A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

A semiconductor package including the heat spreader is provided to improve the heat emitting characteristic by having the fan-out structure for forming the solder ball. A semiconductor package including the heat spreader comprises the semiconductor chip(100) in which the pad is formed; the metal pattern(140) for the rerouting connecting the pad to the solder ball(150); the heat spreader(120) in which the semiconductor chip is adhered; the metal pattern for rerouting is arranged by sealing the semiconductor chip; the insulating layer(132,131) in which the solder ball is formed. The area on which the heat spreader is arranged for the fan out structure and the area on which the solder ball is arranged are broader than the area of the semiconductor chip. The heat spreader is made of the metal material.

Description

히트 스프레더를 구비한 반도체 패키지{Semiconductor package including a heat spreader}Semiconductor package including a heat spreader

도 1은 종래의 RCP(redistributed chip package)의 제조 방법을 도시한 설명도이다.1 is an explanatory diagram illustrating a method of manufacturing a conventional distributed chip package (RCP).

도 2는 종래의 팬 인 타입 패키지를 도시한 배면도이다.Figure 2 is a rear view showing a conventional fan in type package.

도 3은 종래의 팬 아웃 타입 패키지를 도시한 배면도이다.3 is a rear view showing a conventional fan out type package.

도 4 및 도 5는 본 발명의 서로 다른 실시예로서, 히트 스프레더를 구비한 반도체 패키지를 도시한 단면도이다.4 and 5 are cross-sectional views illustrating a semiconductor package having a heat spreader as another embodiment of the present invention.

도 6은 본 발명에 따른 반도체 패키지가 인쇄회로기판에 실장된 상태를 도시한 단면도이다.6 is a cross-sectional view showing a state in which a semiconductor package according to the present invention is mounted on a printed circuit board.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

100...반도체 칩 110...접착 부재100 ... semiconductor chip 110 ... adhesive member

120,120'...히트 스프레더(heat spreader) 125...함몰부120,120 '... heat spreader 125 ... recessed

131...제1 절연층 132...제2 절연층131 ... first insulating layer 132 ... second insulating layer

140...재배치용 금속 배선 150,150'...솔더볼140 ... Reposition Metal Wiring 150,150 '... Solder Ball

160...패드 180...인쇄회로기판160 ... Pad 180 ... Printed Circuit Board

본 발명은 반도체 패키지에 관한 것으로, 구체적으로 반도체 칩에 마련된 패드를 재배치용 금속 패턴을 이용하여 외부의 솔더 볼과 연결함으로써 팬 아웃 구조를 달성하는 재배선 패키지(RCP : redistributed chip package)에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a redistributed chip package (RCP) that achieves a fan-out structure by connecting pads provided on a semiconductor chip with an external solder ball using a repositioning metal pattern. .

반도체 패키지를 만드는 패키징 공정(packaging process)은 반도체 칩에 외부연결단자를 연결해주고, 외부의 충격으로부터 반도체 칩이 보호될 수 있도록 반도체 칩을 밀봉해주는 일련의 공정을 말한다. The packaging process of making a semiconductor package is a series of processes that connect an external connection terminal to a semiconductor chip and seal the semiconductor chip to protect the semiconductor chip from external shock.

최근 전자산업이 발전함에 따라 반도체 패키지는 소형화, 경량화, 제조비용의 절감에 목표를 두고 다양한 방향으로 발전해가고 있다. 또한 그 응용분야가 디지털 화상기기, MP3 플레이어, 모바일 폰(mobile phone), 대용량 저장수단 등으로 확장됨에 따라 다양한 종류의 반도체 패키지가 등장하고 있다. 이에 따라 패키지 종류는 BGA(Ball Grid Array), CSP(Chip Scale Package)구조는 물론, SIP(Single In-line Package), POP(Package-on-Package), MSP(Multi Stack Package)등의 3D 구조로 스택된 패키지와, 패키지 사이즈를 최소화할 수 있는 웨이퍼 레벨 패키지(WLP : Wafer Level Package, WFP : Wafer Level Fabricated Package) 또는 임베디드 타입(embeded type) 등으로 변화하고 있다. With the recent development of the electronics industry, semiconductor packages are developing in various directions with the goal of miniaturization, light weight, and reduction of manufacturing cost. In addition, various types of semiconductor packages have emerged as their application fields are extended to digital image devices, MP3 players, mobile phones, and mass storage means. Accordingly, package types include 3D structures such as Ball Grid Array (BGA), Chip Scale Package (CSP), Single In-line Package (SIP), Package-on-Package (POP), and Multi Stack Package (MSP). It is changing to a wafer stacked package, a wafer level package (WLP: Wafer Level Fabricated Package) or an embedded type (embedded type) that can minimize the package size.

특히, 웨이퍼 레벨 패키지는 칩 사이즈와 동일한 패키지 사이즈를 구현할 수 있다는 장점을 갖는다. 그러나 반도체 칩의 제조 공정이 고집적화됨에 따라 반도체 칩 크기는 점차 줄어들고(shrink) 있으나, 솔더 볼 사이의 간격은 세계반도체표준 협회(JEDEC)의 국제표준이 지정한 규격을 만족하여야 한다. In particular, the wafer level package has the advantage of realizing a package size equal to the chip size. However, as semiconductor chip manufacturing processes are highly integrated, semiconductor chip sizes gradually shrink, but the spacing between solder balls must meet the specifications specified by the International Standards for Semiconductors (JEDEC).

따라서, 입출력을 위한 솔더 범프 혹은 솔더 볼이 반도체 칩의 면적과 동일한 면적에 배열되는 경우 솔더 범프 혹은 솔더 볼의 수가 당연히 제한된다. 이러한 WFP/WLP 패키지의 단점을 보완하기 위하여 팬 아웃 타입의 재배선 패키지(RCP : Re-distributed Chip Package) 구조가 제안되어 있다. 여기서, 솔더 볼이 반도체 칩과 동일한 면적에 배치된 구조를 팬 인(Fan-in) 구조라 하고, 반도체 칩 외곽까지 확장되는 기판(substrate)에 일부의 솔더 볼이 부착되는 구조를 팬 아웃(Fan-out) 구조라 한다. 그리고, 재배선 패키지(RCP : Re-distributed Chip Package)는 반도체 칩에 형성된 패드를 재배선용 금속 패턴을 이용하여 기판의 넓은 면적에 형성된 솔더 볼과 연결하는 구조의 패키지를 일컫는다.Therefore, when the solder bumps or solder balls for input and output are arranged in the same area as the area of the semiconductor chip, the number of solder bumps or solder balls is naturally limited. In order to make up for the shortcomings of the WFP / WLP package, a fan-out re-distributed chip package (RCP) structure has been proposed. Here, a structure in which solder balls are disposed in the same area as a semiconductor chip is called a fan-in structure, and a structure in which some solder balls are attached to a substrate that extends to the outside of the semiconductor chip is fan-out. out) structure. In addition, a re-distributed chip package (RCP) refers to a package having a structure in which pads formed on a semiconductor chip are connected to solder balls formed on a large area of a substrate using a redistribution metal pattern.

도 1은 종래의 재배선 패키지의 구조를 도시한 설명도이다. 웨이퍼(10) 상에 형성된 반도체 칩을 다이싱(dicing)하고 양품의 다이(good die)(20)를 선별한 다음, 봉지재(encapsulation)(30)로 다이(20)를 감싸서 보호하고, 절연층(40)과 재배선용 금속 패턴(50)을 형성하여 솔더 볼(60)과 반도체 칩의 패드(25)를 팬 아웃 구조로 연결함으로써 재배선 패키지를 완성한다.1 is an explanatory diagram showing the structure of a conventional redistribution package. Dicing the semiconductor chip formed on the wafer 10 and sorting the good die 20, then wrapping and protecting the die 20 with an encapsulation 30, and insulating The redistribution package is completed by forming the layer 40 and the redistribution metal pattern 50 to connect the solder balls 60 and the pad 25 of the semiconductor chip in a fan out structure.

도 2는 종래의 팬 인 타입 패키지를 도시한 배면도이고, 도 3은 종래의 팬 아웃 타입 패키지를 도시한 배면도이다. 도 2 및 도 3을 참조하면 팬 아웃 영역은 다이(20)보다 더 큰 면적을 갖는 봉지재(30)에 의하여 확장된 영역이 되며, 팬 아웃 영역에는 재배선용 금속 패턴(도 1의 50)에 의하여 다이(20)의 패드(25)와 연결되는 솔더 볼(60)이 배치된다.2 is a rear view illustrating a conventional fan in type package, and FIG. 3 is a rear view illustrating a conventional fan out type package. Referring to FIGS. 2 and 3, the fan out area is an area extended by the encapsulant 30 having a larger area than the die 20, and the fan out area has a metal pattern for redistribution (50 in FIG. 1). Solder balls 60 connected to the pads 25 of the die 20 are disposed.

그러나, 봉지재(30)가 합성 수지 또는 몰드(mold) 재질인 경우 열 방출 능력이 저하되는 열 방출 성능의 문제 및 전기적 노이즈 발생에 취약한 전기적 성능의 문제가 발생한다. 이를 개선하기 위하여 봉지재(30)와 별도로 부품으로 방열판 구조를 추가하거나, 넓은 영역에 걸쳐 그라운드(ground) 배선을 마련하는 등의 대책을 취할 수 있다. 그러나, 패키지 구조가 복잡해짐은 물론 봉지재와 방열 부품 및 그라운드 배선을 패키지의 한정된 공간에 함께 설치하는 데 배치의 곤란점이 존재한다.However, when the encapsulant 30 is made of a synthetic resin or a mold, a problem of heat dissipation performance in which the heat dissipation capacity is lowered and a problem of electrical performance vulnerable to generation of electrical noise occur. To improve this, measures such as adding a heat sink structure as a part separately from the encapsulant 30 or providing a ground wiring over a wide area can be taken. However, not only the package structure is complicated, but also there is a difficulty in placing the encapsulant, the heat dissipation component, and the ground wiring together in a limited space of the package.

본 발명의 기술적 과제는 상술한 문제점을 개선하기 위한 것으로, 칩 면적 이외의 팬 아웃 영역에 솔더 볼을 형성할 수 있는 팬 아웃 구조를 갖고 열 방출 특성을 개선할 수 있으며 동시에 전기적 노이즈 발생을 억제할 수 있는 반도체 패키지를 제공하는 것이다.The technical problem of the present invention is to improve the above-mentioned problems, and has a fan out structure capable of forming solder balls in a fan out area other than the chip area, which can improve heat dissipation characteristics and at the same time suppress electrical noise generation. It is to provide a semiconductor package that can be.

상술한 목적을 달성하기 위하여 본 발명의 반도체 패키지는,In order to achieve the above object, the semiconductor package of the present invention,

패드가 형성된 반도체 칩;A semiconductor chip in which pads are formed;

상기 패드를 솔더 볼과 연결하는 재배선용 금속 패턴;A redistribution metal pattern connecting the pad to the solder balls;

상기 반도체 칩이 부착되는 히트 스프레더;A heat spreader to which the semiconductor chip is attached;

상기 히트 스프레더 상에 적층되며 상기 반도체 칩을 밀봉하고 상기 재배선용 금속 패턴이 배치되며 상기 솔더 볼이 형성되는 절연층; 을 포함하며,An insulating layer stacked on the heat spreader and sealing the semiconductor chip, the metal pattern for redistribution is disposed, and the solder balls are formed; Including;

팬 아웃 구조를 위하여 상기 히트 스프레더의 면적 및 상기 솔더 볼이 배치 되는 면적은 상기 반도체 칩의 면적보다 넓고, 상기 히트 스프레더가 금속 재질로 된 것을 특징으로 한다.The area of the heat spreader and the area where the solder balls are disposed for the fan out structure is larger than that of the semiconductor chip, and the heat spreader is made of a metal material.

일 실시예로서, 상기 히트 스프레더는 상기 반도체 칩의 그라운드 배선과 연결된다. In one embodiment, the heat spreader is connected to the ground line of the semiconductor chip.

일 실시예로서, 상기 히트 스프레더는 상기 반도체 칩이 삽입 및 부착되는 함몰부를 구비한다.In one embodiment, the heat spreader has a recess in which the semiconductor chip is inserted and attached.

일 실시예로서, 상기 히트 스프레더는 평판 형상이다.In one embodiment, the heat spreader is flat.

일 실시예로서, 상기 반도체 패키지는 상기 패드가 형성되는 면의 반대 면에 해당하는 상기 반도체 칩의 배면을 상기 히트 스프레더에 부착시키는 것으로 상기 절연층으로 밀봉되는 접착 부재; 를 더 포함한다.In an embodiment, the semiconductor package may include: an adhesive member sealed to the insulating layer by attaching a rear surface of the semiconductor chip corresponding to a surface opposite to a surface on which the pad is formed, to the heat spreader; It further includes.

일 실시예로서, 상기 절연층은 상기 반도체 칩을 밀봉하는 제1 절연층 및 상기 솔더 볼이 형성되는 제2 절연층을 구비하고, 상기 제1 절연층 중 상기 패드에 대응되는 부분이 오픈되며 상기 재배선용 금속 패턴의 일단부와 연결되고, 상기 제2 절연층 중 상기 솔더 볼에 대응되는 부분이 오픈되며 상기 재배선용 금속 패턴의 타단부와 연결된다.In example embodiments, the insulating layer may include a first insulating layer sealing the semiconductor chip and a second insulating layer on which the solder balls are formed, and a portion of the first insulating layer corresponding to the pad may be opened. One end of the redistribution metal pattern is connected, and a portion corresponding to the solder ball of the second insulating layer is opened and is connected to the other end of the redistribution metal pattern.

일 실시예로서, 상기 히트 스프레더가 웨이퍼 상태에서 상기 반도체 칩, 재배선용 금속 패턴, 절연층이 패키징된다. In an embodiment, the semiconductor chip, a metal pattern for redistribution, and an insulating layer are packaged in a state where the heat spreader is a wafer.

이하에서는 첨부한 도면을 참조하여 본 발명의 실시예에 대하여 상세히 설명한다. 본 발명의 실시예는 첨부도면에 도시된 바에 국한되지 않고, 동일한 발명의 범주내에서 다양하게 변형될 수 있음을 밝혀둔다. Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention. Embodiments of the invention are not limited to what is shown in the accompanying drawings, it is to be understood that various modifications can be made within the scope of the same invention.

본 발명은 웨이퍼 레벨 패키지 (WFP/WLP)의 변형으로서 금속 재질의 히트 스프레더에 반도체 칩을 직접 부착함으로써 간단한 구조로 팬 아웃 구조를 형성함은 물론 열 방출 특성과 그라운드 특성을 동시에 향상시킬 수 있는 재배선 패키지(RCP)를 제공한다. 종래에 합성 수지 또는 몰드 재질로 이루어진 봉지재와 별도의 부품으로 방열판을 마련하고 좁은 공간에 이들을 함께 배치하던 구조와 달리, 본 발명에서는 봉지재 없이 금속 재질로 된 히트 스프레더에 반도체 칩을 직접 부착하는 것이 특징이다. 즉, 종래의 팬 아웃 타입의 봉지재는 본 발명에서 금속 재질로 된 히트 스프레더 및 그 여분의 공간에 마련되는 절연층으로 대체된다.The present invention is a modification of a wafer level package (WFP / WLP), by directly attaching a semiconductor chip to a metal heat spreader to form a fan out structure with a simple structure as well as cultivation that can simultaneously improve heat dissipation characteristics and ground characteristics. Provides a pre-packaged package (RCP). Unlike a structure in which a heat sink is provided as a separate part and a separate part made of a synthetic resin or a mold material and arranged together in a narrow space, in the present invention, a semiconductor chip is directly attached to a heat spreader made of a metal material without an encapsulant. Is characteristic. That is, the conventional fan-out type encapsulant is replaced with a heat spreader made of metal and an insulating layer provided in the extra space thereof.

이러한 구조는 기존의 팬 인 타입 웨이퍼 레벨 패키지(WFP/WLP)의 단점인 솔더 볼 개수의 제한을 극복할 수 있음은 물론, 재배선 패키지의 열적/전기적 특성을 향상시킬 수 있다. 즉, 반도체 칩의 배면에 반도체 칩보다 큰 사이즈를 갖는 금속 재질의 히트 스프레더를 부착하고, 반도체 칩의 패드는 재배선용 금속 패턴에 의하여 솔더 볼과 연결된다. 히트 스프레더가 반도체 칩의 배면에 직접 접촉되며 열전도성이 좋은 금속 재질로 이루어지고 반도체 칩보다 큰 크기를 가지므로 팬 아웃 구조를 달성함은 물론 열 방출 성능이 크게 개선되며, 금속 재질로 된 히트 스프레더를 그라운드와 연결함으로써 전기적 노이즈를 크게 억제할 수 있다.Such a structure can overcome the limitation of the number of solder balls, which is a disadvantage of the conventional fan-in type wafer level package (WFP / WLP), as well as improve the thermal / electrical characteristics of the redistribution package. That is, a metal heat spreader having a size larger than that of the semiconductor chip is attached to the rear surface of the semiconductor chip, and the pad of the semiconductor chip is connected to the solder ball by a metal pattern for redistribution. Since the heat spreader is directly in contact with the back surface of the semiconductor chip and is made of a metal with good thermal conductivity and has a larger size than the semiconductor chip, it achieves a fan-out structure and greatly improves heat dissipation performance. The electrical noise can be greatly suppressed by connecting to ground.

도 4 및 도 5는 본 발명의 서로 다른 실시예로서, 히트 스프레더(120,120')를 구비한 반도체 패키지를 도시한 단면도이다. 히트 스프레더(120,120')의 실시예로서, 도 4에 도시된 바와 같이 반도체 칩(100)이 삽입되는 함몰부(125)를 구비한 히트 스프레더(120)와 도 5에 도시된 평판 타입의 히트 스프레더(120')를 들 수 있 다. 도시된 실시예에 한정되지 않고 다양한 형태의 히트 스프레더가 본 발명의 실시예로서 가능하다. 4 and 5 are cross-sectional views illustrating semiconductor packages having heat spreaders 120 and 120 'according to different embodiments of the present invention. As an embodiment of the heat spreaders 120 and 120 ', a heat spreader 120 having a depression 125 into which the semiconductor chip 100 is inserted as shown in FIG. 4 and a heat spreader of the flat plate type shown in FIG. (120 '). Various forms of heat spreaders are possible as embodiments of the present invention, without being limited to the illustrated embodiments.

히트 스프레더(120,120')의 크기가 반도체 칩(100)의 면적보다 더 크므로 히트 스프레더(120,120')에 의하여 반도체 칩(100)의 팬 아웃 영역이 형성된다. 또한, 히트 스프레더(120,120')가 금속 재질로 마련되므로 종래의 봉지재의 역할인 반도체 칩(100)의 보호 기능은 물론, 방열 특성의 개선과 그라운드 배선과의 연결을 통한 노이즈 제거 효과를 적은 수의 부품으로 획득할 수 있다.Since the size of the heat spreaders 120 and 120 ′ is larger than the area of the semiconductor chip 100, the fan spreader regions of the semiconductor chips 100 are formed by the heat spreaders 120 and 120 ′. In addition, since the heat spreaders 120 and 120 'are made of a metal material, as well as the protection function of the semiconductor chip 100, which serves as a conventional encapsulant, the heat dissipation characteristics can be improved and the noise removing effect through the connection to the ground wiring can be reduced. Can be obtained as a part.

좀 더 구체적으로 설명하면, 패드(160)가 형성되는 면의 반대 면인 반도체 칩(100)의 배면을 접착 부재(110)를 이용하여 히트 스프레더(120,120')에 부착한다. 접착 부재(110)는 접착 테이프 또는 접착제로 형성된 층 등 다양한 실시예가 가능하다. 접착 부재(110)는 후술할 제1 절연층(131)에 의하여 밀봉된다. In more detail, the back surface of the semiconductor chip 100, which is the surface opposite to the surface on which the pad 160 is formed, is attached to the heat spreaders 120 and 120 ′ using the adhesive member 110. The adhesive member 110 may be various embodiments, such as a layer formed of an adhesive tape or an adhesive. The adhesive member 110 is sealed by the first insulating layer 131 which will be described later.

히트 스프레더(120,120')는 패키지 사이즈에 맞게 미리 개별적으로 다이싱된 다음 반도체 칩(100)이 패키징되는 실시예, 또는 웨이퍼 상태에서 반도체 칩(100)을 패키징한 다음에 원하는 규격으로 다이싱(dicing)되는 실시예 등 다양한 변형이 가능하다. 히트 스프레더(120,120')를 웨이퍼 상태로 마련한 다음 반도체 칩(100)을 부착하고 절연층(131,132)과 재배선 패턴(140) 및 솔더 볼(150)의 형성을 완료한 다음 개별 패키지로 절단되는 경우 생산성을 대폭 향상시킬 수 있을 것이다.The heat spreaders 120 and 120 'are pre-divided individually according to the package size, and then the semiconductor chip 100 is packaged, or the semiconductor chip 100 is packaged in a wafer state and then diced to a desired size. Various modifications are possible, such as an Example). When the heat spreaders 120 and 120 ′ are prepared in a wafer state, the semiconductor chips 100 are attached to each other, and the insulating layers 131 and 132, the redistribution pattern 140, and the solder balls 150 are formed and then cut into individual packages. Productivity will be greatly improved.

즉, 함몰부(125)를 구비한 형상 또는 평판 형상 등 히트 스프레더(120,120')의 형상을 불문하고 웨이퍼 상태로 히트 스프레더(120,120')가 마련될 수 있으며, 웨이퍼 상태의 히트 스프레더(120,120')에 반도체 칩(100), 재배선용 금속 패 턴(140), 절연층(131,132)이 패키징될 수 있다.That is, the heat spreaders 120 and 120 'may be provided in the wafer state regardless of the shape of the heat spreaders 120 and 120' such as the shape having the depression 125 or the flat plate shape, and the heat spreaders 120 and 120 'in the wafer state. The semiconductor chip 100, the redistribution metal pattern 140, and the insulating layers 131 and 132 may be packaged in the semiconductor chip 100.

반도체 칩(100)의 부착이 완료되면, 반도체 칩(100)의 주위와 히트 스프레더(120,120') 사이의 공간을 제1 절연층(131)으로 도포하여 절연한다. 제1 절연층(131)은 증착 또는 스핀 코팅(spin coating) 등의 방법으로 도포될 수 있다. 제1 절연층(131)은 외부의 응력(stress) 및 전기적 노이즈로부터 반도체 칩(100)을 방어하기 위하여, 충분한 탄성과 전기적 절연성을 갖는 폴리머로 형성되는 것이 바람직하다. 제1 절연층(131)의 도포가 완료되면 일반적인 포토리토그래피 및 에칭 공정을 이용하여 반도체 칩(100)의 패드(160)를 오픈한다.When the attachment of the semiconductor chip 100 is completed, a space between the periphery of the semiconductor chip 100 and the heat spreaders 120 and 120 ′ is applied by the first insulating layer 131 to insulate the semiconductor chip 100. The first insulating layer 131 may be applied by a method such as deposition or spin coating. The first insulating layer 131 is preferably formed of a polymer having sufficient elasticity and electrical insulation in order to protect the semiconductor chip 100 from external stress and electrical noise. When the application of the first insulating layer 131 is completed, the pad 160 of the semiconductor chip 100 is opened using a general photolithography and etching process.

다음으로, 일 단부가 상기 패드(160)와 연결되고 타 단부는 솔더 볼(150)과 연결되는 재배선용 금속 패턴(140)을 형성한다. 재배선용 금속 패턴(140)은 서로 다른 위치에 있는 반도체 칩(100)의 패드(160)와 패키지의 솔더 볼(150)을 연결하여 팬 아웃 구조를 획득하기 위한 금속 배선이다. 재배선용 금속 패턴(140)은 도금 또는 증착에 의하여 형성된 다음 에칭 공정에 의하여 소정의 형상으로 패터닝될 수 있다. Next, one end is connected to the pad 160 and the other end forms a redistribution metal pattern 140 connected to the solder ball 150. The redistribution metal pattern 140 is a metal wire for connecting the pad 160 of the semiconductor chip 100 and the solder balls 150 of the package at different positions to obtain a fan out structure. The redistribution metal pattern 140 may be formed by plating or deposition and then patterned into a predetermined shape by an etching process.

재배선용 금속 패턴(140)은 제2 절연층(132)에 의하여 도포된다. 제2 절연층(132)은 재배선용 금속 패턴(140)을 외부에서 작용하는 응력(stress) 및 전기적 노이즈로부터 보호하는 수단이 되며 솔더 볼(150)의 형성을 위한 솔더 마스크가 된다. 제1 절연층(131)과 마찬가지로 제2 절연층(132)은, 충분한 탄성과 전기적 절연성을 갖는 폴리머로 형성될 수 있다. 패드(160), 재배선용 금속 패턴(140) 및 솔더 볼(150)의 연결을 위하여 제1 절연층(131) 및 제2 절연층(132)이 부분적으로 관통 되므로, 제1 절연층(131) 및 제2 절연층(132)은 노광과 에칭에 의하여 패터닝될 수 있는 재질인 것이 바람직하다.The redistribution metal pattern 140 is applied by the second insulating layer 132. The second insulating layer 132 serves as a means for protecting the redistribution metal pattern 140 from stress and electrical noise acting from the outside and serves as a solder mask for forming the solder balls 150. Like the first insulating layer 131, the second insulating layer 132 may be formed of a polymer having sufficient elasticity and electrical insulation. Since the first insulating layer 131 and the second insulating layer 132 are partially penetrated to connect the pad 160, the redistribution metal pattern 140, and the solder ball 150, the first insulating layer 131. And the second insulating layer 132 is preferably a material that can be patterned by exposure and etching.

다음으로 제2 절연층(132)에 대하여 솔더 볼(150)이 형성될 부분을 오픈시키고 솔더 볼(150)을 정해진 위치에 배치하며 이를 리플로우(reflow)하여 솔더 볼(150)을 고정시킨다. 패키지가 팬 아웃 타입이며 솔더 볼(150)은 반도체 칩(100)의 면적에 해당하는 영역은 물론 반도체 칩(100)을 벗어난 영역에 걸쳐 마련될 수 있으므로, 칩 소형화에 따른 솔더 볼(150)의 개수 제한을 극복할 수 있다.Next, the part where the solder ball 150 is to be formed with respect to the second insulating layer 132 is opened, the solder ball 150 is disposed at a predetermined position, and the solder ball 150 is reflowed to fix the solder ball 150. Since the package is a fan-out type and the solder ball 150 may be provided not only in the area corresponding to the area of the semiconductor chip 100 but also in an area outside the semiconductor chip 100, the solder ball 150 may be formed according to the miniaturization of the chip. The number limit can be overcome.

도 6은 본 발명에 따른 반도체 패키지가 인쇄회로기판(180)에 실장된 상태를 도시한 단면도이다. 반도체 패키지의 솔더 볼(150)은 인쇄회로기판(180)의 소정 위치에 솔더링되며, 인쇄회로기판(180)의 솔더 볼(150')은 또 다른 인쇄회로기판(미도시)의 회로 패턴과 연결될 수 있다. 도시하지는 않았지만, 반도체 칩(100) 또는 재배선용 금속 패턴(140)의 그라운드는 금속 재질로 된 히트 스프레더(120,120')에 연결되고 히트 스프레더(120,120')는 반도체 패키지가 장착될 인쇄회로기판(180)의 그라운드 단자(미도시)에 연결됨으로써 노이즈를 효과적으로 억제할 수 있다. 6 is a cross-sectional view illustrating a state in which a semiconductor package according to the present invention is mounted on a printed circuit board 180. The solder ball 150 of the semiconductor package is soldered to a predetermined position of the printed circuit board 180, and the solder ball 150 ′ of the printed circuit board 180 may be connected to a circuit pattern of another printed circuit board (not shown). Can be. Although not shown, the ground of the semiconductor chip 100 or the redistribution metal pattern 140 is connected to the heat spreaders 120 and 120 'made of a metal material, and the heat spreaders 120 and 120' are mounted on the printed circuit board 180 on which the semiconductor package is mounted. Noise can be effectively suppressed by being connected to the ground terminal (not shown).

상술한 바와 같이 본 발명의 반도체 패키지에 따르면, 칩 면적 이외의 팬 아웃 영역에 솔더 볼을 형성할 수 있으므로 입출력을 위한 솔더 볼의 개수에 제한을 받지 않고, 종래의 봉지재 대신에 금속 재질로 된 히트 스프레더에 반도체 칩이 직접 부착되므로 방열 특성 및 패키지의 소형화에 유리하며, 히트 스프레더가 반도체 칩의 그라운드 배선과 연결되므로 전기적 노이즈 제거에 효과적이다. As described above, according to the semiconductor package of the present invention, since solder balls can be formed in a fan-out area other than the chip area, the number of solder balls for input / output is not limited, and a metal material is used instead of a conventional encapsulant. Since the semiconductor chip is directly attached to the heat spreader, it is advantageous for heat dissipation and miniaturization of the package. Since the heat spreader is connected to the ground wire of the semiconductor chip, it is effective for removing electrical noise.

본 발명은 도면에 도시된 실시예를 참고로 하여 설명되었으나, 이는 예시적인 것에 불과하며, 당해 기술이 속하는 분야에서 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타 실시예가 가능하다는 점을 이해할 것이다. 따라서, 본 발명의 진정한 기술적 보호범위는 아래의 특허청구범위에 의해서 정하여져야 할 것이다. Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art to which the art belongs can make various modifications and other equivalent embodiments therefrom. Will understand. Therefore, the true technical protection scope of the present invention will be defined by the claims below.

Claims (7)

패드가 형성된 반도체 칩;A semiconductor chip in which pads are formed; 상기 패드를 솔더 볼과 연결하는 재배선용 금속 패턴;A redistribution metal pattern connecting the pad to the solder balls; 상기 반도체 칩이 부착되는 히트 스프레더;A heat spreader to which the semiconductor chip is attached; 상기 히트 스프레더 상에 적층되며 상기 반도체 칩을 밀봉하고 상기 재배선용 금속 패턴이 배치되며 상기 솔더 볼이 형성되는 절연층; 을 포함하며,An insulating layer stacked on the heat spreader and sealing the semiconductor chip, the metal pattern for redistribution is disposed, and the solder balls are formed; Including; 팬 아웃 구조를 위하여 상기 히트 스프레더의 면적 및 상기 솔더 볼이 배치되는 면적은 상기 반도체 칩의 면적보다 넓고, 상기 히트 스프레더가 금속 재질로 된 것을 특징으로 하는 반도체 패키지.The area of the heat spreader and the area where the solder ball is disposed for the fan out structure is larger than the area of the semiconductor chip, wherein the heat spreader is made of a metal material. 제1항에 있어서,The method of claim 1, 상기 히트 스프레더는 상기 반도체 칩의 그라운드 배선과 연결되는 것을 특징으로 하는 반도체 패키지.The heat spreader is connected to the ground wiring of the semiconductor chip. 제2항에 있어서,The method of claim 2, 상기 히트 스프레더는 상기 반도체 칩이 삽입 및 부착되는 함몰부를 구비하는 것을 특징으로 하는 반도체 패키지.The heat spreader has a recess in which the semiconductor chip is inserted and attached. 제2항에 있어서,The method of claim 2, 상기 히트 스프레더는 평판 형상인 것을 특징으로 하는 반도체 패키지.The heat spreader is a semiconductor package, characterized in that the flat shape. 제2항에 있어서,The method of claim 2, 상기 패드가 형성되는 면의 반대 면에 해당하는 상기 반도체 칩의 배면을 상기 히트 스프레더에 부착시키는 것으로 상기 절연층으로 밀봉되는 접착 부재; 를 더 포함하는 것을 특징으로 하는 반도체 패키지.An adhesive member sealed by the insulating layer by attaching a rear surface of the semiconductor chip corresponding to a surface opposite to a surface on which the pad is formed to the heat spreader; The semiconductor package further comprises. 제2항에 있어서,The method of claim 2, 상기 절연층은 상기 반도체 칩을 밀봉하는 제1 절연층 및 상기 솔더 볼이 형성되는 제2 절연층을 구비하고,The insulating layer includes a first insulating layer sealing the semiconductor chip and a second insulating layer on which the solder balls are formed, 상기 제1 절연층 중 상기 패드에 대응되는 부분이 오픈되며 상기 재배선용 금속 패턴의 일단부와 연결되고,A portion corresponding to the pad of the first insulating layer is opened and is connected to one end of the redistribution metal pattern; 상기 제2 절연층 중 상기 솔더 볼에 대응되는 부분이 오픈되며 상기 재배선용 금속 패턴의 타단부와 연결되는 것을 특징으로 하는 반도체 패키지.A portion of the second insulating layer corresponding to the solder ball is opened and is connected to the other end of the metal pattern for the redistribution. 제1항 내지 제6항 중 어느 한 항에 있어서,The method according to any one of claims 1 to 6, 상기 히트 스프레더가 웨이퍼 상태에서 상기 반도체 칩, 재배선용 금속 패턴, 절연층이 패키징되는 것을 특징으로 하는 반도체 패키지.And the semiconductor chip, a redistribution metal pattern, and an insulating layer are packaged while the heat spreader is in a wafer state.
KR1020070049325A 2007-05-21 2007-05-21 Semiconductor package including a heat spreader KR20080102641A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013010352A1 (en) * 2011-07-18 2013-01-24 江阴长电先进封装有限公司 Method for packaging low-k chip
US9905436B2 (en) 2015-09-24 2018-02-27 Sts Semiconductor & Telecommunications Co., Ltd. Wafer level fan-out package and method for manufacturing the same
CN110648924A (en) * 2019-09-04 2020-01-03 广东芯华微电子技术有限公司 Large-board fan-out type chip packaging structure and manufacturing method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013010352A1 (en) * 2011-07-18 2013-01-24 江阴长电先进封装有限公司 Method for packaging low-k chip
US8987055B2 (en) 2011-07-18 2015-03-24 Jiangyin Changdian Advanced Packaging Co., Ltd Method for packaging low-K chip
US9905436B2 (en) 2015-09-24 2018-02-27 Sts Semiconductor & Telecommunications Co., Ltd. Wafer level fan-out package and method for manufacturing the same
CN110648924A (en) * 2019-09-04 2020-01-03 广东芯华微电子技术有限公司 Large-board fan-out type chip packaging structure and manufacturing method thereof

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