KR20080101582A - Liquid crystal display device - Google Patents

Abstract

A liquid crystal display device is provided to improve the viewing angle by forming charge sharing capacitor without adding an additional process. A first and a second gate lines(GL(i), GL(i+1)) are formed on the insulating substrate to the first direction. A data line(DL(j)) is insulated with the first and the second gate line, and intersects with those lines. A pixel electrode including the first and the second sub-pixel electrode is electrically separated in each pixel region in which the first and the second gate line and data line intersect and defined. A first thin film transistor(T1) is connected to the first gate line, the data line, and the first sub-pixel electrode. A second thin film transistor(T2) is connected to the first gate line, the data line, and the second sub-pixel electrode. A third thin film transistor is connected to the charge sharing capacitor sharing data voltage which is connected to the second gate line, the first sub-pixel electrode, and the second sub-pixel electrode.

Description

Liquid crystal display device

1 is a circuit diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a layout view of a lower panel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a cross-sectional view of the lower panel of FIG. 2 taken along line III-III '.

4 is a cross-sectional view of the lower panel of FIG. 2 taken along line IV-IV '.

5 is a layout view of an upper panel of a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a layout view of a liquid crystal display including the lower panel of FIG. 2 and the upper panel of FIG. 5.

FIG. 7 is a cross-sectional view of the liquid crystal display of FIG. 6 taken along the line 'VIII'.

8 is a layout view of a lower panel of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 9 is a cross-sectional view of the lower panel of FIG. 8 taken along the line 'VIII'.

(Explanation of symbols for the main parts of the drawing)

10: insulation substrate 21a, 21c: gate line

26a and 26c: gate electrode 27: storage line

30: gate insulating film 40a, 40c: semiconductor layer

55a, 56a: ohmic contact layers 65a, 65b, 65c: source electrode

66a, 66b, 66c: drain electrode 67a, 67b: drain electrode extension

70: protective film 75: organic film

76a, 76b, and 76c: contact hole 82a: first subpixel electrode

82b: second subpixel electrode 90: common electrode

92 second domain dividing means 94 black matrix

98: color filter

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device that can improve visibility.

In the liquid crystal display, a liquid crystal layer is interposed between an upper display panel on which a common electrode and a color filter are formed, and a lower display panel on which a switching element and a pixel electrode are formed. By applying different potentials, an electric field is formed to change the arrangement of the liquid crystal molecules, thereby controlling the light transmittance to represent an image.

In addition, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field is applied, and thus the display panel has a high contrast ratio and is easy to implement a wide reference viewing angle. Here, the reference viewing angle refers to a viewing angle having a contrast ratio of 1:10 or a luminance inversion limit angle between gray levels.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming cutouts in the pixel electrode and the common electrode, and a method of forming protrusions on the field generating electrode. Since the inclination and the projection can determine the direction in which the liquid crystal molecules are tilted, the reference viewing angle can be widened by using these to disperse the oblique directions of the liquid crystal molecules in various directions.

However, the liquid crystal display of the vertical alignment type has a problem in that the side visibility is inferior to the front visibility. For example, in the case of a patterned vertically aligned (PVA) type liquid crystal display device having an incision, the image becomes brighter toward the side, and in a severe case, the luminance difference between the high grays disappears and the picture may appear clumped.

An object of the present invention is to provide a liquid crystal display device capable of improving visibility.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an exemplary embodiment of the present invention, a liquid crystal display according to an embodiment of the present invention may include data intersecting and intersecting first and second gate lines and first and second gate lines formed in a first direction on an insulating substrate. A pixel electrode including first and second subpixel electrodes electrically separated from each other in a pixel region defined by a line, the first and second gate lines and a data line intersecting each other, the first gate line, the data line, A first thin film transistor connected to the first subpixel electrode, the first gate line, the data line, a second thin film transistor connected to the second subpixel electrode and the second gate line, the first subpixel electrode, and the And a third thin film transistor connected to a second subpixel electrode and connected to a charge sharing capacitor sharing a data voltage applied to the first subpixel electrode.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a circuit diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

1, a liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of gate lines GL (i) and GL (i + 1) and a gate line GL (i) that transmit a gate signal. And a plurality of data lines DL (j) formed to intersect GL (i + 1) and transferring data signals.

The first thin film transistor T1 and the second thin film transistor T2 are formed at the intersection of the i-th gate line GL (i) and the j-th data line DL (j), and (i + 1) The third thin film transistor T3 is formed at the intersection of the first gate line GL (i + 1) and the jth data line DL (j).

That is, the first thin film transistor T1 includes a gate electrode connected to the i-th gate line GL (i), a source electrode connected to the j-th data DL (j), a first storage capacitor Cst1 and a first electrode. 1 includes a drain electrode connected to the liquid crystal capacitor Clc1. The second thin film transistor T2 includes a gate electrode connected to the i-th gate line GL (i), a source electrode connected to the j-th data DL (j), a second storage capacitor Cst2 and a second liquid crystal. And a drain electrode connected to the capacitor Clc2. The third thin film transistor T3 includes a gate electrode connected to the (i + 1) th gate line GL (i + 1), a source electrode connected to the drain electrode of the first thin film transistor T1, and a third storage capacitor. And a drain electrode connected to Cst3 and the charge sharing capacitor Ccs. Here, one side of the charge sharing capacitor Ccs is connected to the drain electrode of the second thin film transistor T2, and the other side thereof is connected to the drain electrode of the third thin film transistor T3.

The first storage capacitor Cst1 is formed of a dielectric material interposed between and between the first subpixel electrode and the storage line 27. The first liquid crystal capacitor Clc1 includes a first subpixel electrode connected to the first thin film transistor T1, a common electrode, and a liquid crystal material interposed therebetween.

The second storage capacitor Cst2 is formed of a dielectric material interposed between and between the second subpixel electrode and the storage line 27. The second liquid crystal capacitor Clc2 is formed of a second subpixel electrode connected to the second thin film transistor T2, a common electrode, and a liquid crystal material interposed therebetween.

The third storage capacitor Cst3 is formed of the storage line 27, the third drain electrode extension, and a dielectric material interposed therebetween. The charge sharing capacitor Ccs is formed of a dielectric material interposed between the third drain electrode extension and the second subpixel electrode.

Hereinafter, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 2 to 7. The liquid crystal display according to the present exemplary embodiment includes a lower panel, an upper panel facing the panel, and a liquid crystal layer interposed therebetween.

First, the lower panel of the liquid crystal display according to the exemplary embodiment will be described with reference to FIGS. 2 to 4. 2 is a layout view of a lower panel of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 3 is a cross-sectional view of the lower panel of FIG. 2 taken along line III-III ′, and FIG. 4 is a view of the lower panel of FIG. 2. This is a cross-sectional view taken along line IV-IV '.

Gate lines 21a and 21c are formed on the insulating substrate 10 in a first direction, for example, in a horizontal direction. First and second gate electrodes 26a and 26c having protrusions are formed on the gate lines 21a and 21c. The gate lines 21a and 21c and the gate electrodes 26a and 26c are called gate wirings.

The storage line 27 is formed in the horizontal direction along the gate lines 21a and 21c on the insulating substrate 10. The storage line 27 may include a storage electrode 28 having protrusions formed thereon and overlap the first subpixel electrode 82a and the second subpixel electrode 82b. However, the shape and arrangement of the storage line 27 may be modified in various forms. The common voltage Vcom may be applied to the storage line 27.

The gate wirings 21a, 21c, 26a, and 26c and the storage lines 27 include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper (Cu) and copper It may be made of a copper-based metal such as an alloy, molybdenum-based metal such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta). In addition, the gate lines 21a, 21c, 26a, and 26c and the storage line 27 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive films is a low resistivity metal such as an aluminum-based metal or a silver-based metal so as to reduce the signal delay or voltage drop of the gate wirings 21a, 21c, 26a, and 26c and the storage line 27. And copper-based metals. In contrast, the other conductive layer is made of a material having excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metals, chromium, titanium, tantalum and the like. A good example of such a combination is a chromium bottom film and an aluminum top film and an aluminum bottom film and a molybdenum top film. However, the present invention is not limited thereto, and the gate lines 21a, 21c, 26a, and 26c and the storage line 27 may be made of various metals and conductors.

The gate insulating film 30 is formed on the gate wirings 21a, 21c, 26a, and 26c and the storage line 27.

The semiconductor layers 40a and 40c made of hydrogenated amorphous silicon, polycrystalline silicon, or the like are formed on the gate insulating film 30. The semiconductor layers 40a and 40c may have various shapes, such as islands and linear shapes. For example, the semiconductor layers 40a and 40c may be formed in island shapes as in the present embodiment. In addition, when the semiconductor layers 40a and 40c are linearly formed, the semiconductor layers 40a and 40c may be disposed below the data line 61 and may extend to the upper portions of the gate electrodes 26a and 26c.

On the semiconductor layers 40a and 40c, ohmic contact layers 55a and 56a made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed. The ohmic contact layers 55a and 56a may have various shapes such as island shape and linear shape. For example, as in the present embodiment, the island type ohmic contact layers 55a and 56a may include the first source electrode 65a and the first source electrode 65a and 56a. Located below the first drain electrode 66a, the linear ohmic contact layers 55a and 56a may extend below the data line 61.

The data line 61, the first drain electrode 66a, the second drain electrode 66b, and the third drain electrode 66c are formed on the ohmic contact layers 55a and 56a and the gate insulating layer 30. The data line 61 extends in a second direction, for example, a vertical direction, and defines a pixel by crossing the gate lines 21a and 21c. The first source electrode 65a and the second source electrode 65b extending from the data line 61 to the upper portion of the first gate electrode 26a in a branch form are formed. The first drain electrode 66a is separated from the first source electrode 65a and positioned on the semiconductor layer 40a so as to face the first source electrode 65a with respect to the first gate electrode 26a. The second drain electrode 66b is separated from the second source electrode 65b and positioned on the semiconductor layer so as to face the second source electrode 65b with respect to the first gate electrode 26a. The first drain electrode 66a and the second drain electrode 66b have a rod-shaped pattern on the semiconductor layer 40a and a large area extending from the rod-shaped pattern and having a large area and having a first contact hole 76a and a second contact hole. Drain electrode extensions 67a and 67b on which 76b is located. The first contact hole 76a and the second contact hole 76b may be formed to overlap the first subpixel electrode 82a and the second subpixel electrode 82b, respectively.

The third source electrode 65c extends from the upper portion of the second gate electrode 26c to overlap the storage line 27 and the first subpixel electrode 82a, and the third drain electrode 66c extends the second gate. It extends from the upper part of the electrode 26c to overlap with the 1st and 2nd subpixel electrodes 82a and 82b. The third drain electrode 66c is separated from the third source electrode 65c and positioned above the semiconductor layer 40c to face the third source electrode 65c with respect to the second gate electrode 26c.

The data line 61, the first source electrode 65a, the second source electrode 65b, the third source electrode 65c, the first drain electrode 66a, the second drain electrode 66b, and the third drain The electrode 66c is called data wiring.

The data wirings 61, 65a, 65b, 65c, 66a, 66b, and 66c are preferably made of refractory metals such as chromium, molybdenum-based metals, tantalum and titanium, and a lower layer (not shown) such as refractory metals and the like. It may have a multi-layer structure consisting of a low-resistance material upper layer (not shown) located. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

At least a portion of the first source electrode 65a overlaps the semiconductor layer 40a, and the first drain electrode 66a faces the first source electrode 65a around the first gate electrode 26a and is a semiconductor layer. And at least a portion overlap. The ohmic contact layers 55a and 56a are interposed between the semiconductor layer 40a and the first source electrode 65a and the semiconductor layer 40a and the first drain electrode 66a to lower contact resistance therebetween. Do it.

In addition, at least a portion of the second source electrode 65b overlaps with the semiconductor layer 40a, and the second drain electrode 66b faces the second source electrode 65b around the second gate electrode 26c and is semiconductor. At least a portion overlaps with the layer. Here, the ohmic contact layer is interposed between the semiconductor layer and the second source electrode 65b and the semiconductor layer and the second drain electrode 66b to lower the contact resistance therebetween.

A protective film 70 made of an insulating film is formed on the data wirings 61, 65a, 65b, 65c, 66a, 66b, and 66c and the semiconductor layers 40a and 40c exposed thereby.

The organic layer 75 is formed on the passivation layer 70.

Here, the protective film 70 may be formed of an inorganic material made of silicon nitride or silicon oxide, the organic film 75 is an organic material or plasma enhanced chemical vapor deposition (PECVD) having excellent planarization characteristics and photosensitivity Low dielectric constant insulating materials such as a-Si: C: O and a-Si: O: F.

The organic layer 75 is provided with a first contact hole 76a and a second contact hole 76b exposing the first drain electrode extension 67a and the second drain electrode extension 67b, respectively.

On the organic layer 75, pixel electrodes 82a and 82b which are substantially long in the vertical direction and generally rectangular in the shape of the pixel are formed. The pixel electrodes 82a and 82b may include a first subpixel electrode 82a and a second contact hole connected to the first drain electrode 66a and the third source electrode 65c through the first contact hole 76a. The second subpixel electrode 82b is connected to the second drain electrode 66b through the 76b. Here, the first subpixel electrode 82a and the second subpixel electrode 82b may be made of a transparent conductor such as ITO or IZO or a reflective conductor such as aluminum.

The first subpixel electrode 82a and the second subpixel electrode 82b have the first drain electrode 66a and the third source electrode 65c through the first contact hole 76a and the second contact hole 76b, respectively. ) And the second drain electrode 66b are physically and electrically connected to each other to receive a data voltage from the first drain electrode 66a and the second drain electrode 66b. In the present exemplary embodiment, since the first source electrode 65a and the second source electrode 65b for transmitting the data voltage are respectively connected to the first drain electrode 66a and the second drain electrode 66b, the first subpixel is connected. Substantially the same data voltage is applied from the data line 61 to the electrode 82a and the second subpixel electrode 82b.

The first subpixel electrode 82a and the second subpixel electrode 82b to which the data voltage is applied generate an electric field together with the common electrode of the upper panel, thereby forming the electric field between the first subpixel electrode 82a and the common electrode and between the second and second electrodes. The arrangement of the liquid crystal molecules of the liquid crystal layer positioned between the subpixel electrode 82b and the common electrode is determined.

The first subpixel electrode 82a and the second subpixel electrode 82b constituting one pixel area are separated from each other with a predetermined gap 83 therebetween, and the outer boundary thereof is approximately in the vertical direction. It is a long rectangle. The first subpixel electrode 82a has a rotated V shape and is disposed in the center of the pixel area. The second subpixel electrode 82b is formed at a portion of the rectangular pixel area except for the first subpixel electrode 82a. Here, the gap 83 includes a portion that is substantially 45 degrees and a portion that is -45 degrees with the transmission axis or the gate lines 21a and 21c of the polarizing plate. Therefore, the edges of the first subpixel electrode 82a and the second subpixel electrode 82b adjacent to the gap 83 are substantially -45 degrees or 45 degrees (hereinafter, referred to as the transmission axis or gate lines 21a and 21c of the polarizing plate). , Oblique direction). The first subpixel electrode 82a and the second subpixel electrode 82b may have a first domain dividing means (not shown) such as a plurality of cutouts or protrusions in an oblique direction. The display regions of the pixel electrodes 82a and 82b are divided into a plurality of domains according to the direction in which the main directors of the liquid crystal molecules included in the liquid crystal layer are arranged when an electric field is applied. The gap 83 and the first domain dividing means serve to divide the pixel electrodes 82a and 82b into many domains. Here, the domain refers to an area formed of liquid crystal molecules in which the directors of the liquid crystal molecules are inclined in a specific direction by an electric field formed between the pixel electrodes 82a and 82b and the common electrode (see reference numeral 90 in FIG. 5). .

As described above, when the gate-on signal is applied to the first gate line 21a, the data voltage transferred from the data line 61 is transferred to the first subpixel electrode 82a and the second subpixel adjacent to the gate line 21a. It is applied to the electrode 82b. Here, assuming that the data voltage is 6.0V, it is applied to the first subpixel electrode 82a and the second subpixel electrode 82b of the data voltage of 6.0V, and one side of the charge sharing capacitor Ccs is the second drain. Since it is connected to the electrode 66b, the data voltage stored in the second subpixel electrode 82b is stored in the charge sharing capacitor Ccs.

Subsequently, when a gate-on signal is applied to the second gate line 21c, the data voltage stored in the first subpixel electrode 82a is distributed to the third drain electrode 66c through the third thin film transistor T3. As a result, a relatively low data voltage is stored in the first subpixel electrode 82a. At this time, since the third storage capacitor Cst3 and the charge sharing capacitor Ccs are connected to the third drain electrode 66c, charge sharing occurs and a data voltage is stored in the third storage capacitor Cst3. At the same time, the data voltage is also stored in the charge sharing capacitor Ccs. As a result, the second subpixel electrode 82b has a data voltage higher than the data voltage of 6.0V applied from the data line 61, for example, a data voltage of 7,0V. Therefore, in the present invention, visibility of the side surface can be improved by forming a charge sharing capacitor so as to generate a voltage difference between the first subpixel electrode and the second subpixel electrode by charge sharing.

An alignment film (not shown) capable of orienting the liquid crystal layer may be coated on the first subpixel electrode 82a, the second subpixel electrode 82b, and the organic layer 75.

Next, an upper panel and a liquid crystal display including the same will be described with reference to FIGS. 5 to 7. 5 is a layout view of an upper panel of the liquid crystal display according to an exemplary embodiment of the present invention. FIG. 6 is a layout view of a liquid crystal display including the lower panel of FIG. 2 and the upper panel of FIG. 5, and FIG. Is a cross-sectional view taken along the line VII-VII '.

A common electrode made of a black matrix 94 for preventing light leakage on the insulating substrate 96 made of transparent glass, a color filter 98 of red, green, and blue, and a transparent conductive material such as ITO or IZO. ) 90 is formed. Here, the black matrix 94 may have various shapes to block light leakage.

The common electrode 90 faces the first subpixel electrode 82a and the second subpixel electrode 82b and has a plurality of second domain dividing means 92. The second domain dividing means 92 may consist of an incision or a protrusion. Here, the second domain dividing means 92 includes an oblique portion that is substantially -45 degrees or 45 degrees with the transmission axes or the gate lines 21a and 21c of the polarizing plate. In the present embodiment, for convenience of description, the present invention will be described by using the second domain dividing means 92 having a cutout.

The oblique portions of the second domain dividing means 92 of the common electrode 90 are alternately arranged with the gap 83 between the first subpixel electrode Pa and the second subpixel electrode Pb.

An alignment layer (not shown) may be coated on the common electrode 90 to align the liquid crystal molecules of the liquid crystal layer 150.

When the lower display panel 100 and the upper display panel 200 having the above structure are aligned to each other and vertically aligned with a liquid crystal material interposed therebetween, a basic structure of the liquid crystal display device is provided. The liquid crystal display device is formed by disposing elements such as a polarizing plate and a backlight on the basic structure. At this time, one polarizing plate (not shown) is disposed on both sides of the basic structure, and the transmission axes thereof are arranged to be parallel to the gate lines 21a and 21c and the other one is perpendicular thereto. When the liquid crystal display device is formed as described above, when an electric field is applied to the liquid crystal, the liquid crystal in each domain is inclined in a direction perpendicular to the gap 83 or the second domain dividing means 92 for dividing the domain. . Therefore, the liquid crystal of each domain is inclined approximately 45 degrees or -45 degrees with respect to the transmission axis or gate lines 21a and 21c of the polarizing plate. A lateral field formed between the gap 83 or the second domain dividing means 92 assists the liquid crystal alignment of each domain.

In the above embodiment, a case where the third thin film transistor T3 is connected to the second gate line 21c has been described as an example, but the present invention is not limited thereto.

FIG. 8 is a layout view of a lower panel of a liquid crystal display according to another exemplary embodiment. FIG. 9 is a cross-sectional view of the lower panel of FIG. 8 taken along the line 'VIII'.

In the lower panel of the liquid crystal display according to another exemplary embodiment of the present invention, one storage line (see 27 in FIG. 2) is formed by separating the first to third storage electrodes 27a, 27b, and 27c, and the storage electrode. Except that the 27b is connected to the second subpixel electrode 82b through the third contact hole 76c, it is the same as the lower panel of the liquid crystal display according to the exemplary embodiment. Duplicate description with one embodiment of will be omitted.

First to third storage electrodes 27a, 27b, and 27c are formed on the insulating substrate 10 in the horizontal direction along the gate lines 21a and 21c. The first and second storage electrodes 27a and 27b may overlap the first subpixel electrode 82a, and the third storage electrode 27c may overlap the second subpixel electrode 82b. In this case, the common voltage Vcom may be applied to the first and third storage electrodes 27a and 27c, and the second storage electrode 27b may be in a floating state in which no voltage is applied.

As illustrated in FIG. 9, the third storage capacitor Cst3 includes the first story electrode 27a, the third drain electrode extension 68, and a dielectric material interposed therebetween. The charge sharing capacitor Ccs is formed of the second storage electrode 27b, the third drain electrode extension 68, and a dielectric material interposed therebetween. In this case, since the second storage electrode 27b is connected to the second subpixel electrode 82b through the third contact hole 76c, the voltage applied to the second subpixel electrode 82b is applied to the second storage electrode 27b. ) Is applied.

When the gate-on signal is applied to the first gate line 21a as in the exemplary embodiment of the present invention, the data voltage transferred from the data line 61 is transferred to the first subpixel electrode 82a adjacent to the gate line 21a and It is applied to the second subpixel electrode 82b. Here, assuming that the data voltage is 6.0V, it is applied to the first subpixel electrode 82a and the second subpixel electrode 82b of the data voltage of 6.0V, and one side of the charge sharing capacitor Ccs, that is, the second Since the storage electrode 27b is connected to the second subpixel electrode 82b, the data voltage stored in the second subpixel electrode 82b is stored in the charge sharing capacitor Ccs.

Subsequently, when a gate-on signal is applied to the second gate line 21c, the data voltage stored in the first subpixel electrode 82a is distributed to the third drain electrode 66c through the third thin film transistor T3. As a result, a relatively low data voltage is stored in the first subpixel electrode 82a. At this time, since the third storage capacitor Cst3 and the charge sharing capacitor Ccs are connected to the third drain electrode 66c, charge sharing occurs and a data voltage is stored in the third storage capacitor Cst3. At the same time, the data voltage is also stored in the charge sharing capacitor Ccs. As a result, the second subpixel electrode 82b has a data voltage higher than the data voltage of 6.0V applied from the data line 61, for example, a data voltage of 7,0V. Accordingly, another embodiment of the present invention forms a charge sharing capacitor to generate a voltage difference between the first subpixel electrode and the second subpixel electrode by charge sharing, so that the visibility of the side surface is the same as that of the embodiment of the present invention. Can improve.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

According to the liquid crystal display device according to the present invention as described above, it is possible to improve the visibility of the side by forming a charge sharing capacitor without additional process.

Claims (8)

First and second gate lines formed on the insulating substrate in a first direction; A data line insulated from and intersecting the first and second gate lines; A pixel electrode including first and second subpixel electrodes electrically separated from each other in each pixel area defined by the crossing of the first and second gate lines and the data line; A first thin film transistor connected to the first gate line, the data line, and the first subpixel electrode; A second thin film transistor connected to the first gate line, the data line, and the second subpixel electrode; And And a third thin film transistor connected to the second gate line, the first subpixel electrode, and the second subpixel electrode, and connected to a charge sharing capacitor sharing a data voltage applied to the first subpixel electrode. Device. The method of claim 1, Further comprising a storage line arranged side by side between the first and second gate line, The charge sharing capacitor of claim 3, wherein the drain electrode of the third thin film transistor and the second subpixel electrode overlap each other. The method of claim 1, And a same data voltage is applied to the first subpixel electrode and the second subpixel electrode from the data line. The method of claim 1, The data voltage applied to the first subpixel electrode is transferred to the charge sharing capacitor through the third thin film transistor. The method of claim 2, Further comprising first to third storage electrodes arranged side by side between the first and second gate lines and spaced apart from each other; The charge sharing capacitor of claim 2, wherein the second storage electrode and the drain electrode of the third thin film transistor overlap each other. The method of claim 5, wherein The second storage electrode is a floating electrode to which no voltage is applied. The method of claim 5, wherein And the second storage electrode and the second subpixel electrode are electrically connected to each other. The method of claim 1, And a data voltage stored at the second subpixel electrode is greater than a data voltage stored at the first subpixel electrode.

Images