KR20080095232A - Ferroelectric memory device and methods of manufacturing the same - Google Patents

Abstract

A ferroelectric memory device and a method of manufacturing the same are provided to improve polarization and to manufacture many memory cells on the same area. A ferroelectric memory device comprise a gate(21) formed on the upper part of substrate, a channel formation layer(22) on the gate, a ferroelectric layer(23) on the channel formation layer. The ferroelectric layer is composed of inorganic ferroelectric material or a mixture of its solid solution or an organic ferroelectric material.

Description

Ferroelectric memory device and methods of manufacturing the same

The present invention relates to a memory device using a ferroelectric and a method of manufacturing the same.

At present, memory devices are essentially adopted in most electronic devices including personal computers. These memory devices are mainly ROMs such as EPROM (Electrically Programmable Read Only Memory), EEPROM (Electrically Erasable PROM), Flash ROM (Flash ROM), Static Random Access Memory (SRAM), Dynamic RAM (DRAM), and Ferroelectric RAM (FRAM). RAM). These memory devices are usually made by forming a capacitor and a transistor on a semiconductor wafer such as silicon.

Conventional memory devices have been mainly studied for ways to increase the density of memory cells. However, in recent years, as the interest in non-volatile memory that can maintain stored data even when the power supply is cut off, a lot of researches on the use of ferroelectric material as a material of the memory device.

Currently, inorganic materials such as lead zirconate titanate (PZT), strontium bismuth tantalite (SBT), and lanthanum-substituted bismuth titanate (BLT) are mainly used as ferroelectric materials used in memory devices. However, in the case of such inorganic ferroelectric, its price is high, and the deterioration of polarity characteristics is caused over time, and high temperature treatment is required as well as expensive equipment is required.

In consideration of the above circumstances, the present applicant and the inventor have applied for a ferroelectric memory device using organic materials through Korean Patent Application Nos. 2005-0039167 and 2006-0003399 and 2006-0041814.

However, in the case of a memory device using an organic material, when the same memory structure is adopted, high integration is disadvantageous as compared with a conventional inorganic memory.

Accordingly, the present invention has been made in view of the above-described circumstances, and provides a memory device and a method of manufacturing the same, which are easy to manufacture, low cost, and have excellent polarity characteristics, and are capable of manufacturing a large number of memory cells in the same area. The purpose is to provide.

A ferroelectric memory device according to the first aspect of the present invention for realizing the above object is formed by stacking a plurality of memory cells on a substrate, the memory cell comprising a gate electrode, a drain and source electrode, a channel forming layer and a ferroelectric layer The ferroelectric layer is composed of a mixture of an inorganic ferroelectric material and an organic material, and a channel forming layer is formed between the gate electrode and the ferroelectric layer.

A ferroelectric memory device according to a second aspect of the present invention is formed by stacking a plurality of memory cells on a substrate, the memory cell comprising a gate electrode, a drain and source electrode, a channel forming layer and a ferroelectric layer, the ferroelectric The layer is composed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material, and a channel forming layer is formed between the gate electrode and the ferroelectric layer.

In addition, an insulating layer is formed between the memory cells, and the insulating layer is an organic material.

In addition, the stacked memory cells are characterized in that the ferroelectric layer is disposed adjacent to each other.

In addition, the stacked memory cells may have gate electrodes disposed adjacent to each other.

In addition, the ferroelectric memory device according to the third aspect of the present invention is formed by stacking a plurality of memory cells on a substrate, the memory cell comprises a gate electrode, a drain and source electrode, a channel forming layer and a ferroelectric layer, The ferroelectric layer is composed of a mixture of an inorganic ferroelectric material and an organic material, characterized in that the ferroelectric layer is formed between the gate electrode and the channel forming layer.

A ferroelectric memory device according to a fourth aspect of the present invention is formed by stacking a plurality of memory cells on a substrate, and the memory cell includes a gate electrode, a drain and a source electrode, a channel forming layer, and a ferroelectric layer. The layer is composed of a mixture of a solid solution of an inorganic ferroelectric material and an organic material, characterized in that a ferroelectric layer is formed between the gate electrode and the channel forming layer.

In addition, an insulating layer is formed between the memory cells, and the insulating layer is an organic material.

In addition, the stacked memory cells are characterized in that the ferroelectric layer is disposed adjacent to each other.

In addition, the stacked memory cells may have gate electrodes disposed adjacent to each other.

A method of manufacturing a ferroelectric memory device according to a fifth aspect of the present invention includes forming a first memory cell on a substrate, forming an insulating layer on the first memory cell, and forming a second memory cell on the insulating layer. And forming the first and second memory cells by forming a gate electrode, forming a channel forming layer, and using a mixture of an inorganic ferroelectric material and an organic material. And forming a drain and a source electrode.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a ferroelectric memory device, including forming a first memory cell on a substrate, forming an insulating layer on the first memory cell, and forming a second memory cell on the insulating layer. And forming the first and second memory cells by forming a gate electrode, forming a channel forming layer, and using a mixture of a solid solution of an inorganic ferroelectric material and an organic material. Forming a layer, and forming a drain and a source electrode.

The ferroelectric layer of the first memory cell and the second memory cell may be adjacent to each other.

The gate electrodes of the first memory cell and the second memory cell may be adjacent to each other.

In addition, the channel forming layer is formed between the gate electrode and the ferroelectric layer.

The ferroelectric layer may be formed between the gate electrode and the channel forming layer.

In a method of manufacturing a ferroelectric memory device according to a seventh aspect of the present invention, a plurality of memory cells are stacked on a substrate, and the memory cells include a gate electrode, a drain and a source electrode, a channel forming layer, and a ferroelectric layer. The ferroelectric layer of the stacked memory cell is composed of a mixture of inorganic ferroelectric materials and organic materials, and is composed of different ferroelectric materials, and a channel forming layer is formed between the gate electrode and the ferroelectric layer.

In a method of manufacturing a ferroelectric memory device according to an eighth aspect of the present invention, a plurality of memory cells are stacked on a substrate, and the memory cells include a gate electrode, a drain and a source electrode, a channel forming layer, and a ferroelectric layer. The ferroelectric layer of the stacked memory cell is composed of a mixture of inorganic ferroelectric materials and organic materials, and is composed of different ferroelectric materials, and a ferroelectric layer is formed between the gate electrode and the channel forming layer.

According to the present invention having the above-described configuration, a plurality of memory cells are formed by sequentially stacking a memory device having an inorganic ferroelectric material, a solid solution thereof, and an organic or organic ferroelectric material as a ferroelectric material, and sequentially stacking a 1T structure memory device using the ferroelectric material. Will be configured. Therefore, according to the present invention, a ferroelectric memory cell can be configured through a relatively low temperature process, and a plurality of memory cells can be configured for the same area.

Hereinafter, an embodiment according to the present invention will be described with reference to the drawings.

First, the basic concept of the present invention will be described.

Currently, various materials are known as ferroelectric properties. These substances are largely divided into inorganic and organic substances. Examples of the inorganic ferroelectric include oxide ferroelectrics, fluoride ferroelectrics such as BMF (BaMgF ₄ ), ferroelectric semiconductors, and the like, and polymer ferroelectrics as organic ferroelectrics.

As the oxide ferroelectric, for example, Pseudo-ilmenite ferroelectric such as Perovskite ferroelectric such as PZT (PbZr _x Ti _1-x O ₃ ), BaTiO ₃ , PbTiO ₃ , LiNbO ₃ , LiTaO _3, and the like , Tungsten-bronze (TB) ferroelectrics such as PbNb ₃ O ₆ , Ba ₂ NaNb ₅ O ₁₅ , SBT (SrBi ₂ Ta ₂ O ₉ ), BLT ((Bi, La) ₄ Ti ₃ O ₁₂ ), Bi ₄ Ti ₃ Ferroelectrics of bismuth layer structure such as O ₁₂ and Pyrochlore ferroelectrics such as La ₂ Ti ₂ O ₇ and solid solutions of these ferroelectrics, as well as Y, Er, Ho, Tm, Yb, Lu, etc. RMnO ₃ , PGO (Pb ₅ Ge ₃ O ₁₁ ), and BFO (BiFeO ₃ ) containing a rare earth element (R).

Examples of the ferroelectric semiconductors include Group 2-6 compounds such as CdZnTe, CdZnS, CdZnSe, CdMnS, CdFeS, CdMnSe, and CdFeSe.

As the polymer ferroelectric, for example, polyvinylidene fluoride (PVDF), a polymer, a copolymer, or a terpolymer containing the PVDF is included. In addition, an odd number of nylons, cyano polymers, polymers thereof and air Coalescing and the like.

In general, inorganic ferroelectrics such as oxide ferroelectrics, fluoride ferroelectrics, and ferroelectric semiconductors have a higher dielectric constant than organic ferroelectrics. Therefore, in the case of ferroelectric field effect transistors and ferroelectric memories, which are currently generally proposed, an inorganic ferroelectric is employed as a material of the ferroelectric layer.

However, in the case of the inorganic ferroelectric described above, a high temperature treatment of, for example, 500 degrees or more is required when forming it on a substrate. When the inorganic ferroelectric layer is formed on the silicon substrate through the high temperature treatment, a low quality transition layer is formed on the interface between the ferroelectric layer and the silicon substrate by high temperature, and elements such as Pb and Bi of the ferroelectric material are diffused on the silicon substrate. This causes a problem that the data holding time of the ferroelectric memory becomes very short.

In the present invention, a mixture of an inorganic ferroelectric material and an organic or organic ferroelectric material is used as the ferroelectric material.

According to the inventors' research, the inorganic ferroelectric material has a high dielectric constant while its formation temperature is high. In addition, the organic material including the organic ferroelectric material has a low dielectric constant while its formation temperature is very low. Therefore, when the inorganic ferroelectric material and the organic or organic ferroelectric material are mixed, the ferroelectric material having a very high dielectric constant and having a very low formation temperature can be obtained.

* As the method of mixing the inorganic ferroelectric material and organic or organic ferroelectric material may be used as follows.

1. After mixing inorganic powder and organic powder, dissolve it in solvent to produce mixed solution.

2. Dissolve organic powder in mineral solution to produce mixed solution.

3. Dissolve the inorganic powder in the organic solution to produce a mixed solution.

4. Mix the inorganic and organic solutions to form a mixed solution.

In addition, in the method of mixing the inorganic ferroelectric material and the organic material, it is possible to adopt the following method.

1. Mix ferroelectric minerals and organics.

2. Mix ferroelectric minerals with ferroelectric organics.

3. Mix solid solution of organic fertilizer with organic material.

4. Mix solid solution of ferroelectric mineral with ferroelectric organic material.

5. Mixing silicide, silicate or other metals into the mixture according to the first to fourth manners.

Of course, the mixing method and method of the said inorganic substance and organic substance are not limited to a specific thing, Any arbitrary method which can mix an inorganic substance and an organic substance suitably can be employ | adopted here.

In addition, as the organic material mixed with the ferroelectric inorganic material, a general monomer, oligomer, polymer, copolymer, preferably an organic material having a high dielectric constant may be used.

These materials include, for example, polyvinyl pyrrolidone (PVP), polycarbonate (PC), polyvinyl chloride (PVC), polystyrene (PS), epoxy (epoxy), polymethyl methacrylate (PMMA), polyimide (PE), poly (ethylene) (PE), and PVA ( polyvinyl alcohol), nylon 66 (polyhezamethylene adipamide), and PEKK (polytherketoneketone).

In addition, as the organic material, fluorinated para-xylene, fluoropolyarylether, fluorinated polyimide, polystyrene, poly (α-methyl styrene) (poly (α) -methyl styrene), poly (α-vinylnaphthalene), poly (vinyltoluene), polyethylene, cis-polybutadiene, poly Propylene, polyisoprene, poly (4-methyl-1-pentene), poly (tetrafluoroethylene), poly ( Chlorotrifluoroethylene (poly (chlorotrifluoroethylene), poly (2-methyl-1,3-butadiene) (poly (2-methyl-1,3-butadiene)), poly (p-xylylene) (poly ( p-xylylene)), poly (α-α-α'-α'-tetrafluoro-p-xylylene) (poly (α-α-α'-α'-tetrafluoro-p-xylylene)), poly [1,1- (2-methyl propane) bis (4-phenyl) carbonate] (poly [1,1- (2-methyl propane) bis (4-phenyl) carbonate]), poly (cyclohexyl methacrylate), poly (chlorostyrene), poly (2,6- Dimethyl-1,4-phenylene ether) (poly (2,6-dimethyl-1,4-phenylene ether)), polyisobutylene, poly (vinyl cyclohexane), Nonpolar organics such as poly (arylene ether) and polyphenylene, poly (ethylene / tetrafluoroethylene), poly (ethylene / chloro Poly (ethylene / chlorotrifluoroethylene), fluorinated ethylene / propylene copolymer, polystyrene-co-α-methyl styrene, ethylene / ethyl Ethylene / ethyl acrylate copolymer, poly (styrene / 10% butadiene) (poly (styrene / 10% butadiene), poly (styrene / 15% butadiene) (po ly (styrene / 15% butadiene), poly (styrene / 2,4-dimethylstyrene) (poly (styrene / 2,4-dimethylstyrene), Cytop, Teflon AF, polypropylene-co-1-butene (polypropylene-co- Low dielectric constant copolymers such as 1-butene) and the like can be used.

And other conjugated hydrocarbon polymers such as polyacene, polyphenylene, poly (phenylene vinylene), polyfluorene, and oligomers of such conjugated hydrocarbons. ; Condensed aromatic hydrocarbons such as anthracene, tetratracene, chrysene, pentacene, pyrene, perylene and coronene; oligomeric para substitutions such as p-quaterphenyl (p-4P), p-quinquephenyl (p-5P), p-sexiphenyl (p-6P) Oligomeric para substituted phenylenes; Poly (3-substituted thiophene), poly (3,4-bisubstituted thiophene), polybenzothiophene, poly Isotia naphthene (polyisothianaphthene), poly (N-substituted pyrrole), poly (3-substituted pyrrole), poly (3,4-disubstituted pyrrole) ) (poly (3,4-bisubstituted pyrrole)), polyfuran, polypyridine, poly-1,3,4-oxadiazoles, polyiso Polyisothianaphthene, poly (N-substituted aniline), poly (2-substituted aniline), poly (2-substituted aniline), poly (3-substituted aniline) (poly Conjugated heterocyclic polymers such as (3-substituted aniline), poly (2,3-bisubstituted aniline), polyazulene, polypyrene; Pyrazoline compounds; Polyselenophene; Polybenzofuran; Polyindole; Polypyridazine; Benzidine compounds; Stilbene compounds; Triazines; Substituted metallo- or metal-free porphines, phthalocyanines, fluorophthalocyanines, naphthalocyanines or fluoronaphthalocyanines; C ₆₀ and C ₇₀ fullerenes; N, N'-dialkyl, substituted dialkyl, diaryl or substituted diaryl-1,4,5,8-naphthalenetetracarboxylic diimide (N, N'-dialkyl, substituted dialkyl, diaryl or substituted diaryl-1,4,5,8-naphthalenetetracarboxylic diimide) and fluorinated derivatives; N, N'-dialkyl, substituted dialkyl, diaryl or substituted diaryl 3,4,9,10-perylenetetracarboxylic diimide (N, N'-dialkyl, substituted dialkyl, diaryl or substituted diaryl 3,4,9,10-perylenetetracarboxylic diimide); Bathophenanthroline; Diphenoquinones; 1,3,4-oxadiazoles (1,3,4-oxadiazoles); 11,11,12,12-tetracyanonaphtho-2,6-quinodimethane (11,11,12,12-tetracyanonaptho-2,6-quinodimethane); α, α'-bis (dithieno [3,2-b2 ', 3'-d] thiophene) (α, α'-bis (dithieno [3,2-b2', 3'-d] thiophene) ); 2,8-dialkyl, substituted dialkyl, diaryl or substituted diaryl anthrathiothiophenes (2,8-dialkyl, substituted dialkyl, diaryl or substituted diaryl anthradithiophene); Organic groups such as 2,2'-bibenzo [1,2-b: 4,5-b '] dithiophene (2,2'-bibenzo [1,2-b: 4,5-b'] dithiophene) Semi-conducting materials or their compounds, oligomers and compound derivatives can be used.

In the above manner, the mixing ratio of the inorganic material and the organic material can be appropriately set as necessary. If the mixing ratio of the ferroelectric inorganic material is increased, the dielectric constant of the mixture is increased while the formation temperature is high, and if the mixing ratio of the ferroelectric inorganic material is low, the dielectric constant of the mixture is low while the formation temperature is low.

The ferroelectric material according to the present invention has the following characteristics.

1. Since the ferroelectric layer is formed using a mixed solution of an inorganic material and an organic material, the ferroelectric layer can be easily formed using inkjet, spin coating, or screen printing.

2. As the formation temperature of the ferroelectric layer is lowered, field effect transistors or ferroelectric memories can be formed on various kinds of substrates such as organic materials or paper instead of the existing silicon substrates.

Meanwhile, FIGS. 1 to 5 illustrate ferroelectric layers formed by mixing inorganic ferroelectric materials and organic ferroelectric materials, for example, PZT (PbZr _x Ti _1-x O ₃ ) and PVDF-TrFE at a predetermined ratio, among ferroelectric materials according to the present invention. It is a graph which measured the polarization characteristic after that.

Here, the ferroelectric layer is mixed with the PZT solution and PVDF-TrFE solution in a constant ratio to generate a mixed solution, the mixed solution is applied on the silicon wafer by spin coating method, and then the silicon wafer is fixed on the hot plate for a predetermined time. It was formed by heating to about 150 ~ 200 degrees.

In addition, the PZT solution, for example, by mixing a zirconium propoxide solution with a mixed solution of 2-methoxyethanol solution and lead acetate trihydrate solution to produce a PZO solution Then, a titanium isopropoxide solution was mixed with a mixed solution of 2-methoxyethanol solution and lead acetate trihydrate solution to generate a PTO solution, and then a PZO solution and a PTO solution were mixed.

In addition, the PVDF-TrFE solution may contain PVDF-TrFE powders such as THF (C ₄ H ₅ O), MEK (C ₄ H ₈ O), Acetone (C ₃ H ₆ O), DMF (C ₃ H ₇ NO) It was produced by dissolving in a solvent such as (C ₂ H ₆ OS).

1 to 5, the mixing ratio of PZT and PVDF-TrFE is 1: 1, the mixing ratio of PZT and PVDF-TrFE is 2: 1, and the mixing ratio of PZT and PVDF-TrFE is 3: 1. 4 shows the polarization characteristics when the mixing ratio of PVDF-TrFE is 1: 2 and the mixing ratio of PVDF-TrFE is 1: 3.

1A, 2A and 3A show the thickness of the ferroelectric layer 50 nm, FIGS. 1B, 2B, 3B, 4 and 5 show the thickness of the ferroelectric layer 75 nm, and FIG. 1C shows the ferroelectric layer. The case where the film thickness is 100 nm is shown.

In addition, in the characteristic graphs indicated by A in FIGS. 1 to 5, the formation temperature of the ferroelectric layer is 190 degrees and the formation temperature of B is 170 degrees and the formation temperature of the ferroelectric layer is 150 degrees. The case is shown.

1 to 5, when the mixing ratio of PZT and PVDF-TrFE is 1: 1 or the mixing ratio of PVDF-TrFE is larger, the polarization characteristics are generally good at the formation temperature of 150 to 190 degrees, and the mixing ratio of PZT The higher is, the better the polarization characteristic is at the formation temperature.

In addition, as the thickness of the ferroelectric layer is increased, the polarization value, that is, the capacitance value is lowered, while the size of the memory window is increased.

In particular, it is noteworthy that even when the mixing ratio of PZT and PVDF-TrFE is changed or the formation temperature is set to a temperature of 200 degrees or less, very good hysteresis characteristics are exhibited.

As described above, in the case of the conventional inorganic ferroelectric material, since its formation temperature is high, various problems occur when it is formed on a silicon substrate. In contrast, the mixture of the inorganic ferroelectric material and the organic material according to the present invention can be formed at a low temperature of 200 degrees or less, and exhibits good hysteresis characteristics at a voltage between -5 and 5V. This means that the ferroelectric material according to the present invention can be usefully used as a material for ferroelectric field effect transistors or ferroelectric memories.

Hereinafter, the embodiment according to the present invention will be described in more detail.

6 is a structural diagram illustrating a structure of a ferroelectric memory device to which the ferroelectric material is applied.

In FIG. 6, a transistor or a memory cell 20 is formed on a substrate 10. Here, the substrate 10 is composed of a semiconductor substrate such as silicon, for example. In addition, the substrate 10 may be formed of an organic material such as paper, paper coated with a coding material such as parylene, or a plastic having flexibility. The organic materials usable here include polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyetheretherketone (PEEK), polybutylene terephthalate (PBT), polyethylene terephthalate (PET), polychlorinated Vinyl (PVC), Polyethylene (PE), Ethylene Copolymer, Polypropylene (PP), Propylene Copolymer, Poly (4-methyl-1-pentene) (TPX), Polyarylate (PAR), Polyacetal (POM) , Polyphenylene oxide (PPO), polysulfone (PSF), polyphenylene sulfide (PPS), polyvinylidene chloride (PVDC), polyvinyl acetate (PVAC), polyvinyl alcohol (PVAL), polyvinyl acetal, polystyrene (PS), AS resin, ABS resin, polymethyl methacrylate (PMMA), fluorine resin, phenol resin (PF), melamine resin (MF), urea resin (UF), unsaturated polyester (UP), epoxy resin ( EP), diallyl phthalate resin (DAP), polyurethane (PUR), polyamide (PA), silicone resin (SI) or mixtures and compounds thereof. Available.

The gate electrode 21 is formed as a lower electrode on the substrate 10 by a known method. In this case, the gate electrode 21 is based on gold, silver, aluminum, platinum, indium tin compound (ITO), strontium titanate compound (SrTiO ₃ ), other conductive metal oxides, alloys and compounds thereof, or conductive polymers. For example, a mixture such as polyaniline, poly (3,4-ethylenedioxythiophene) / polystyrenesulfonate (PEDOT: PSS), a compound, or a multilayered material is used.

Subsequently, for example, an organic semiconductor layer is formed as the channel forming layer 22 while coating the gate electrode 21 and the substrate 10 as a whole. Examples of the organic semiconductor layer include Cu-phthalocyanine, polyacetylene, merocyanine, polythiophene, phthalocyanine, and poly (3-hexylthiophene). (3-hexylthiophene)], poly (3-alkylthiophene) [Poly (3-alkylthiophene), α-sexithiophene, pentacene, α-ω-dihexyl-seccity Α-ω-dihexyl-sexithiophene, Polythienylenevinylene, Bis (dithienothiophene), α-ω-dihexyl-quaterthiophene, dihexyl-anthrathiity Difenxyl-anthradithiophene, α-ω-dihexyl-quinquethiophene, F8T2, Pc ₂ Lu, Pc ₂ Tm, C ₆₀ / C ₇₀ , TCNQ, C ₆₀ , PTCDI- Ph, TCNNQ, NTCDI, NTCDA, PTCDA, F16CuPc, NTCDI-C8F, DHF-6T, PTCDI-C8 and the like can be used.

As the channel forming layer 22, an inorganic semiconductor layer such as silicon may be used in addition to the organic material.

It is also possible to use an insulating layer as the channel forming layer 22. At this time, as the insulating layer, inorganic materials such as ZrO ₂ , SiO ₄ , Y ₂ O ₃ , CeO ₂ , or organic materials such as BCB, polyimide, acryl, parylene C, PMMA, CYPE, etc. Can be used.

The channel formation layer 22 is for channel formation of the ferroelectric memory device.

The ferroelectric layer 23 is formed in a region corresponding to the gate electrode 21 on the channel forming layer 22. In this case, as described above, the ferroelectric layer 23 is composed of an inorganic ferroelectric material, a solid solution thereof, and a mixture of organic or organic ferroelectric materials.

A drain electrode 24 and a source electrode 25 are formed on both side surfaces of the ferroelectric layer 23 as upper electrodes.

In this case, as the drain electrode 24 and the source electrode 25, gold, silver, aluminum, platinum, indium tin compound (ITO), strontium titanate compound (SrTiO ₃ ), other conductive metal oxides, and alloys thereof And materials such as polyaniline, poly (3,4-ethylenedioxythiophene) / polystyrenesulfonate (PEDOT: PSS), compounds, or multilayers based on the compound or conductive polymer.

In the above structure, the ferroelectric layer 23 has a polarization characteristic according to the voltage applied to the gate electrode 21. As a result, a predetermined channel is formed in the channel forming layer 22 due to the polarization characteristic of the ferroelectric layer 23, so that the drain electrode 24 and the source electrode 25 are set to the conductive or non-conductive state through the channel region. Will be.

In general, a commercially available memory device has a 1T-1C (One Transistor-One Capacitor) structure. In these memory devices, data is written to or read from a capacitor through a method of charging or discharging a predetermined voltage to the capacitor through on / off of a transistor.

In the above structure, the ferroelectric layer 23 has a predetermined polarization characteristic according to the voltage applied to the gate electrode 21, and this polarization characteristic is kept constant even when the voltage is cut off. Therefore, in the case of the memory device having the above-described structure, as shown in FIG. 7, the nonvolatile memory device has a simple 1T structure in which the source electrode of the ferroelectric memory device 40 is grounded and data is read through the drain electrode. You can configure it.

8 is a structural diagram showing the structure of a ferroelectric memory device according to the second embodiment of the present invention.

In FIG. 8, a first memory cell 80 is formed on the substrate 70, and an insulating layer 90, such as polyimide (PI), is formed on the first memory cell 80. The second memory cell 100 is again formed on the insulating layer 90.

The substrate 70 is composed of, for example, a semiconductor substrate such as silicon. In addition, the substrate 70 may be made of paper, a species coated with a coding material such as parylene, or an organic material such as a plastic having flexibility. The organic materials usable here include polyimide (PI), polycarbonate (PC), polyethersulfone (PES), polyetheretherketone (PEEK), polybutylene terephthalate (PBT), polyethylene terephthalate (PET), poly Vinyl chloride (PVC), polyethylene (PE), ethylene copolymer, polypropylene (PP), propylene copolymer, poly (4-methyl-1-pentene) (TPX), polyarylate (PAR), polyacetal (POM ), Polyphenylene oxide (PPO), polysulfone (PSF), polyphenylene sulfide (PPS), polyvinylidene chloride (PVDC), polyvinyl acetate (PVAC), polyvinyl alcohol (PVAL), polyvinyl acetal, Polystyrene (PS), AS resin, ABS resin, polymethyl methacrylate (PMMA), fluorocarbon resin, phenolic resin (PF), melamine resin (MF), urea resin (UF), unsaturated polyester (UP), epoxy resin (EP), diallyl phthalate resin (DAP), polyurethane (PUR), polyamide (PA), silicone resin (SI) or mixtures and compounds thereof It can be used.

Memory cells 80 and 100 are sequentially stacked on the substrate 70. In this embodiment, a case where two layers of memory cells are stacked on the substrate 70 is described as an example. However, the stack of such memory cells may be formed of two or more layers as necessary.

In the first memory cell 80, a gate electrode 81 is formed as a lower electrode, and a channel formation layer 82 is formed on the gate electrode 81. Subsequently, a ferroelectric layer 83 is formed in a region corresponding to the gate electrode 81 on the channel formation layer 82. At this time, the ferroelectric layer 83 is composed of a ferroelectric material, that is, an inorganic ferroelectric material or a mixture of organic or organic ferroelectric materials thereof. A drain electrode 84 and a source electrode 85 are formed on both side surfaces of the ferroelectric layer 83.

The second memory cell 100 has a structure substantially the same as that of the first memory cell 80. Like the first memory cell 80, the second memory cell 100 has a structure in which the gate electrode 101, the channel forming layer 102, and the ferroelectric layer 103 are sequentially stacked.

Like the first memory cell 80, the ferroelectric layer 103 of the second memory cell 100 is composed of an inorganic ferroelectric material, a solid solution thereof, and a mixture of organic or organic ferroelectric materials.

In particular, the material of the ferroelectric layers 83 and 103 may be appropriately used in some cases without having to be the same as each other. For example, the ferroelectric layer 83 may be composed of a mixture of inorganic ferroelectric materials and organic materials, and the ferroelectric layer 103 may be composed of a mixture of inorganic ferroelectric materials and organic ferroelectric materials.

That is, the ferroelectric layers 83 and 103 may be formed using any kind of ferroelectric mixture material provided in the present invention.

Examples of the gate electrodes 81 and 101 include gold, silver, aluminum, platinum, indium tin compound (ITO), strontium titanate compound (SrTiO ₃ ), other conductive metal oxides, alloys and compounds thereof, or conductive polymers. For example, a mixture such as polyaniline, poly (3,4-ethylenedioxythiophene) / polystyrenesulfonate (PEDOT: PSS), a compound, or a multilayered material may be used.

Examples of the channel forming layers 82 and 102 include Cu-phthalocyanine, polyacetylene, merocyanine, polythiophene, phthalocyanine, and poly (3-hexylthione). Offen) [Poly (3-hexylthiophene)], poly (3-alkylthiophene) [Poly (3-alkylthiophene), α-sexithiophene, pentacene, α-ω-di Hexyl-Sexythiophene (α-ω-dihexyl-sexithiophene), Polythienylenevinylene, Bis (dithienothiophene), α-ω-dihexyl-quaterthiophene, di Hexyl-anthradithiophene, α-ω-dihexyl-quinquethiophene, F8T2, Pc ₂ Lu, Pc ₂ Tm, C ₆₀ / C ₇₀ , TCNQ, C ₆₀ , PTCDI-Ph, TCNNQ, NTCDI, NTCDA, PTCDA, F16CuPc, NTCDI-C8F, DHF-6T, PTCDI-C8 and the like may be used.

It is also possible to use an insulating layer as the channel forming layers 82 and 102. At this time, as the insulating layer, inorganic materials such as ZrO ₂ , SiO ₄ , Y ₂ O ₃ , CeO ₂ , or organic materials such as BCB, polyimide, acryl, parylene C, PMMA, CYPE, etc. Can be used.

The channel forming layers 82 and 102 are for channel formation of the ferroelectric memory device.

The drain electrodes 84 and 104 and the source electrodes 85 and 105 are gold, silver, aluminum, platinum, indium tin compound (ITO), strontium titanate compound (SrTiO ₃ ), and other conductive metal oxides. And mixtures of compounds such as polyaniline, poly (3,4-ethylenedioxythiophene) / polystyrenesulfonate (PEDOT: PSS), compounds or multilayers based on conductive alloys and compounds or conductive polymers are used. do.

In the above structure, the ferroelectric layers 83 and 103 have polarization characteristics according to voltages applied to the gate electrodes 81 and 101. As a result, a predetermined channel is formed in the channel forming layers 82 and 102 due to the polarization characteristics of the ferroelectric layers 83 and 103, so that the drain electrodes 84 and 104 and the source electrodes 85 and 105 take up the channel region. Through or non-conductive state is set through.

Next, a manufacturing process of the ferroelectric memory device according to the present invention will be described with reference to FIG. 9.

A conductive layer 51 such as gold (Au), for example, is deposited on a substrate 70 such as a semiconductor wafer, paper, or a coding material such as parylene, or a plastic or the like (FIG. 9A and 9B). The photoresist 52 is apply | coated using spin coating method (FIG. 9C).

Subsequently, the photoresist 52 is removed except for only a portion for forming the gate electrode using a remover such as acetone, and the gate electrode 81 is formed by etching the conductive layer 51 using the mask as a mask. (FIG. 9D, FIG. 9E).

After removing the photoresist 52 on the gate electrode 81, a channel forming layer 82 is formed on the entire surface of the structure by spin coating (FIG. 9F), and spin coating is formed on the channel forming layer 82. The ferroelectric material solution according to the present invention is applied by a method, an inkjet printing method, or a screen printing method, and then fired at a low temperature of 200 degrees or less, for example, to form the ferroelectric layer 83.

The photoresist 53 is used to cope with the gate electrode 81, for example, by performing two-step etching of BOE (Buffered Oxide Etching), BOE and Gold etchant, or RIE (Reactive Ion Etching). After removing the remaining ferroelectric layer except for the portion (Figs. 9H to 9J). The photoresist 53 formed on the ferroelectric layer 83 is removed (FIG. 9K). Then, the photoresist 54 is applied on the ferroelectric layer 83 by the same method as described above, and the drain electrode 84 and the source electrode 85 are deposited by depositing a conductive layer made of, for example, gold entirely on the resultant. ), The photoresist 54 and the conductive layer 55 on the ferroelectric layer 83 are removed in a lift-off manner to form the first memory cell 80 (FIG. 9L). To 9o)

After forming the first memory cell 80 as described above, an insulating layer 90 such as polyimide (PI) is formed on the entire structure of the first memory cell 80, and the insulating layer 90 is formed. Flatten).

The second memory cell 100 is formed by repeatedly performing the processes of FIGS. 9A to 9O on the planarized insulating layer 90.

In the stacked structure, the gate electrode 101 of the second memory cell 100 is formed on the ferroelectric layer 83 of the first memory cell 80 through the insulating layer 90. Therefore, in this case, the ferroelectric layer 83 included in the first memory cell 80 is affected by the voltage applied to the gate electrode 101, thereby weakening data retention characteristics of the first memory cell 80. There is a possibility of becoming.

10 is a cross-sectional view illustrating a structure of a memory device according to another embodiment of the present invention in consideration of the above circumstances. In FIG. 10, the same parts as in FIG. 8 are given the same reference numerals, and detailed description thereof will be omitted.

In the structure shown in FIG. 10, the ferroelectric layer 103 is formed above the insulating layer 90 in the second memory cell 100. The channel forming layer 102 is formed while covering the ferroelectric layer 103 as a whole, and the gate electrode 101 is formed in a portion corresponding to the ferroelectric layer 103 on the channel forming layer 102.

In the second memory cell 100, the ferroelectric layer 103 has a polarization characteristic according to the voltage applied to the gate electrode 101, and a channel is formed in the channel formation layer 102 by this polarization value, thereby draining the drain electrode. 104 and the source electrode 105 are set to the conductive or non-conductive state through this channel region.

In the present embodiment, the ferroelectric layers 83 and 103 of the first memory cell 80 and the second memory cell 100 are disposed adjacent to each other through the insulating layer 90, and the respective gate electrodes 81 and 101 are disposed. Is positioned at the furthest position from other memory cells, so that the ferroelectric layer 83 of the first memory cell 80 is affected by the gate voltage of the second memory cell 100 unlike the above-described embodiment. Will be removed.

In the present embodiment, when the memory cells are stacked on the second memory cell 100 again, the gate electrode 81 is disposed below the second memory cell 100 like the first memory cell 80. And the gate electrode may be disposed adjacent to each other.

The embodiment according to the present invention has been described above. However, the above-described embodiment shows one preferred embodiment in implementing the present invention, and examples of such embodiments are not intended to limit the scope of the present invention. The present invention can be implemented in various modifications without departing from the basic concept and spirit thereof.

For example, in the above-described embodiment, the ferroelectric layers 83 and 103 are coupled to the gate electrodes 81 and 101 through the channel forming layers 82 and 102 as the structures of the respective memory cells 80 and 100. The case where is adopted is described as an example.

However, the ferroelectric memory device according to the present invention may be implemented by adopting various structures in addition to the memory cell structure described above.

For example, FIG. 11 shows various structural examples of memory cells applicable to the present invention.

In FIG. 11, the channel forming layer 22 is formed on the opposite side of the ferroelectric layer 23 facing the gate electrode 21 while directly coupling the gate electrode 21 and the ferroelectric layer 23. However, FIG. 11A shows a staggered structure, FIG. 11B shows an inverted staggered structure, FIG. 11C shows a coplanar structure, and FIG. 11D shows an inverted coplanar structure. It is shown. In Fig. 11, the same reference numerals are added to the corresponding parts in Fig. 6.

In the structure shown in FIG. 11, when a constant voltage is applied to the gate electrode 21, polarization occurs in the ferroelectric layer 23, so that a channel is formed in the channel forming layer 22. The drain electrode 24 and the source electrode 25 are set to the conductive state or the non-conductive state through the channel formed as described above.

In the structure of FIG. 11, an insulating layer may be used instead of the channel forming layer 22. That is, the channel forming layer 22 may be of any type that can form a channel according to the applied voltage.

1 to 5 is a characteristic graph showing the capacity characteristics according to the voltage of the ferroelectric material applied to the present invention.

6 is a structural diagram showing the structure of a ferroelectric memory device according to the first embodiment of the present invention;

FIG. 7 is a diagram showing an equivalent circuit configuration of the ferroelectric memory device shown in FIG.

8 is a structural diagram showing the structure of a ferroelectric memory device according to the second embodiment of the present invention;

9 is a view for explaining a manufacturing process of the ferroelectric memory device shown in FIG.

10 is a structural diagram showing a structure of a ferroelectric memory device according to a modification of the embodiment shown in FIG.

11 is a structural diagram showing another structural example of the ferroelectric memory device according to the present invention;

Claims (28)

Stacking a plurality of memory cells on a substrate, The memory cell includes a gate electrode, a drain and a source electrode, a channel forming layer, and a ferroelectric layer. The ferroelectric layer is composed of a mixture of inorganic ferroelectric materials and organic matter, And a channel forming layer is formed between the gate electrode and the ferroelectric layer. The method of claim 1, An insulating layer is formed between the memory cells, wherein the insulating layer is an organic material. The method of claim 1, The stacked memory cells are ferroelectric memory device, characterized in that the ferroelectric layer is disposed adjacent to each other. The method of claim 1, The stacked memory cells of the ferroelectric memory device, characterized in that the gate electrode is disposed adjacent to each other. Stacking a plurality of memory cells on a substrate, The memory cell includes a gate electrode, a drain and a source electrode, a channel forming layer, and a ferroelectric layer. The ferroelectric layer is composed of a mixture of an organic solid solution and a solid solution of inorganic ferroelectric material, And a channel forming layer is formed between the gate electrode and the ferroelectric layer. The method of claim 5, An insulating layer is formed between the memory cells, wherein the insulating layer is an organic material. The method of claim 5, The stacked memory cells are ferroelectric memory device, characterized in that the ferroelectric layer is disposed adjacent to each other. The method of claim 5, The stacked memory cells of the ferroelectric memory device, characterized in that the gate electrode is disposed adjacent to each other. Stacking a plurality of memory cells on a substrate, The memory cell includes a gate electrode, a drain and a source electrode, a channel forming layer, and a ferroelectric layer. The ferroelectric layer is composed of a mixture of inorganic ferroelectric materials and organic matter, A ferroelectric memory device, characterized in that a ferroelectric layer is formed between the gate electrode and the channel forming layer. The method of claim 9, The stacked memory cells are ferroelectric memory device, characterized in that the ferroelectric layer is disposed adjacent to each other. The method of claim 9, The stacked memory cells of the ferroelectric memory device, characterized in that the gate electrode is disposed adjacent to each other. Stacking a plurality of memory cells on a substrate, The memory cell includes a gate electrode, a drain and a source electrode, a channel forming layer, and a ferroelectric layer. The ferroelectric layer is composed of a mixture of organic solid solution and solid solution of inorganic ferroelectric material, A ferroelectric memory device, characterized in that a ferroelectric layer is formed between the gate electrode and the channel forming layer. The method of claim 12, An insulating layer is formed between the memory cells, wherein the insulating layer is an organic material. The method of claim 12, The stacked memory cells are ferroelectric memory device, characterized in that the ferroelectric layer is disposed adjacent to each other. The method of claim 12, The stacked memory cells of the ferroelectric memory device, characterized in that the gate electrode is disposed adjacent to each other. Forming a first memory cell on the substrate; Forming an insulating layer on the first memory cell, and And forming a second memory cell on the insulating layer, The forming of the first and second memory cells may include forming a gate electrode, forming a channel forming layer, forming a ferroelectric layer using a mixture of an inorganic ferroelectric material and an organic material, and drain and source electrodes. A method of manufacturing a ferroelectric memory device, characterized in that it comprises a step of forming a. The method of claim 16, And a ferroelectric layer of the first memory cell and the second memory cell adjacent to each other. The method of claim 16, And forming gate electrodes of the first memory cell and the second memory cell adjacent to each other. The method of claim 16, The channel forming layer is formed between the gate electrode and the ferroelectric layer. The method of claim 16, And manufacturing the ferroelectric layer between the gate electrode and the channel forming layer. The method of claim 16, And the ferroelectric layer is formed by applying a mixed solution of an inorganic ferroelectric material and an organic solution on a substrate to form a ferroelectric film, heating and baking the ferroelectric film, and then etching the ferroelectric memory device. Forming a first memory cell on the substrate; Forming an insulating layer on the first memory cell, and And forming a second memory cell on the insulating layer, The forming of the first and second memory cells may include forming a gate electrode, forming a channel forming layer, forming a ferroelectric layer using a mixture of an organic ferroelectric material and an organic material, and drain and A method for manufacturing a ferroelectric memory device, comprising the step of forming a source electrode. The method of claim 22, And a ferroelectric layer of the first memory cell and the second memory cell adjacent to each other. The method of claim 22, And forming gate electrodes of the first memory cell and the second memory cell adjacent to each other. The method of claim 22, The channel forming layer is formed between the gate electrode and the ferroelectric layer. The method of claim 22, And manufacturing the ferroelectric layer between the gate electrode and the channel forming layer. Stacking a plurality of memory cells on a substrate, The memory cell includes a gate electrode, a drain and a source electrode, a channel forming layer, and a ferroelectric layer. The ferroelectric layer of the stacked memory cells is composed of a mixture of inorganic ferroelectric materials and organic materials, and is composed of different ferroelectric materials. And a channel forming layer is formed between the gate electrode and the ferroelectric layer. Stacking a plurality of memory cells on a substrate, The memory cell includes a gate electrode, a drain and a source electrode, a channel forming layer, and a ferroelectric layer. The ferroelectric layer of the stacked memory cells is composed of a mixture of inorganic ferroelectric materials and organic materials, and is composed of different ferroelectric materials. A ferroelectric memory device, characterized in that a ferroelectric layer is formed between the gate electrode and the channel forming layer.

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