KR20080094996A - Liquid crystal display device and method for fabricating the same - Google Patents

Abstract

An LCD(Liquid Crystal Display) device and a manufacturing method thereof are provided to prevent a protection film pressing stain by a cell gap holding member to improve the uniformity of a cell gap and liquid crystal distribution, thereby improving image quality. An LCD device includes a first substrate(100), a second substrate(170), at least one TFT(Thin Film Transistor), a first electrode(133), a cell gap holding member(185), a pad(133a), and a liquid crystal layer. The first substrate has plural pixel regions. The second substrate faces the first substrate. The at least one TFT is formed in the pixel regions. The first electrode is connected to the TFT and is formed in the pixel regions. The cell gap holding member is formed on the second substrate. The pad is formed on the first substrate and faces the cell gap holding member. The liquid crystal layer is interposed between the first and second substrates.

Description

Liquid crystal display device and method for manufacturing the same

1 is an enlarged plan view of a unit pixel of a transverse electric field type liquid crystal display device according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of a transverse electric field type liquid crystal display device taken along the line II ′ of FIG. 1.

3A is a cross-sectional view illustrating a manufacturing process of a first substrate in a transverse electric field type liquid crystal display device according to the present invention.

3B is a cross-sectional view illustrating a manufacturing process of a first substrate in a transverse electric field type liquid crystal display device according to the present invention.

3C is a cross-sectional view illustrating a manufacturing process of a first substrate in a transverse electric field type liquid crystal display device according to the present invention.

3D is a cross-sectional view illustrating a manufacturing process of a first substrate in a transverse electric field type liquid crystal display device according to the present invention.

4A is a cross-sectional view illustrating a manufacturing process of a second substrate in a transverse electric field type liquid crystal display device according to the present invention.

4B is a cross-sectional view illustrating a manufacturing process of a second substrate in a transverse electric field type liquid crystal display device according to the present invention.

4C is a cross-sectional view illustrating a manufacturing process of a second substrate in a transverse electric field type liquid crystal display device according to the present invention.

4D is a cross-sectional view illustrating a manufacturing process of a second substrate in a transverse electric field type liquid crystal display device according to the present invention.

5 is an enlarged plan view of a unit pixel of a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view of the liquid crystal display shown along the line II-II ′ of FIG. 5.

<Description of Signs of Major Parts of Drawings>

100, 200: first substrate 133, 233: first electrode

133a and 233a: pad 170 and 270: second substrate

185, 285: cell gap holding member

The present invention relates to a liquid crystal display device and a manufacturing method thereof.

As the information society develops, the demand for display devices is increasing in various forms. In response, liquid crystal display devices (LCDs), plasma display panels (PDPs), and electroluminescent displays have been recently developed. Various flat panel display devices such as electroluminescent display (VL) and vacuum fluorescent display (VFD) have been studied, and some of them are already used as display devices in various devices.

Among them, the liquid crystal display is the most widely used as a substitute for the CRT (Cathode Ray Tube) for the use of the mobile image display device because of the excellent image quality, light weight, thinness, and low power consumption. In addition to the use of the present invention, a variety of applications such as a television, a computer monitor, and the like for receiving and displaying broadcast signals have been developed.

In order to use a liquid crystal display as a general screen display device in various parts, development of high quality images such as high definition, high brightness, and large area is required while maintaining the characteristics of light weight, thinness, and low power consumption. It can be said.

A general liquid crystal display device may be largely divided into a liquid crystal panel displaying an image and a driving unit for applying a driving signal to the liquid crystal panel, wherein the liquid crystal panel includes first and second substrates bonded to each other with a predetermined space, and It consists of the liquid crystal layer injected between the 1st, 2nd board | substrate.

A cell gap holding member is formed on at least one of the first substrate and the second substrate to maintain a constant cell gap.

When an external stimulus such as pressing is applied to the liquid crystal panel, the cell gap holding member formed on one substrate presses the other substrate.

In this case, there is a problem in that a protective film or the like formed on the other substrate is pressed and a nonuniformity of cell gap and liquid crystal distribution occurs.

An object of the present invention is to provide a liquid crystal display device and a method for manufacturing the same, which can prevent cell gap non-uniformity caused by the cell gap holding member.

In order to achieve the above object, a liquid crystal display according to the present invention includes a first substrate having a plurality of pixel regions, a second substrate facing the first substrate, at least one thin film transistor formed in the pixel region, and the thin film. A first electrode formed in the pixel region, a cell gap retaining member formed on the second substrate, a pad formed on the first substrate and facing the cell gap retaining member, and the first and second substrates; It is characterized by including a liquid crystal layer interposed therebetween.

In addition, in order to achieve the above object, the manufacturing method of the liquid crystal display device according to the present invention comprises the steps of preparing a first substrate and a second substrate, forming a light blocking pattern on the boundary of the pixel region on the second substrate, Forming a cell gap holding member on the light blocking pattern, forming a gate wiring and a gate electrode extending from the gate wiring on the first substrate, forming a semiconductor layer on the gate electrode, and forming the gate Forming a data wire crossing the wire, a source electrode formed at one end of the semiconductor layer and a drain electrode spaced apart from the source electrode to expose a channel region of the semiconductor layer, the source and drain Forming a first passivation layer on the first substrate on which the electrode is formed, and a second passivation layer on the first passivation layer Forming a pad in a region corresponding to the first electrode and the cell gap retaining member connected to the drain electrode on the second passivation layer; and bonding the first substrate and the second substrate to each other. It is characterized by.

In the liquid crystal display, since the unevenness of the protective film by the cell gap holding member is prevented, the uniformity of the cell gap and the uniformity of the liquid crystal distribution are improved, thereby improving image quality.

Hereinafter, a liquid crystal display according to the present invention will be described in detail with reference to the accompanying drawings.

<First Embodiment>

FIG. 1 is a plan view showing an enlarged unit pixel of a transverse electric field type liquid crystal display device according to a first embodiment of the present invention, and FIG. 2 is a transverse electric field type liquid crystal display device cut along a line II ′ of FIG. 1. It is a cross section of.

1 and 2, the transverse electric field type liquid crystal display device includes a first substrate 100, a second substrate 170 facing the first substrate 100, a first substrate 100, and The liquid crystal layer 190 is interposed between the second substrate 170.

A cell gap retention member 185 is formed on the second substrate 170 to maintain a uniform cell gap between the first substrate 100 and the second substrate 170.

The pad 133a corresponding to the cell gap retaining member 185 is formed on the first substrate 100.

The cell gap retaining member 185 and the pad 133a correspond one to one with each other, and an area of the pad 133a is larger than an area of one surface of the cell gap retaining member 185 facing the pad 133a.

The transverse electric field type liquid crystal display device defines a pixel region P by crossing the gate wiring 101 formed on the first substrate 100 and the gate wiring 101 on the first substrate 100. Covering the data line 121, the at least one thin film transistor (TFT) formed in the pixel region P, and the channel region of the thin film transistor TFT and covering the entire surface of the first substrate 100. And a first passivation layer 151 formed thereon and a second passivation layer 153 formed on the first passivation layer 151.

The first passivation layer 151 and the second passivation layer 153 have a first contact hole 141 exposing a predetermined region of the drain electrode 127.

The data pad part 123 is formed at one end of the data line 121.

The data pad unit 123 includes a data lower pad 121a from which the data line 121 extends and a data upper pad 135 covering the data lower pad 121a.

The data lower pad 121a and the data upper pad 135 are electrically connected to each other through a second contact hole 143 formed in the first passivation layer 151 or the second passivation layer 153.

The gate pad part 113 is formed at one end of the gate wiring 101.

The gate pad 113 includes a gate lower pad 101a from which the gate wiring 101 extends, and a gate upper pad 137 covering the gate lower pad 101a.

The gate lower pad 101a and the gate upper pad 137 are electrically connected to each other through a third through hole 145 formed in the first passivation layer 151 or the second passivation layer 153.

The thin film transistor TFT may include a gate electrode 103 that receives a signal from the gate wiring 101, a gate insulating layer 105 covering the gate electrode 103, and the gate electrode 103 at the position of the gate electrode 103. The semiconductor layer 119 formed on the gate insulating layer 105 and the source electrode 125 and the drain electrode 127 are formed on one end and the other end of the semiconductor layer 119 spaced apart from each other by a predetermined interval. Here, the source electrode 125 is connected to the data line 121 to receive a data signal.

The source electrode 125 protrudes to have a '⊂' shaped groove, and the drain electrode 127 is inserted into the '⊂' shaped groove spaced apart from the source electrode 125 by a predetermined interval. A channel region is formed in a '⊂' shape between the source electrode 125 and the drain electrode 127.

However, the shape of the source electrode 125 and the drain electrode 127 is not limited to the illustrated embodiment, and the shape of the source electrode 125 and the drain electrode 127 may vary depending on the design of the channel length and width. Naturally, it can be modified.

The semiconductor layer 119 may be formed of an active layer 115 made of amorphous silicon, an ohmic contact layer 117 contacted with the source electrode 125 and the drain electrode 127 and implanted with impurities.

A semiconductor layer pattern 119a may be further formed below the data line 121, the data lower pad 121a, and the capacitor upper electrode 130.

First electrodes 133 are connected to the drain electrode 127 of the thin film transistor TFT to receive a pixel signal, and the first and second electrodes 133 are alternately disposed in the pixel region. 2 electrodes 107 are formed.

In general, the first electrode 133 is called a pixel electrode, and the second electrode 107 is called a common electrode.

The first electrodes 133 have a bar shape, and each of the first electrodes 133 is connected to each other. However, the first electrodes 133 are not limited to a bar shape and have a bending structure, a curved shape, or a circular shape in a range having a transverse electric field between the second electrodes 107. May have

The common wiring 109 is formed on the first substrate 100 in substantially the same direction as the gate wiring 101.

The second electrode 107 is connected to the common wiring 109, and the second electrode 107 receives a common signal from the common wiring 109.

In the present exemplary embodiment, the second electrode 107 is branched from the common wiring 109 to be formed in the pixel area, and the branched second electrodes 107 are disposed at predetermined intervals from each other.

At least one of the data line 121, the first electrode 133, and the second electrode 107 may be zigzag.

A capacitor electrode 130 is formed on a portion of the gate wiring 101.

The first electrode 133 is overlapped on the capacitor electrode 130.

A fourth contact hole 147 is formed in the first passivation layer 151 and the second passivation layer 153 formed between the capacitor electrode 130 and the first electrode 133.

The capacitor electrode 130 and the first electrode 133 are electrically connected to each other through the fourth contact hole 147.

A gate insulating layer 105 is formed between the capacitor electrode 130 and the gate wiring 101 to form a storage capacitor.

The structure of forming the storage capacitor may be various, it is not limited to the illustrated embodiment.

The material constituting the first electrode 133 may include at least one selected from a group of transparent conductive metals consisting of indium tin oxide (ITO) and zinc indium oxide (IZO). have.

Metal materials constituting the gate wiring 101, the common wiring 109, and the second electrode 107 include copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), and chromium. And at least one selected from the group consisting of (Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW).

In the present exemplary embodiment, the common wiring 109 and the second electrode 107 are formed of the same layer as the gate wiring 101, but the present invention is not limited thereto. 107 may be formed of the same material as the first electrode 133 in the same layer.

Thus, the first electrode 133 and the second electrode 107 is at least one selected from the group consisting of tin indium oxide, zinc indium oxide, copper, aluminum, aluminum alloy, molybdenum, chromium, titanium, tantalum and molybdenum-tungsten It may include.

The first passivation layer 151 is made of an inorganic insulating layer, and is made of, for example, a silicon-based insulating material such as silicon nitride (SiNx).

The second passivation layer 153 is made of an organic insulating layer, and is made of, for example, an acrylic material such as photo acryl.

The thickness of the second passivation layer 153 is thicker than the thickness of the first passivation layer 151.

The second passivation layer 153 may not be formed in the gate pad part 113 and the data pad part 123.

The second passivation layer 153 further includes a second contact hole 143 exposing a portion of the data lower pad 121a of the data pad part 123, and a gate of the gate pad part 113. A third contact hole 145 is formed through the gate insulating layer 115 to expose a portion of the lower pad 101a.

A first electrode 133 is formed in the pixel region P on the second passivation layer 153, and the first electrode 133 is connected to the drain electrode 147 through the first contact hole 141. The first electrode 133 is disposed in the pixel region P at predetermined intervals.

A first alignment layer 181 is formed on the entire surface of the first substrate 100.

The second substrate 170 facing the first substrate 100 may include a light blocking pattern 171 for blocking light leakage generated at the boundary of the pixel region P, and the pixel region P. Red, green, and blue color filter patterns 173 formed by using the same are arranged.

For example, the light blocking pattern 171 is formed to correspond to the gate wiring 101, the data wiring 121, and the thin film transistor TFT area.

A second alignment layer 182 is formed on the entire surface of the second substrate 171.

In addition, the first substrate 100 and the second substrate 170 are bonded to each other by an encapsulation member formed along the outside of the panel.

A cell gap retaining member 185 is formed between the first substrate 100 and the second substrate 170 so that the first substrate 100 and the second substrate 170 are spaced apart from each other by a predetermined interval.

At least one cell gap retaining member 185 is formed on the light blocking pattern 171 on the second substrate 170.

The pad 133a is formed on the first substrate 100 to face the cell gap holding member 185.

The pad 133a corresponds one-to-one with the cell gap retaining member 185.

The pad 133a may be formed of the same material as the first electrode 133, and the pad may be formed on the same layer with the same thickness as that of the first electrode 133.

The pad 133a may have various shapes, and may be polygonal or circular.

The pad 133a may be spaced apart from the first electrode 133 or the second electrode 107, and the pad may be connected to the first electrode 133 or the second electrode 107.

When the second electrode 107 is formed on the second passivation layer 153, the pad 133a may be formed of the same material as the second electrode 107, and the pad 133a may be formed of the first material. The same thickness as that of the two electrodes 107 may be formed in the same layer.

The cell gap retaining member 185 has a smaller area of the second surface 185b facing the first substrate 100 than an area of the first surface 185a in contact with the second substrate 170.

That is, the width b of the second surface 185b is smaller than the width a of the first surface 185a.

The cell gap retaining member 185 has a columnar shape in which the width decreases from the bottom to the top.

The width c of the pad 133a corresponding to the cell gap holding member 185 is larger than the width b of the second surface 185b of the cell gap holding member 185.

The second surface 185b of the cell gap retaining member 185 may be disposed at the center of the pad 133a.

The liquid crystal layer is formed between the first substrate 100 and the second substrate 170.

In a state where the first substrate 100 and the second substrate 170 are bonded together, the cell gap retaining member 185 presses the pad 133a when an external stimulus such as pressing is applied to the panel.

In this case, since the pad 133a has a larger area than the second surface 185b of the cell gap retaining member 185 on the second passivation layer 153, the pressure applied to the second passivation layer 153 is dispersed. Can be.

In particular, since the second protective film 153 is made of an organic film such as photoacrylic, it is easy to generate a pressing mark by the pressure.

Such pressing marks may cause cell gap non-uniformity and non-uniformity of liquid crystal distribution, which may cause poor image quality. However, the pad 133a of the present exemplary embodiment may be formed by the second protective layer 153 and the cell gap retaining member 185. Disperses the pressing pressure to prevent pressing marks.

Hereinafter, a method of manufacturing a transverse electric field type liquid crystal display device according to a first embodiment of the present invention will be described in order with reference to FIGS. 3A to 3D and 4A to 4D.

3A is a cross-sectional view illustrating a manufacturing process of a first substrate in a transverse electric field type liquid crystal display device according to the present invention, and is a cross-sectional view taken along the line II ′ of FIG. 1.

As shown in FIGS. 1 and 3A, the gate wiring 101 and the common wiring 109 are formed in one direction on the first substrate 100 in the same direction as the gate wiring 101.

The gate electrode 103 protrudes from a portion of the gate line 101, and at least one branch from the common line 109 to the pixel region P forms the second electrodes 107. .

The gate electrode 103 is not necessarily protruded from the gate wiring 101, and may be a portion or an area capable of receiving a gate signal from the gate wiring 101.

Materials forming the gate wiring 101, the common wiring 109, and the second electrode 107 include copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), and chromium ( At least one selected from the group consisting of Cr), titanium (Ti), tantalum (Ta), and molybdenum-tungsten (MoW).

The gate wiring 101, the common wiring 109, and the second electrode 107 may not only be formed of a single layer of metal wiring, but also may be formed of double, triple, or more multilayer metal wiring.

Subsequently, an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) is deposited on the entire surface of the first substrate 100 by, for example, a plasma enhanced chemical vapor deposition (PECVD) method to deposit the gate insulating layer 105. Form.

The semiconductor layer 119 is formed on the gate insulating layer 105 at the gate electrode 103 position.

The semiconductor layer 119 is formed on the gate electrode 103 by sequentially depositing and patterning an amorphous silicon layer and an amorphous silicon layer into which impurities are implanted on the gate insulating layer 105.

Thereafter, a data line forming metal layer is deposited and patterned on the gate insulating layer 105 on which the semiconductor layer 119 is formed to connect the data line 121 and the data line 121 crossing the gate line 101. The source electrode 125 overlaps with one side of the semiconductor layer 119, and the drain electrode 127 overlaps with the other side of the semiconductor layer 119 to be spaced apart from the source electrode 125.

The capacitor electrode 130 may be formed on the gate wiring 101.

A semiconductor layer including an active layer 115 and an ohmic contact layer 117 by etching an amorphous silicon layer into which impurities of the semiconductor layer 119 exposed between the source electrode 125 and the drain electrode 127 are implanted. Form a pattern.

Meanwhile, in the method of forming the semiconductor layer 119, the source electrode 125, and the drain electrode 127, the semiconductor layer 119, the source, and the drain are subjected to two photolithography processes as described above. The electrodes 125 and 127 may be formed, but the semiconductor layer 119, the source electrode 125, and the drain electrode 127 may be collectively formed in one photolithography process. This will be described below.

An amorphous silicon layer, an amorphous silicon layer implanted with impurities, and a data line forming metal layer are sequentially formed on the gate insulating layer 105.

In addition, a semiconductor layer 119 including an amorphous silicon layer and an amorphous silicon layer into which impurities are implanted is formed on the gate electrode 103, and intersects with the gate wiring 101 on the first substrate 100. The data line 121 is formed at the same time in the direction.

To this end, the second process uses a diffraction mask or a half-tone mask process, and the diffraction mask process or the half-tone mask process will be described in detail as follows.

A photoresist film is formed on the substrate in which the amorphous silicon layer, the amorphous silicon layer into which the impurities are implanted, and the data line forming metal layer are sequentially stacked, and then a diffraction mask or a half-tone mask is aligned on the first substrate 100.

The photoresist film may be selectively used among a positive photoresist material or a negative photoresist material. The positive photoresist material is a material in which a cross link of the lighted portion is broken and is removed by a developer. It is a substance removed by the developer.

The diffraction mask or the half-tone mask is disposed on the photoresist film at predetermined intervals, and light, for example, ultraviolet rays or the like, is irradiated onto the photomask.

The diffraction mask or half-tone mask has a pattern formed to transmit or block irradiated light to adjust the amount of light, and the diffraction mask or half-tone mask includes a light blocking part, a light transmitting part, and a light partial transmitting part.

The light blocking portion of the diffraction mask or the half-tone mask is formed of a material capable of blocking the light irradiated with the diffraction mask or the half-tone mask, and the light transmitting portion is light irradiated with the diffraction mask or the half-tone mask. A transparent material capable of penetrating all of them is formed or opened.

The light partial transmissive portion of the diffraction mask or the half-tone mask may be formed by forming a slit in the blocking pattern so as to transmit only a portion of the light irradiated by the diffraction mask or the half-tone mask, or by patterning a material that transmits only a portion of the light. have.

The diffraction mask or half-tone mask formed as described above is disposed on the entire surface of the first substrate 100, and when light is irradiated onto the diffraction mask or half-tone mask, the diffraction mask or half-tone mask passes through the diffraction mask or half-tone mask. Light is transferred onto the photoresist film.

Subsequently, when the photoresist film is developed by immersing or spraying the developer, a stepped photoresist pattern is formed, and a region corresponding to the light blocking part remains undeveloped and corresponds to the light transmitting part. A region is removed by development to expose the data line forming metal layer, and only a portion of the region corresponding to the light partial transmissive portion is removed.

A region in which the gate insulating layer 105 is exposed by etching the metallization layer and the semiconductor layer of the portion where the photoresist pattern is exposed using the mask is exposed, and the photoresist pattern is ashed to correspond to the light partial transmissive portion. The photoresist pattern of the data line 121, the data lower pad, the source electrode 125, and the drain electrode 127 are etched by removing the photoresist pattern and etching the metal layer and the amorphous silicon layer into which the impurities are implanted. ) May be formed, as well as the semiconductor layer 119 having the active layer 115 and the ohmic contact layer 117.

When the semiconductor layer 119 and the data line 121 are formed by the mask process using the diffraction mask or the half-tone mask, the semiconductor layer pattern 119 is essentially formed under the data line 119. The semiconductor layer pattern 119 is formed under the data line 121 and the data lower pad 121a.

As a result, the gate wiring 101 and the data wiring 121 define the pixel region P while crossing each other with the gate insulating layer 105 interposed therebetween.

The source electrode 125 branched from the data line 121 extends to one end of the semiconductor layer 119 above the gate electrode 103, and the other end of the semiconductor layer 119 is formed on the source electrode ( A drain electrode 127 is formed spaced apart from the 125.

The gate electrode 103, the semiconductor layer 119, the source electrode 125, and the drain electrode 127 form a thin film transistor TFT.

3B is a cross-sectional view illustrating a manufacturing process of a first substrate in a transverse electric field type liquid crystal display device according to the present invention, and is a cross-sectional view taken along the line II ′ of FIG. 1.

As shown in FIGS. 1 and 3B, the first passivation layer 151 and the second passivation layer 153 are successively formed on the first substrate 100 on which the thin film transistor TFT is formed.

The first passivation layer 151 is made of an inorganic insulating material, for example, a silicon-based insulating material such as a silicon nitride film.

The first passivation layer 151 covers the active layer 115 exposed between the source and drain electrodes 125 and 127 of the thin film transistor TFT.

The second passivation layer 153 formed on the first passivation layer 151 is an organic insulating material, and is made of, for example, an acryl-based material such as photoacryl.

The photoacryl is a photosensitive insulating material, and there is no need to form a separate photosensitive film in order to pattern the second protective film 153.

The second passivation layer 153 is formed to a thickness of 1 ~ 3 ㎛.

By selectively exposing and developing on the second passivation layer 153, first to fourth contact holes 141, 143, 145, and 147 are formed in the second passivation layer 153.

Thereafter, the first passivation layer 151 exposed by the first to fourth contact holes 141, 143, 145, and 147 is etched.

The first contact hole 141 exposes a portion of the drain electrode 127.

The second contact hole 143 exposes a portion of the data lower pad 121a.

The gate insulating layer 105 of the third contact hole 145 and the gate pad 113 is exposed.

The fourth contact hole 147 exposes a portion of the capacitor electrode 130.

Thereafter, the gate insulating layer 105 exposed by the third contact hole 145 is further etched so that the third contact hole 145 exposes the gate lower pad 101a.

3C is a cross-sectional view illustrating a manufacturing process of a first substrate in a transverse electric field type liquid crystal display device according to the present invention, and is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 3C, a first electrode connected to the drain electrode 127 through the first contact hole 141 by depositing and patterning a transparent conductive metal on the second passivation layer 153. 133 is formed. The pad 133a is formed on at least one of the thin film transistor (TFT) region, the gate wiring 101, the data wiring 121, and the capacitor electrode 130.

A data upper pad 135 is formed on the data lower pad 121a and a gate upper pad 137 is formed on the gate lower pad 101a.

The data upper pad 135 is connected to the data lower pad 121a through the second contact hole 143.

The gate upper pad 137 is connected to the gate lower pad 101a through the third contact hole 145.

The first electrode 133 is connected to the capacitor electrode 130 through the fourth contact hole 147.

The transparent conductive metal may include at least one selected from the group of transparent conductive metals formed of tin indium oxide (ITO) or zinc indium oxide (IZO). It may include one.

3D is a cross-sectional view illustrating a manufacturing process of a first substrate in a transverse electric field liquid crystal display according to the present invention, and is a cross-sectional view taken along the line II ′ of FIG. 1.

As shown in FIGS. 1 and 3D, a first alignment layer 181 is formed on the entire surface of the first substrate 100 manufactured in the order of FIGS. 3A to 3C described above.

The first alignment layer 181 is for alignment of liquid crystal molecules.

The formation process of the alignment film is largely made of a process of applying a polymer thin film and a process of arranging the alignment film in a predetermined direction.

Generally, a polyimide-based organic material is mainly used for the first alignment layer 181, and a rubbing method is mainly used as a method of arranging the alignment layer.

In such a rubbing method, a polyimide-based organic material is first applied onto a substrate, the solvent is blown and aligned at a temperature of about 60 to 80 ° C., and then cured at a temperature of about 80 to 200 ° C. to form a polyimide alignment layer. It is a method of forming the orientation direction by rubbing the alignment layer in a predetermined direction using a rubbing cloth made of velvet or the like.

The step of arranging the alignment layer in a predetermined direction may include a non-rubbing process such as a light irradiation alignment method and an ion beam irradiation alignment method as well as the rubbing process.

The process of arranging the alignment film may also perform the rubbing method and the non-rubbing method continuously, which further improves the orientation characteristic.

4A is a cross-sectional view illustrating a manufacturing process of a second substrate in a transverse electric field type liquid crystal display device according to the present invention, and is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 4A, the light blocking pattern 171 is formed by forming and patterning a chromium (Cr) or a light blocking material on the entire surface of the second substrate 170.

The light blocking pattern 171 is formed at a boundary between an area corresponding to the pixel area P and the light blocking pattern 171.

For example, the light blocking pattern 171 may be formed in a region corresponding to the thin film transistor TFT, the gate wiring 101, the data wiring 121, and the capacitor electrode 130 formed on the first substrate 100. Formed to block light leakage.

4B is a cross-sectional view illustrating a manufacturing process of a second substrate in the transverse electric field type liquid crystal display device according to the present invention, and is a cross-sectional view taken along the line II ′ of FIG. 1.

As shown in FIGS. 1 and 4B, a color filter pattern 173 is formed on the second substrate 170 on which the light blocking pattern 171 is formed.

The light blocking pattern 171 is formed in a lattice form along the boundary of the pixel region P, and the color filter pattern 173 is formed in a region partitioned by the lattice.

The color filter pattern 173 includes red, green, and blue color filter patterns corresponding to each pixel area P. FIG.

For example, a red color resin is coated on the second substrate 170 and then patterned to form a red color filter pattern. Thereafter, a green color resin is coated on the second substrate 170 on which the red color filter pattern is formed, and then patterned to form a green color filter pattern. Thereafter, a blue color resin is coated on the second substrate 170 on which the red and green color filter patterns are formed, and then patterned to form a blue color filter pattern.

Subsequently, an overcoat layer may be formed on the entire surface of the second substrate 170 on which the light blocking pattern 171 and the color filter patterns 173 are formed so that the second substrate 170 may have a flat surface without a step. have. The overcoat layer forming process is not an essential process and can be selected as necessary.

4C is a cross-sectional view illustrating a manufacturing process of a second substrate in a transverse electric field liquid crystal display according to the present invention, and is a cross-sectional view taken along the line II ′ of FIG. 1.

As shown in FIGS. 1 and 4C, a second alignment layer 182 is formed on the second substrate 170 on which the light blocking pattern 171 and the color filter pattern 173 are formed.

The second alignment layer 182 is the same as the process of forming the first alignment layer 181.

The arrangement direction of the second alignment layer 182 may be the same as or different from the arrangement direction of the first alignment layer 181.

For example, in the transverse electric field type liquid crystal display device according to the present embodiment, the arrangement directions of the first alignment layer and the second alignment layer are the same.

4D is a cross-sectional view illustrating a manufacturing process of a second substrate in a transverse electric field liquid crystal display according to the present invention, and is a cross-sectional view taken along the line II ′ of FIG. 1.

1 and 4D, a photosensitive film is coated on the second substrate 170, the photosensitive film is partially exposed and developed to form a cell gap retaining member 185.

The photosensitive film is formed to a thickness of 2 to 4 ㎛.

The cell gap retaining member 185 has a smaller area of the second surface 185b facing the first substrate 100 than an area of the first surface 185a in contact with the second substrate 170.

That is, the width b of the second surface 185b is smaller than the width a of the first surface 185a.

The width b of the second surface 185b is 5 to 30 μm.

Width (a) of the first surface (185a) is characterized in that 2 to 2.5 times the width of the second surface (185b).

The cell gap retaining member 185 has a columnar shape in which the width decreases from the bottom to the top.

The width c of the pad 133a corresponding to the cell gap holding member 185 is larger than the width b of the second surface 185b of the cell gap holding member 185.

The cell gap maintaining member 185 is formed to have a one-to-one correspondence with the pad 133a formed on the first substrate 100.

An encapsulation member is formed along an outer periphery of one of the first substrate 100 and the second substrate 170.

Second Embodiment

FIG. 5 is a plan view illustrating an enlarged unit pixel of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view of the liquid crystal display shown along the line II-II ′ of FIG. 5.

5 and 6, the liquid crystal display device includes a first substrate 200, a second substrate 270 facing the first substrate 200, and the first substrate 200 and the second substrate. The liquid crystal layer 290 is interposed between the substrate 270.

A cell gap holding member 285 is formed on the second substrate 270 to maintain a uniform cell gap between the first substrate 200 and the second substrate 270.

The pad 233a corresponding to the cell gap retaining member 285 is formed on the first substrate 200.

The cell gap retaining member 285 and the pad 233a correspond one to one with each other, and an area of the pad is larger than an area of one surface of the cell gap retaining member facing the pad.

The liquid crystal display includes a gate wiring 201 formed on the first substrate 200 and a data wiring defining the pixel region P by crossing the gate wiring 201 on the first substrate 200. 221, at least one thin film transistor TFT formed in the pixel region P, and a first passivation layer 251 formed over the first substrate 200 to cover the channel region of the thin film transistor TFT. And a second passivation layer 253 formed on the first passivation layer 251.

The first passivation layer 251 is made of an inorganic insulating layer, and is made of, for example, a silicon-based insulating material such as silicon nitride (SiNx).

The second passivation layer 253 is formed of an organic insulating layer, and is made of, for example, an acrylic material such as photo acryl.

The thickness of the second passivation layer 253 is greater than the thickness of the first passivation layer 251.

The second passivation layer 253 may not be formed in the gate pad part 213 and the data pad part 223.

The second passivation layer 253 further includes a second contact hole 243 exposing a portion of the data lower pad 221a of the data pad unit 223, and a lower portion of the gate pad 213 of the gate pad 213. A third contact hole 245 exposing a portion of the pad 201a is formed through the gate insulating film 205.

The first passivation layer 251 and the second passivation layer 253 have a first contact hole 241 that exposes the drain electrode 227.

The data pad part 223 is formed at one end of the data line 221.

The data pad unit 223 may include a data lower pad 221a from which the data line 221 extends and a data upper pad covering the data lower pad.

The data lower pad 221a and the data upper pad 235 are electrically connected to each other through a second contact hole 243 formed in the first passivation layer 251 or the second passivation layer 253.

The gate pad part 213 is formed at one end of the gate wiring 201.

The gate pad part 213 includes a gate lower pad 201 a from which the gate wiring 201 extends and a gate upper pad 237 covering the gate lower pad 201 a.

The gate lower pad 201a and the gate upper pad 237 are electrically connected to each other through a third through hole 245 formed in the first passivation layer 251 or the second passivation layer 253.

The thin film transistor TFT may include a gate electrode 203 that receives a signal from the gate wiring 201, a gate insulating film 205 covering the gate electrode 203, and the gate electrode 203 at the position of the gate electrode 203. The semiconductor layer 219 is formed on the gate insulating layer 205 and the source electrode 225 and the drain electrode 227 which are formed at one end of the semiconductor layer 219 and the other end of the semiconductor layer 219 are spaced apart from each other by a predetermined interval. Here, the source electrode 225 is connected to the data line 221 to receive a data signal.

The source electrode 225 protrudes to have a '⊂' shaped groove, and the drain electrode 227 is inserted into the '⊂' shaped groove spaced apart from the source electrode 225 by a predetermined interval. A channel region is formed in a '전극' shape between the source electrode 225 and the drain electrode 227.

However, the shape of the source electrode 225 and the drain electrode 227 is not limited to the illustrated embodiment, the shape of the source electrode 225 and the drain electrode 227 varies depending on the design of the channel length and width Naturally, it can be modified.

The semiconductor layer 219 may be formed of an active layer 215 made of amorphous silicon, an ohmic contact layer 217 in contact with the source electrode 225 and the drain electrode 227 and implanted with impurities.

A semiconductor layer pattern 219a may be further formed below the data line 221, the data lower pad 221a, and the capacitor upper electrode 230.

First electrodes 233 connected to the drain electrode 227 of the thin film transistor and receiving a pixel signal are formed in the pixel area.

The material constituting the first electrode 233 may include at least one selected from a group of transparent conductive metals consisting of indium-tin-oxide (ITO) and zinc indium-zinc-oxide (IZO). have.

Metal materials constituting the gate wiring 201 include copper (Cu), aluminum (Al), aluminum alloy (AlNd: Aluminum Neodymium), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and the like. It may comprise at least one selected from the group consisting of molybdenum-tungsten (MoW).

A first alignment layer 281 is formed on the first substrate 200.

The second substrate 270 facing the first substrate 200 may include a light blocking pattern 271 for blocking light leakage generated at the boundary of the pixel region P, and the pixel region P. Red, green, and blue color filter patterns 273 formed by using the same are disposed.

For example, the light blocking pattern 271 is formed to correspond to the gate wiring 201, the data wiring 221, and the thin film transistor TFT area.

A second electrode 277 is formed on an entire surface of the second substrate 270 on which the light blocking pattern 271 and the color filter patterns 273 are formed.

The material constituting the second electrode 277 may include at least one selected from a group of transparent conductive metals consisting of indium tin oxide (ITO) and zinc indium oxide (IZO). have.

A second alignment layer 282 is formed on the second electrode 277.

In addition, the first substrate 200 and the second substrate 270 are bonded to each other by an encapsulation member formed along the outside of the panel.

A cell gap retaining member 285 is formed between the first substrate 200 and the second substrate 270 so that the first substrate 200 and the second substrate 270 may be spaced apart from each other by a predetermined interval.

At least one cell gap retention member 285 is formed on the light blocking pattern 271 on the second substrate 200.

The pad 233a is formed on the first substrate 200 so as to face the cell gap holding member 285.

The pad 233a corresponds one-to-one with the cell gap retaining member 285.

The pad 233a may be formed of the same material as the first electrode 233, and the pad may be formed on the same layer with the same thickness as the first electrode 233.

The pad 233a may have various shapes, and may be polygonal or circular.

The pad 233a may be spaced apart from or connected to the first electrode 233.

The cell gap retaining member 285 has a smaller area of the second surface 285b facing the first substrate 200 than an area of the first surface 285a in contact with the second substrate 270.

That is, the width of the second surface 285b is smaller than the width of the first surface 285a.

The second surface 285b has a width of 5 to 30 μm.

The width of the first surface 285a is two to 2.5 times the width of the second surface 285b.

The cell gap retaining member has a columnar shape in which the width decreases from the lower portion to the upper portion of the cell gap holding member.

The width of the pad 233a corresponding to the cell gap retaining member 285 is greater than the width of the second surface 285b of the cell gap retaining member 285.

The second surface 285b of the cell gap retaining member 285 may be disposed at the center of the pad 233a.

The liquid crystal layer 290 is formed between the first substrate 200 and the second substrate 270.

In a state where the first substrate 200 and the second substrate 270 are bonded together, the cell gap retaining member 285 presses the pad 233a when an external stimulus such as pressing is applied to the panel.

In this case, since the pad 233a has a larger area than the second surface 285b of the cell gap retaining member 285 on the second passivation layer 285, the pressure applied to the second passivation layer 253 is dispersed. Can be.

In particular, since the second passivation layer 253 is formed of an organic layer such as photoacrylic, it is easy to generate a pressing mark due to the pressure. However, the pad 233a according to the present embodiment may be formed of the second passivation layer 253 and the second passivation layer 253. The pressing pressure of the cell gap holding member 285 is dispersed to prevent the pressing marks.

By preventing the pressing of the protective film by the cell gap holding member 285, the uniformity of the cell gap and the uniformity of the liquid crystal distribution may be improved.

Although the present invention has been described in detail through specific embodiments, it is intended to describe the present invention in detail, and the liquid crystal display and the manufacturing method thereof according to the present invention are not limited thereto, and various modifications and improvements are possible.

The present invention has a first effect of improving image quality because the uniformity of the cell gap and the uniformity of the liquid crystal distribution are improved by preventing the protective film from being pressed by the cell gap holding member in the liquid crystal display.

According to the present invention, a pad corresponding to a cell gap retaining member is formed to disperse the pressing pressure of the pad, and the pad is formed in a dummy pattern when forming a pixel electrode.

Claims (23)

A first substrate having a plurality of pixel regions; A second substrate facing the first substrate; At least one thin film transistor formed in the pixel region; A first electrode connected to the thin film transistor and formed in the pixel area; A cell gap retaining member formed on the second substrate; A pad formed on the first substrate and facing the cell gap retaining member; And And a liquid crystal layer interposed between the first substrate and the second substrate. The method of claim 1, And a first passivation layer is formed on the first substrate on which the thin film transistor is formed. The method of claim 1, A first passivation layer formed on the first substrate on which the thin film transistor is formed; And a second passivation layer formed on the first passivation layer. The method of claim 3, wherein And the first passivation layer is made of an inorganic insulating material. The method of claim 3, wherein The second passivation layer is formed of an organic insulating material. The method of claim 5, wherein And the organic insulating material is photoacrylic. The method of claim 3, wherein The thickness of the second protective film is 2 to 4 ㎛ characterized in that the liquid crystal display device. The method of claim 1, A color filter pattern formed on the second substrate and corresponding to the pixel area; A light blocking pattern corresponding to a boundary of the pixel area; A second electrode formed on the second substrate; And And a second alignment layer formed on the second electrode. The method of claim 1, A second electrode formed in the pixel area on the first substrate and disposed alternately with the first electrode; A color filter pattern formed on the second substrate and corresponding to the pixel area; A light blocking pattern formed on the second substrate and corresponding to a boundary of the pixel area; And And a second alignment layer formed on the second substrate. The method of claim 1, And a first alignment layer on the first substrate on which the pad is formed. The method of claim 1, And the pad is spaced apart from the first electrode. The method of claim 1, And the pad is connected to the first electrode. The method of claim 1, And the pad is formed of the same layer and the same material as the first electrode. The method of claim 1, And the cell gap holding member has an area of a first surface in contact with the second substrate being larger than an area of a second surface facing the first substrate. The method of claim 14, The width of the first surface is 2 to 2.5 times the width of the second surface of the liquid crystal display device. The method of claim 1, And the pad is larger than an area of the second surface of the cell gap retaining member facing the pad. The method of claim 14, The width of the second surface is 5 ~ 30 ㎛ characterized in that the liquid crystal display device. Preparing a first substrate and a second substrate; Forming a light blocking pattern on a boundary of a pixel region on the second substrate; Forming a cell gap retaining member on the light blocking pattern; Forming a gate wiring and a gate electrode extending from the gate wiring on the first substrate; Forming a semiconductor layer on the gate electrode; Forming a data line crossing the gate line, a source electrode connected to the data line and a drain electrode spaced apart from the source electrode to expose a channel region of the semiconductor layer; Forming a first passivation layer on the first substrate on which the source and drain electrodes are formed; Forming a second passivation layer on the first passivation layer; Forming a pad on the second passivation layer in a region corresponding to the first electrode connected to the drain electrode and the cell gap retaining member; And And bonding the first substrate and the second substrate to each other. The method of claim 18, In the forming of the first electrode and the pad, Forming a metal layer on the second passivation layer; Forming a photoresist pattern on the metal layer; And And etching the metal layer using the photoresist pattern as a mask to form the first electrode and the pad. The method of claim 18, In the forming of the gate wiring and the gate electrode, And forming a common wiring in the same direction as the gate wiring, and forming a second electrode branched from the common wiring and arranged alternately with the first electrode. The method of claim 18, And said second protective film is photoacrylic. The method of claim 18, After the forming of the first electrode and the pad, And forming a first alignment layer over the entire surface of the first substrate. The method of claim 18, Prior to forming the cell gap retaining member, And forming a second alignment layer on the entire surface of the second substrate.

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