KR20080088102A - Method for manufacturing of wafer level package - Google Patents
Method for manufacturing of wafer level package Download PDFInfo
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- KR20080088102A KR20080088102A KR1020070030523A KR20070030523A KR20080088102A KR 20080088102 A KR20080088102 A KR 20080088102A KR 1020070030523 A KR1020070030523 A KR 1020070030523A KR 20070030523 A KR20070030523 A KR 20070030523A KR 20080088102 A KR20080088102 A KR 20080088102A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 claims abstract description 89
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000000465 moulding Methods 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims abstract description 12
- 229910000679 solder Inorganic materials 0.000 claims abstract description 11
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 9
- 238000000227 grinding Methods 0.000 claims abstract description 6
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 239000002390 adhesive tape Substances 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims description 4
- 238000007789 sealing Methods 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 210000004185 liver Anatomy 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 238000004148 unit process Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
Description
도 1a 내지 도 1c는 본 발명의 실시예에 따른 웨이퍼 레벨 패키지의 제조 방법을 설명하기 위하여 도시한 도면.1A to 1C are diagrams for explaining a method of manufacturing a wafer level package according to an embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
102 : 반도체 칩 106 : 유니트 레벨 기판102
108 : 캐버티 110 : 접속 패드108: cavity 110: connection pad
112 : 볼랜드 114 : 금속 와이어112: Borland 114: metal wire
116 : 몰딩부 118 : 솔더볼116: molding 118: solder ball
120 : 본딩 패드 122 : 접착 부재120: bonding pad 122: adhesive member
본 발명은 웨이퍼 레벨 패키지의 제조 방법에 관한 것으로서, 보다 상세하게는, 제조 공정을 단순화할 수 있고, 제조 원가를 절감시킬 수 있는 웨이퍼 레벨 패키지의 제조 방법에 관한 것이다. The present invention relates to a method for manufacturing a wafer level package, and more particularly, to a method for manufacturing a wafer level package that can simplify the manufacturing process and reduce the manufacturing cost.
오늘날 전자 산업의 추세는 경량화, 소형화, 고속화, 다기능화, 고성능화되 고 높은 신뢰성을 갖는 제품을 저렴하게 제조하는 것이다. 이와 같은 제품 설계의 목표 달성을 가능하게 하는 중요한 기술 중의 하나가 바로 패키지 조립 기술이다.The trend in today's electronics industry is to make products that are lighter, smaller, faster, more versatile, more powerful and more reliable. One of the key technologies that enables these product design goals is package assembly technology.
이러한 패키지 조립 기술은 웨이퍼 조립 공정을 거쳐 집적회로가 형성된 반도체 칩을 외부 환경으로부터 보호하고, 기판 상에 용이하게 실장되도록 하여 반도체 칩의 동작 신뢰성 확보하기 위한 기술이다.This package assembly technique is a technique for securing the operation reliability of the semiconductor chip by protecting the semiconductor chip on which the integrated circuit is formed through the wafer assembly process from the external environment and easily mounted on the substrate.
기존의 패키지는 웨이퍼를 절단하여 개개의 반도체 칩들로 분리시킨 다음, 개개의 반도체 칩 별로 패키징 공정을 실시하는 방식으로 제조되었다. 그러나, 상기의 패키징 공정은 자체적으로 많은 단위 공정들, 즉, 칩 부착, 와이어 본딩, 몰딩, 트림/포밍 등의 공정들을 포함하고 있는 바, 반도체 칩 별로 각각의 패키징 공정이 수행되어야 하는 기존의 패키지 제조방법은, 하나의 웨이퍼에서 얻어지는 반도체 칩의 수를 고려할 때, 모든 반도체 칩에 대한 패키징 소요 시간이 너무 많다는 문제점을 갖고 있다.Existing packages are manufactured by cutting a wafer into separate semiconductor chips and then packaging the semiconductor chips. However, the packaging process itself includes many unit processes, that is, chip attaching, wire bonding, molding, trim / forming, etc., and thus, a conventional package in which each packaging process must be performed for each semiconductor chip. The manufacturing method has a problem that the packaging time for all the semiconductor chips is too large, considering the number of semiconductor chips obtained from one wafer.
이에, 최근에는 개별 반도체 칩으로 분리된 상태에서 조립이 진행되지 않고, 웨이퍼 상태에서 재배선 작업과 볼 형태의 외부 접속 단자의 형성 및 개별 반도체 칩 분리하는 작업을 거쳐 제조하는 웨이퍼 레벨 패키지(Wafer Level Package)라는 기술이 제안되었다.Therefore, in recent years, assembling does not proceed in a state of being separated into individual semiconductor chips, and wafer level packages manufactured by rewiring in a wafer state, formation of ball-type external connection terminals, and work of separating individual semiconductor chips (Wafer Level) Package technology has been proposed.
한편, 웨이퍼 레벨 패키지의 제조 방법을 간단히 살펴보면, 우선, 상면에 회로 패턴이 형성된 반도체 칩 상면 전체에 절연막을 형성하고 포토 공정을 통하여 본딩 패드를 노출시키고, 상기 절연막으로 형성된 반도체칩 상면 일부에 전기적 신호연결을 위하여 메탈층을 증착시킨다.On the other hand, briefly looking at the manufacturing method of the wafer-level package, first, an insulating film is formed on the entire upper surface of the semiconductor chip having a circuit pattern formed thereon, the bonding pad is exposed through a photo process, and an electrical signal is formed on a portion of the upper surface of the semiconductor chip formed of the insulating film. A metal layer is deposited for the connection.
다음으로, 다시 포토 공정을 이용하여 상기 반도체 칩 상에 증착된 메탈층과 볼랜드를 도금한 후, 상기 메탈층을 식각하여 솔더 범프가 형성될 영역을 노출시켜 상기 솔더 범프가 형성될 영역과 본딩 패드 간이 전기적으로 연결되도록 재배선층을 형성한다.Next, after plating the metal layer and the borland deposited on the semiconductor chip using a photo process again, the metal layer is etched to expose the region where the solder bumps are to be formed, and the bonding pads and the region where the solder bumps are to be formed. The redistribution layer is formed so that the liver is electrically connected.
그런 다음, 상기 솔더 범프가 형성될 영역을 제외한 전 부분에 솔더 마스크를 형성시키고, 상기 노출된 솔더 범프 자리에 솔더를 부착하여 마운팅(mounting)하며, 각각의 패키지로 쏘잉(sawing)하여 웨이퍼 레벨 패키지를 제조한다.Then, a solder mask is formed over the entire area except the region where the solder bumps are to be formed, and the solder is attached to the exposed solder bumps to mount them, and sawed into each package to wafer-level packages. To prepare.
그러나, 종래 웨이퍼 레벨 패키지는 반도체 칩의 패드 재배선 공정이 필수적으로 필요하며, 스퍼터링(Sputtering), 스핀 코팅(Spin Coating), 포토리소그라피( Photolithography), 도금(Plating) 공정, 에칭(Etching) 공정 등의 복잡한 공정을 사용하기 때문에 웨이퍼 레벨 패키지의 제조 공정 난이도가 높으며, 웨이퍼 레벨 패키지 제조 공정에 사용되는 원소재의 가격이 높아 제조 비용이 높다.However, conventional wafer level packages require a semiconductor chip pad redistribution process, and are sputtering, spin coating, photolithography, plating, etching, and the like. Due to the complicated process of using, the manufacturing process difficulty of the wafer level package is high, and the cost of the raw materials used in the wafer level package manufacturing process is high.
본 발명은 제조 공정을 단순화할 수 있고, 제조 원가를 절감시킬 수 있는 웨이퍼 레벨 패키지의 제조 방법을 제공한다. The present invention provides a method of manufacturing a wafer level package that can simplify the manufacturing process and reduce the manufacturing cost.
본 발명에 따른 웨이퍼 레벨 패키지 제조 방법은, 다수의 센터 패드형 반도체 칩들로 구성된 웨이퍼의 각 반도체 칩 상에 중앙부에 캐버티가 구비된 기판을 부착하는 단계; 상기 각 캐버티를 관통하여 대응하는 반도체 칩과 기판을 각각 금속 와이어로 연결시키는 단계; 상기 금속 와이어를 포함하여 각 기판의 캐버티 부 분을 몰딩하는 단계; 상기 각 기판에 솔더볼을 형성하는 단계; 및 상기 웨이퍼 레벨을 각 반도체 칩 레벨로 절단하는 단계;를 포함하는 것을 특징으로 한다. A wafer level package manufacturing method according to the present invention comprises the steps of: attaching a substrate having a cavity at the center on each semiconductor chip of the wafer consisting of a plurality of center pad-type semiconductor chips; Connecting the semiconductor chip and the substrate to each other by metal wires through the cavities; Molding a cavity portion of each substrate including the metal wires; Forming solder balls on each of the substrates; And cutting the wafer level to each semiconductor chip level.
상기 웨이퍼의 상면에 반도체 패키지용 기판을 부착하는 단계 전, 상기 웨이퍼의 후면에 백그라인딩 공정을 진행하는 단계를 더 포함하는 것을 특징으로 한다. The method may further include performing a backgrinding process on the rear surface of the wafer before attaching the semiconductor package substrate to the upper surface of the wafer.
상기 웨이퍼의 후면에 백그라인딩 공정을 진행하는 단계 후, 상기 웨이퍼의 후면에 몰딩제 또는 반도체 칩 보호용 필름을 형성하는 단계를 더 포함하는 것을 특징으로 한다.After the step of performing a back grinding process on the back of the wafer, characterized in that it further comprises the step of forming a molding agent or a semiconductor chip protective film on the back of the wafer.
상기 웨이퍼를 구성하는 각 반도체 칩의 상면에 기판을 부착하는 단계는, 상기 각 반도체 칩의 크기 및 수에 대응하는 유니트 레벨 기판으로 이루어지며 상기 웨이퍼의 크기에 대응하는 크기를 갖는 스트립 레벨 기판을 웨이퍼의 상면에 부착하는 방법으로 이루어지는 것을 특징으로 한다.The step of attaching the substrate to the upper surface of each semiconductor chip constituting the wafer, consisting of a unit level substrate corresponding to the size and number of each semiconductor chip, the wafer having a strip level substrate having a size corresponding to the size of the wafer Characterized in that the method consists of attaching to the upper surface.
상기 웨이퍼를 구성하는 각 반도체 칩의 상면에 기판을 부착하는 단계는, 상기 각 반도체 칩의 크기에 대응하는 유니트 레벨 기판을 상기 각 반도체 칩의 상면에 부착하는 방법으로 이루어지는 것을 특징으로 한다.The step of attaching the substrate to the upper surface of each semiconductor chip constituting the wafer, characterized in that consisting of a method of attaching a unit level substrate corresponding to the size of each semiconductor chip on the upper surface of each semiconductor chip.
상기 기판은 웨이퍼의 반도체 칩에 접착 테이프 또는 액상 접착제를 사용하여 부착하는 것을 특징으로 한다.The substrate is characterized in that attached to the semiconductor chip of the wafer using an adhesive tape or a liquid adhesive.
(실시예)(Example)
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세하게 설명하도록 한다. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 종래 웨이퍼 레벨 패키지의 필수 공정인 재배선 공정을 진행하지 않고, 일반적인 반도체 패키지에 사용되는 반도체 패키지용 기판을 사용하여 볼 형태의 외부 접속 단자를 형성하는 방법으로 웨이퍼 레벨 패키지를 제조한다. The present invention manufactures a wafer level package by a method of forming an external connection terminal in the form of a ball using a semiconductor package substrate used in a general semiconductor package without proceeding a rewiring process, which is an essential step of a conventional wafer level package.
자세하게, 본 발명은 중앙부에 다수의 본딩 패드를 구비한 센터 패드형 반도체 칩들로 구성된 웨이퍼의 후면에 반도체 칩을 보호하기 위한 보호 필름 또는 몰딩제를 형성하고, 각 반도체 칩 상에 중앙부에 캐버티가 형성되어 있고 하면에 다수의 접속 패드 및 볼랜드가 구비된 일반적인 반도체 패키지 제조용 기판을 부착한다.In detail, the present invention forms a protective film or a molding agent for protecting a semiconductor chip on the back side of a wafer composed of center pad-type semiconductor chips having a plurality of bonding pads in a central portion, and a cavity in the central portion on each semiconductor chip. It is formed, and a substrate for manufacturing a general semiconductor package having a plurality of connection pads and a ball land is attached to the lower surface.
그런 다음, 상기 웨이퍼 레벨 단위에서 상기 반도체 칩의 본딩 패드와 기판의 접속 패드 간에 본딩 와이어를 형성하고, 캐버티 부분을 몰딩한 후, 개개의 반도체 패키지 단위로 절단하여 웨이퍼 레벨 패키지를 제조한다. Then, a bonding wire is formed between the bonding pad of the semiconductor chip and the connection pad of the substrate at the wafer level unit, the cavity portion is molded, and then cut into individual semiconductor package units to manufacture a wafer level package.
따라서, 본 발명에 따른 웨이퍼 레벨 패키지는 종래 웨이퍼 레벨 패키지의 필수 공정인 재배선 공정을 진행하지 않고, 일반적인 반도체 패키지에 사용되는 반도체 패키지용 기판을 사용하여 볼 형태의 외부 접속 단자를 형성함으로써 웨이퍼 레벨 패키지의 복잡한 제조 과정을 단순화할 수 있고, 웨이퍼 레벨 패키지의 제조 비용을 절감할 수 있다.Therefore, the wafer level package according to the present invention does not proceed with the rewiring process, which is an essential step of the conventional wafer level package, and forms a ball-level external connection terminal using a semiconductor package substrate used for a general semiconductor package. The complex manufacturing process of the package can be simplified and the manufacturing cost of the wafer level package can be reduced.
그리고, 종래 웨이퍼 레벨 패키지와 달리, 몰딩제로 반도체 칩을 완전히 밀봉하지 않고 반도체 칩의 상부 및 측면을 외부로 노출시킴으로써 반도체 패키지를 외부 온도에 따라 자유롭게 수축 및 팽창을 할 수 있도록 하여 열에 의해 반도체 패키지 내부에 작용하는 스트레스를 감소시켜 신뢰성을 향상시킬 수 있다.And, unlike a conventional wafer level package, the semiconductor package can be freely shrunk and expanded according to an external temperature by exposing the upper and side surfaces of the semiconductor chip to the outside without completely sealing the semiconductor chip with a molding agent, and thereby, inside the semiconductor package by heat. It can improve the reliability by reducing the stress acting on.
또한, 와이어 본딩 공정 설비와 같은 종래 반도체 패키지 제조 설비를 활용 할 수 있으므로 웨이퍼 레벨 패키지를 제조하기 위한 투자비용이 절감시킬 수 있다.In addition, it is possible to utilize the conventional semiconductor package manufacturing equipment, such as wire bonding process equipment can reduce the investment cost for manufacturing a wafer-level package.
도 1a 내지 도 1c는 본 발명의 실시예에 따른 웨이퍼 레벨 패키지의 제조 방법을 설명하기 위하여 도시한 도면이다.1A to 1C are diagrams for explaining a method of manufacturing a wafer level package according to an embodiment of the present invention.
도 1a를 참조하면, 중앙부에 다수의 본딩 패드(120)를 구비한 센터 패드형 반도체 칩(102)들로 이루어진 웨이퍼(100)의 후면에 백그라인딩 공정을 진행한다.Referring to FIG. 1A, a backgrinding process is performed on a rear surface of a
그런 다음, 상기 백그라인딩 공정이 진행된 웨이퍼(100)의 각 반도체 칩(102) 상에 중앙부에 캐버티(108)가 구비된 반도체 패키지용 기판을 접착 테이프 또는 액상 접착제와 같은 접착 부재(122)를 매개로 부착한다.Subsequently, a semiconductor package substrate having a
이때, 상기 반도체 패키지용 기판은 상기 웨이퍼(100)를 구성하고 있는 각 센터 패드형 반도체 칩(102)의 크기 및 형태에 대응하는 유니트 레벨 기판(106) 또는 웨이퍼(100)의 크기에 대응하는 유니트 레벨 기판(106)으로 구성된 스트립 레벨 기판(104)으로서, 일반적인 센터 패드형 반도체 칩(102)으로 패키지를 구성할 때 사용되는 기판이며, 하면에 다수의 접속 패드(110) 및 볼랜드(112)가 형성되어 있다. In this case, the semiconductor package substrate is a
그리고, 상기 웨이퍼(100) 상에 유니트 레벨 기판(106) 또는 스트립 레벨 기판(104)을 부착하는 방법은, 웨이퍼(100)의 크기 및 웨이퍼(100)에 구비된 반도체 칩(102)의 수에 맞추어 다수의 유니트 레벨 기판(106)으로 구성된 스트립 레벨 기판(10)을 웨이퍼(100) 상에 부착하거나, 또는, 상기 스트립 레벨 기판(104)을 각각 절단 및 분리하여 상기 웨이퍼(100)를 구성하고 있는 각 반도체 칩(102)에 개별적 으로 유니트 레벨 기판(106)을 부착하는 방식으로 진행된다. In addition, the method of attaching the
도 2b를 참조하면, 웨이퍼 레벨에서 상기 각 반도체 칩(102)의 본딩 패드(120)와 상기 각 반도체 칩(102)에 접착 테이프 또는 액상 접착제와 같은 접착 부재(122)를 매개로 부착된 각 유니트 레벨 기판(106)의 접속 패드(110) 간에 본딩 와이어 공정을 진행하여 금속 와이어(114)를 연결한다. Referring to FIG. 2B, each unit attached to a
그런 다음, 웨이퍼 레벨에서 상기 와이어 본딩 공정으로 형성된 상기 금속 와이어(114)를 보호하기 위하여 상기 유니트 레벨 기판(106)의 캐버티 부분을 몰딩하여 몰딩부(116)를 형성한다.Then, the cavity portion of the
이어서, 상기 유니트 레벨 기판(106)의 후면에 형성된 볼랜드(112)에 솔더볼(118)을 형성한 후, 상기 웨이퍼 레벨을 각 반도체 칩 레벨로 절단하여 분리한다. Subsequently, after the
따라서, 본 발명은 일반적인 반도체 패키지에 사용되는 반도체 패키지용 기판을 사용함으로써 제조 과정을 단순화할 수 있다. Therefore, the present invention can simplify the manufacturing process by using a substrate for a semiconductor package used in a general semiconductor package.
한편, 본 발명은 웨이퍼 레벨 패키지의 제조 과정 중에, 도 1c를 참조하면, 중앙부에 다수의 본딩 패드(120)를 구비한 센터 패드형 반도체 칩(102)들로 이루어진 웨이퍼(100)의 후면에 백그라인딩 공정을 진행한 후, 상기 웨이퍼(100)의 후면에 상기 반도체 칩(102)을 보호하기 위한 몰딩제 또는 보호 필름 등과 같은 반도체 칩(102) 보호물질(124)을 형성할 수 있다.Meanwhile, in the manufacturing process of the wafer-level package, referring to FIG. 1C, the back of the
이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다.As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.
이상에서와 같이, 본 발명은 다수의 반도체 칩으로 구성된 웨이퍼의 후면에 반도체 칩을 보호하기 위한 보호 필름 또는 몰딩제를 형성하고, 각 반도체 칩 상에 일반적인 반도체 패키지 제조용 기판을 부착하는 방법으로 웨이퍼 레벨 패키지를 제조한다.As described above, the present invention forms a protective film or molding agent for protecting a semiconductor chip on the back surface of a wafer composed of a plurality of semiconductor chips, and a wafer level by attaching a substrate for manufacturing a general semiconductor package on each semiconductor chip. Manufacture the package.
따라서, 본 발명에 따른 웨이퍼 레벨 패키지는 종래 웨이퍼 레벨 패키지의 필수 공정인 재배선 공정을 진행하지 않고, 일반적인 반도체 패키지에 사용되는 반도체 패키지용 기판을 사용하여 볼 형태의 외부 접속 단자를 형성함으로써 웨이퍼 레벨 패키지의 복잡한 제조 과정을 단순화할 수 있고, 웨이퍼 레벨 패키지의 제조 비용을 절감할 수 있다.Therefore, the wafer level package according to the present invention does not proceed with the rewiring process, which is an essential step of the conventional wafer level package, and forms a ball-level external connection terminal using a semiconductor package substrate used for a general semiconductor package. The complex manufacturing process of the package can be simplified and the manufacturing cost of the wafer level package can be reduced.
그리고, 종래 웨이퍼 레벨 패키지와 달리, 몰딩제로 반도체 칩을 완전히 밀봉하지 않고 반도체 칩의 상부 및 측면을 외부로 노출시킴으로써 반도체 패키지를 외부 온도에 따라 자유롭게 수축 및 팽창을 할 수 있도록 하여 열에 의해 반도체 패키지 내부에 작용하는 스트레스를 감소시켜 신뢰성을 향상시킬 수 있다.And, unlike a conventional wafer level package, the semiconductor package can be freely shrunk and expanded according to an external temperature by exposing the upper and side surfaces of the semiconductor chip to the outside without completely sealing the semiconductor chip with a molding agent, and thereby, inside the semiconductor package by heat. It can improve the reliability by reducing the stress acting on.
또한, 종래 반도체 패키지 제조 설비를 활용할 수 있으므로 웨이퍼 레벨 패키지를 제조하기 위한 투자비용이 절감시킬 수 있다. In addition, since the conventional semiconductor package manufacturing equipment can be utilized, the investment cost for manufacturing a wafer level package can be reduced.
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