KR20080070045A - Image display apparatus, electronic device, portable terminal device, and method of displaying image - Google Patents

Abstract

A multiple-bit memory system is applied to a liquid crystal display device which stores input image data (SIG) in a memory (62) for each pixel and drives on a time-sharing basis to display a half-tone image in response to the input image data stored in the memory (62).

Description

Image display devices, electronic devices, mobile devices, and image display methods {IMAGE DISPLAY APPARATUS, ELECTRONIC DEVICE, PORTABLE TERMINAL DEVICE, AND METHOD OF DISPLAYING IMAGE}

The present invention relates to an image display apparatus, an electronic apparatus, a portable apparatus, and an image display method, and can be applied to, for example, a liquid crystal display apparatus using a multi-bit memory system. The present invention records the input image data in the memory section of each pixel and expresses the gray scale by driving the time division according to the input image data recorded in the memory section, which is more efficient than the conventional method in image display by a multi-bit memory system. Displays images at high quality.

Background Art Conventionally, a liquid crystal display device is provided in Japanese Laid-Open Patent Publication No. 2005-1641814 or the like with a plurality of sub pixels having different areas, and the display is controlled by display and non-display control of the plurality of sub pixels. A so-called area gray scale method of varying the gray scale of each pixel by varying the area of the area used is proposed. Also, in Japanese Unexamined Patent Application Publication No. 2005-1641814, one bit of memory is provided in one subpixel, and the display and non-display of the corresponding subpixel are controlled by writing the memory, thereby inputting by multiple bits. A method of expressing the gradation of image data has been proposed. In the following description, the multi-bit memory is provided in one pixel in this manner, and the method of expressing the gray level of each pixel by writing the multi-bit memory is called a multi-bit memory system.

That is, FIG. 1 is a block diagram which shows the image display apparatus by the multi-bit memory system of this area gray scale system. In this image display apparatus 1, the display part 2 is a reflective liquid crystal display panel or a transmissive liquid crystal display panel, and is formed by arrange | positioning the pixel which set the red, green, and blue color filter in matrix form.

As shown in FIG. 2, the configuration of one pixel 2A of this display unit 2, each pixel 2A includes electrodes 3A, 3B, 3C, 3D, 3E, and 3F, which are sites used for display. ) Is formed by a plurality of sub-pixels 2AA to 2AF set to 1: 2: 4: 8: 16: 32. The sub-pixels 2AA to 2AF are formed in the same manner except that the areas of the electrodes 3A to 3F are set in a constant proportional relationship, and the pixel circuits 4A to 4F shown in FIG. Each of the liquid crystal cells 5A to 5F by the electrodes 3A to 3F is driven.

That is, the pixel circuits 4A to 4F are CMOS inverters 6 each including an N-channel MOS transistor (hereinafter referred to as NMOS) transistor Q1 and a P-channel MOS transistor (hereinafter referred to as PMOS) transistor Q2 each having a gate and a drain connected in common. Similarly, a CMOS inverter 7 composed of an NMOS transistor Q3 and a PMOS transistor Q4 each having a common gate and a drain connected to each other is provided in parallel between the positive side power line VDD and the negative side power line VSS. (6, 7) are connected in a loop shape to form a memory by SRAM (Static Random Access Memory) configuration.

The pixel circuits 4A to 4F connect the signal lines SIG to these CMOS inverters 6 and 7 by the NMOS transistor Q5 to form a switch circuit 8 for supplying the logic values of the signal lines SIG to the memory. As shown in Fig. 4, by the control of the NMOS transistor Q5 by the gate signal GATE (Fig. 4B), data by the signal line SIG (Fig. 4A) is set in the memory (Fig. 4 (C)). In addition, V1 is a potential on the input side of the inverter 6 which is an input side by this switch circuit 8 here.

The pixel circuits 4A to 4F are applied to the common voltage VCOM (FIG. 4G) applied to the common electrode of the liquid crystal cells 5A (5B to 5F) in accordance with the data held in the memory in this manner. , The in-phase drive signal FRP (FIG. 4D) or the reverse phase drive signal XFRP (FIG. 4E) is selected and applied to the liquid crystal cells 5A (5B to 5F), whereby the liquid crystal cell ( 5A) (5B to 5F) are driven. That is, the pixel circuits 4A to 4F turn on and off the switch circuit 9 including the NMOS transistor Q6 and the PMOS transistor Q7 by the output of the inverter 7, and through the switch circuit 9, the common potential VCOM In-phase drive signal XFRP is applied to liquid crystal cells 5A (5B to 5F). In addition, the switch circuit 10 consisting of the same NMOS transistor Q8 and PMOS transistor Q9 is controlled on and off by the output of the inverter 6, and the drive signal FRP in the reverse phase of the common potential VCOM is reversed through the switch circuit 10. To cells 5A (5B to 5F).

As a result, as shown in FIG. 4, when the potential of the signal line SIG is switched, the voltage V5 applied to the liquid crystal cells 5A (5B to 5F) from the time point t1 of the subsequent rise of the gate signal GATE (FIG. 4F). )) Can be switched from in-phase to inverse phase with respect to the common potential VCOM to switch between display and non-display of the liquid crystal cells 5A (5B to 5F). In addition, the example shown in this FIG. 4 is a case with what is called normally black.

In the image display device 1 (FIG. 1), the interface (IF) 11 includes image data SDI based on serial data sequentially indicating gray levels of respective pixels, a system lock SCK synchronized with this image data SDI, and vertical synchronization. The timing signal SCS in synchronization with the signal is input from the configuration of the device in which the image display device 1 is installed. The interface 11 divides this image data SDI into two systems corresponding to the odd lines and even lines of the display portion 2, and outputs the separated image data DATA to the horizontal drivers 12O and 12E, respectively. In addition, a clock LSSCK in synchronization with this image data DATA is generated and output to the timing generator 14. In addition, the timing signal SCS outputs to the timing generator 14 a reset signal RST whose signal level rises at a timing synchronized with the vertical synchronization signal.

The timing generator 14 generates and outputs various timing signals necessary for the operation of the horizontal drivers 12O and 12E and the vertical driver 15 from these clocks LSSCK and the reset signal RST.

The horizontal drivers 12O and 12E operate by the timing signal output from the timing generator 14, and the image data DATA output from the interface 11 to the pixels of odd lines and even lines of the display unit 2, respectively. The logic level of the signal line SIG is set to correspond to.

That is, as shown in Fig. 5, the horizontal driving units 12O and 12E sequentially line the timing signal HST rising at the timing of the start of the horizontal scanning period by the shift registers SR 21A, 21B,... Direction, and the image data DATA is latched by the sampling latches SL (22A, 22B, ...) according to the timing signals output from the respective shift registers 21A, 21B, .... As a result, the horizontal drivers 12O and 12E classify the image data DATA into corresponding signal lines SIG.

The second latches 23A, 23B, ..., ... latch and output the latch results of these sampling latches 22A, 22B, ..., respectively, thereby matching the timing of the image data classified by the respective signal lines SIG, Output The parallel serial conversion circuit PS 24A, 24B, ... is sequentially selected by the selection signal SERI for the logic value of each bit constituting the latch result Lout of the second latch 23A, 23B, .... By outputting the data, the input image data classified by each signal line SIG is converted into serial data and output.

That is, as shown in Figs. 6 and 7, in the parallel serial conversion circuits 24A, 24B, ..., the AND circuits 25 to 30 select signal SERI0 to SERI5 ( According to Figs. 7A to 7A, the logic values Lout0 to Lout5 of the respective bits of the latch result Lout are gated, respectively, and the OR circuit 31 supplies the output signals of these AND circuits 25 to 30, respectively. Generate a logical sum signal. The parallel serial conversion circuits 24A, 24B, ..., ... output the output signal of this OR circuit 31 through the buffer circuit 32, and thereby the image data classified into each signal line SIG is 1-bit serial data. The signal is output to each signal line SIG (FIG. 7B).

The vertical driver 15 (FIG. 1) has a pixel 2A of the display unit 2 in response to the timing signal generated by the timing generator 14 so as to correspond to the driving of the signal lines SIG by these horizontal drivers 12O and 12E. ) Is selected on a line-by-line basis, and is output to the gate signals GATE0 to GATE5 which sequentially select sub-pixels within each line.

That is, as shown in Fig. 8, the vertical drive unit 15 shifts the timing signal VST (Fig. 7 (C)) in which the signal level rises in synchronization with the vertical synchronizing signal and shift registers (SR) 41A, 41B,... ...) sequentially in the vertical direction. The vertical drive unit 15 select signals ENB0 to ENB5 (D0 to D5 in FIG. 7) in which signal levels sequentially increase cyclically by the AND circuits 42A0 to 42A5, 42B0 to 42B5,... Gate signals GATE0 to GATE5 ((E0) to (E5) in FIG. 7) which are gated by the output signals of the shift registers 41A, 41B, ...) to sequentially select each sub-pixel of each line. The gate signals GATE0 to GATE5 are generated and output to the display unit 2 via the buffer circuits 43A0 to 43A5, 43B0 to 43B5, ....

Thus, the image display device 1 according to the example shown in FIG. 1 classifies one signal line by time division into a plurality of pixels in the vertical direction, and furthermore, time division into sub pixels constituting one pixel. By classifying into one signal line SIG, display and non-display of each sub-pixel are controlled to display a desired image. Moreover, the image display apparatus by such a multi-bit memory system can be widely applied also when using the liquid crystal cell which used the reflection type electrode and the transmission type electrode instead of a reflection type liquid crystal or a transmission type liquid crystal.

However, in this multi-bit memory system, it is necessary to insulate the electrodes between a plurality of sub-pixels constituting one pixel, so that a wasteful area not used for display occurs in one pixel, and as a result 1 There are drawbacks in that the transmittance and reflectance of two pixels are reduced. As a result, there is a problem that images cannot be displayed efficiently.

In addition, the gray scales are expressed by turning on and off sub-pixels having different areas so that the position of the center of gravity of the area related to the display is changed in each pixel according to the luminance of each pixel. There is a drawback that the fixation pattern by is observed. In addition, there is a drawback in that the resolution and the number of gray scales are limited by the processing accuracy of the smallest sub-pixel, and furthermore, there is a drawback in that the resolution and the number of gray scales are limited because it is necessary to provide many semiconductor elements in one pixel. As a result, there is still a problem that is practically insufficient in terms of image quality.

<Start of invention>

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and in a multi-bit memory system, an image display device, an electronic device, a mobile device, and an image display method which solve these problems at one time and can display images with high image quality more efficiently than in the related art. I would like to propose.

In order to solve the above problems, the present invention provides a display unit in which pixels are arranged in a matrix, a vertical driver for outputting a gate signal to the display unit, a horizontal driver for classifying and outputting input image data into signal lines of the display unit, and Applied to an image display device having a timing generator for outputting a timing signal for operation reference to a display unit, the horizontal drive unit, and a vertical drive unit, wherein the input image data is multi-bit image data, and the pixel is output to the signal line. It has a memory part which receives input image data selectively by the said gate signal, and hold | maintains, The gradation is represented by drive of time division according to the said input image data hold | maintained in the said memory part.

According to the structure of this invention, the display part which has arrange | positioned the pixel in matrix form, the vertical drive part which outputs a gate signal to the said display part, the horizontal drive part which classifies and outputs input image data into the signal line of the said display part, the said display part, the said Applied to an image display device having a timing generator for outputting a timing signal for operation reference to a horizontal drive unit and a vertical drive unit, wherein the input image data is multi-bit image data, and the pixel is the input image data output to the signal line. Has a memory section which is selectively inputted and held by the gate signal, and when gray scales are expressed by driving time division according to the input image data held in the memory section, an image is displayed by a multi-bit memory system so that the area is displayed. Compared with the gradation method, a large area of electrodes It may be created, thereby reducing the useless area between the electrodes by, and furthermore it is possible to prevent the occurrence of the fixed pattern. In addition, the limitation of the resolution and the number of gradations due to the processing accuracy of the electrode can be relaxed, and furthermore, the number of semiconductor elements can be reduced, thereby making it possible to display images with high image quality more efficiently than in the prior art in the multi-bit memory system.

Moreover, this invention acquires input image data by an image acquisition means, it applies to the electronic device which displays the said input image data by an image display part, The said image display part is the display part which arrange | positioned the pixel in matrix form, and A vertical driver for outputting a gate signal to a display unit; a horizontal driver for classifying the input image data into signal lines of the display unit; and a timing generator for outputting timing signals for operation reference to the display unit, the horizontal driver, and a vertical driver unit. Wherein the input image data is multi-bit image data, and the pixel has a memory portion for selectively receiving and holding the input image data output to the signal line by the gate signal, and retained in the memory portion. Grayscale by driving time division according to the input image data It expresses.

Thus, according to the configuration of the present invention, it is possible to display images with high image quality more efficiently than in the conventional case in the multi-bit memory system.

Moreover, this invention operates with a battery, acquires input image data by an image acquisition means, and applies it to the portable device which displays the said input image data by an image display part, The said image display part has a pixel in a matrix form. A display unit arranged, a vertical drive unit for outputting a gate signal to the display unit, a horizontal drive unit for classifying and outputting the input image data into signal lines of the display unit, and an operation reference for the display unit, the horizontal drive unit, and the vertical drive unit. A timing generator for outputting a timing signal, wherein the input image data is multi-bit image data, and the pixel has a memory section for selectively receiving and holding the input image data output to the signal line by the gate signal And time minutes according to the input image data held in the memory section. And of expressing gray scales by the drive.

Thus, according to the configuration of the present invention, it is possible to display images with high image quality more efficiently than in the conventional case in the multi-bit memory system.

In addition, the present invention is applied to an image display method of driving pixels arranged in a matrix by corresponding input image data, and displaying an image according to the input image data, wherein the multi-bit memory unit is provided in one pixel. A step of display of expressing the gray scale by driving of time division according to the input image data by driving of image data recording corresponding to the input image data and driving by a time interval corresponding to each bit of the memory unit. Has

Thus, according to the configuration of the present invention, it is possible to display images with high image quality more efficiently than in the conventional case in the multi-bit memory system.

According to the present invention, it is possible to provide an electronic device, a portable device, and an image display method capable of solving the conventional drawbacks at once in image display by a multi-bit memory system and displaying images with high image quality more efficiently than in the past. .

1 is a block diagram showing a conventional image display device.

FIG. 2 is a connection diagram showing a configuration of a pixel of the image display device of FIG. 1. FIG.

3 is a connection diagram illustrating a configuration of a pixel circuit in the pixel of FIG. 2;

4 is a time chart used for explaining the operation of the configuration of FIG. 3;

FIG. 5 is a block diagram showing a horizontal drive unit in the image display device of FIG. 1; FIG.

FIG. 6 is a block diagram showing a parallel serial conversion circuit in the horizontal driver of FIG. 5; FIG.

FIG. 7 is a time chart used for explaining the operation of the horizontal driver of FIG. 5; FIG.

8 is a block diagram showing a vertical drive unit in the image display device of FIG. 1;

Fig. 9 is a block diagram showing the image display device according to the first embodiment of the present invention.

FIG. 10 is a connection diagram showing one pixel applied to the image display device of FIG. 9; FIG.

FIG. 11 is a connection diagram showing a basic configuration of one pixel of FIG. 10; FIG.

12 is a time chart used for explaining the operation of the pixel of FIG.

FIG. 13 is a connection diagram showing an equalization circuit of the configuration in FIG. 10. FIG.

FIG. 14 is a time chart used for explaining the operation of the pixel of FIG. 12; FIG.

Fig. 15 is a connection diagram showing one pixel applied to the image display device according to the second embodiment of the present invention.

Fig. 16 is a connection diagram showing one pixel applied to the image display device according to the third embodiment of the present invention.

Fig. 17 is a connection diagram showing one pixel applied to the image display device according to the fourth embodiment of the present invention.

Fig. 18 is a plan view showing an electrode of a pixel applied to an image display device according to a fifth embodiment of the present invention.

19 is a plan view showing an electrode of a pixel according to an example different from FIG. 18.

20 is a plan view showing an electrode of a pixel by different examples from FIGS. 18 and 19.

Fig. 21 is a connection diagram showing a pixel circuit according to a sixth embodiment of the present invention.

FIG. 22 is a connection diagram showing a pixel circuit according to an example different from FIG. 21. FIG.

FIG. 23 is a connection diagram showing a pixel circuit according to an example different from FIGS. 21 and 22.

Fig. 24 is a block diagram used for explaining the driving of each pixel according to the seventh embodiment of the present invention.

25 is a time chart used for explaining the driving of each pixel in FIG. 24;

Fig. 26 is a block diagram showing the image display device according to the eighth embodiment of the present invention.

FIG. 27 is a connection diagram showing a configuration of one pixel of the image display device of FIG. 26; FIG.

FIG. 28 is a connection diagram used for explaining writing to many system sides in the configuration shown in FIG. 27; FIG.

29 is a plan view showing a blanking indication;

30 is a plan view showing display by superimposition;

Fig. 31 is a block diagram showing an image display device according to a ninth embodiment of the present invention.

FIG. 32 is a schematic diagram used for explaining stereoscopic display by the image display device of FIG. 31; FIG.

33 is a time chart used for explaining the configuration of the image display device according to a tenth embodiment of the present invention;

34 is a block diagram showing an image display device according to a eleventh embodiment of the present invention.

FIG. 35 is a connection diagram showing a configuration of a pixel in the image display device of FIG. 34; FIG.

36 is a block diagram showing the configuration of a horizontal drive unit in the image display device of FIG.

FIG. 37 is a block diagram showing a configuration of a vertical drive unit in the image display device of FIG. 34; FIG.

FIG. 38 is a time chart used for explaining an operation by a multi-bit memory system in the image display device of FIG. 34; FIG.

FIG. 39 is a time chart used for explaining an operation during analog signal driving in the image display device of FIG. 34; FIG.

40 is a time chart used for explaining operation switching in the image display device of FIG. 34;

Fig. 41 is a plan view showing a display screen of the image display device according to a twelfth embodiment of the present invention.

<Best Mode for Carrying Out the Invention>

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail, referring drawings suitably.

(1) Configuration of Example 1

9 is a block diagram showing an image display device according to Embodiment 1 of the present invention. The image display device 51 displays an image by video data output from a tuner unit, an external device, or the like, which is not illustrated, for example, on the display unit 52 by a multi-bit memory system. In addition, in the image display apparatus 51 shown in this FIG. 9, the structure similar to the image display apparatus 1 mentioned above with respect to FIG. 1 is attached | subjected with the code | symbol, and the overlapping description is abbreviate | omitted.

The display unit 52 is a reflective liquid crystal display panel or a transmissive liquid crystal display panel, and is formed by arranging pixels in which red, green, and blue color filters are arranged in a matrix. As shown in FIG. 10, the configuration of one pixel 52A of the display unit 52, the pixel 52A is disposed at a portion where one electrode 53 by a large area is used for display. The liquid crystal cell is formed using this electrode 53. In addition, the pixel circuit 54 is provided in each pixel 52A, and the gray level is represented by the drive of the electrode 53 by this pixel circuit 54.

Here, as an example in which the gray scale is represented by two bits, the configuration of the pixel circuit 54 is illustrated in FIG. 11, and each pixel 52A is, for example, in a frame period as shown in FIG. 12. As a result, the common voltage VCOM (FIG. 12A) to which the signal level is switched is applied to the common electrode of each liquid crystal cell 55. The pixel circuit 54 is connected to the common voltage VCOM and the in-phase driving signal FRP through the switch circuit 56 made up of the NMOS transistor Q51 and the PMOS transistor Q52 in which the source and the drain are commonly connected, respectively (Fig. 12 (B)). ) And a drive signal XFRP inverse to the common voltage VCOM (FIG. 12) via a switch circuit 57 comprising an NMOS transistor Q53 and a PMOS transistor Q54 having electrodes 53 connected to each other and similarly connected to a source and a drain. The electrode 53 is connected to (C)).

As a result, the pixel circuit 54 controls the switch circuits 56 and 57 on and off complementarily to switch the display and the non-display of the liquid crystal cell 55. In addition, the pixel circuit 54 controls each of these switch circuits 56 and 57 to be complementarily on and off by time division by the drive circuits 58A and 58B respectively responsible for displaying each bit of image data. The gray scale is represented by time division driving by the drive circuits 58A and 58B. More specifically, the drive time of the switch circuits 56 and 57 by these drive circuits 58A and 58B is set so as to correspond to the bits of the image data that the drive circuits 58A and 58B are responsible for, thereby making it possible to time-division By this, the liquid crystal cell 55 by the one electrode 53 is driven.

Here, the driving circuits 58A and 58B are configured in the same manner except that the bits that are in charge and the signals related to the control are different from each other. Hereinafter, only the driving circuit 58A will be described. Omit. Here, the driving circuit 58A is similar to the CMOS inverter 60 including the NMOS transistor Q56 and the PMOS transistor Q57 with the gate and the drain connected in common, and similarly, the NMOS transistor Q58 and the PMOS transistor with the gate and the drain connected in common. A CMOS inverter 61 made of Q59 is provided in parallel between the positive side power line VDD1 and the negative side power line VSS, and these CMOS inverters 60 and 61 are connected in a loop shape so that the memory 62 having the SRAM configuration is connected. Is formed.

In addition, a switch circuit 64 is provided by an NMOS transistor Q61 which operates on and off by the gate signal GATE and writes the logic value of the signal line SIG into the memory 62. The output of this memory 62 is selected by the selection signal SEP. The switch circuits 65 and 66 by the NMOS transistors Q65 and Q66 which selectively output to the switch circuits 56 and 57 are provided. As a result, this pixel circuit 54 can be represented by an equalization circuit shown in FIG.

As shown in FIGS. 12D and 12D, the pixel circuits 54 are driven by increasing signal levels in the selection signals SEP0 and SEP1 supplied to the respective driving circuits 58A and 58B. The ratios of the periods T0 and T1 which leave the control of the switch circuits 56 and 57 to the circuits 58A and 58B, respectively, are set at a ratio corresponding to each bit of the input image data. The ratio of the periods T0 and T1 is set to 1: 2. The input of the logic value from the signal line SIG is input to each of the driving circuits 58A and 58B by serial data in the same manner as in the case of the pixel circuits 4A to 4F described with reference to FIG. By SEP0 and SEP1, the logic value of the lower bit of the image data is selectively inputted to the drive circuit 58A on the shorter side in which control of the switch circuits 56 and 57 is short, and is higher than the remaining drive circuit 58B. The logic value of the side bit is optionally input.

As a result, the pixel circuit 54 writes and holds the input image data in the memory portion constituted by the memory 62 of the driving circuits 58A and 58B, and controls the time division according to the input image data held in the memory portion. By driving, the gray level of the input image data by two bits is expressed using the integration effect in the time axis direction (Fig. 12 (E)).

According to such a gradation representation principle, six drive circuits 58A to 58F are provided in the pixel 52A of the image display device 51 (Fig. 10) so that the gradation by 6 bits can be expressed. The control time of the switch circuits 56 and 57 by the drive circuits 58A-58F is set by the selection signals SEP0-SEP5 according to the bit which each drive circuit 58A-58F is in charge of display.

That is, in the image display device 51 (Fig. 9), the timing generator 71, as shown in Fig. 14, controls the common voltage VCOM, the drive signal FRP, and XFRP (Figs. 14A to 14C). Create and print In addition, the selection signals SEP0 to SEP5 ((D1) to (D6) in FIG. 14) for giving control of the switch circuits 56 and 57 to the respective drive circuits 58A to 58F, respectively, are sequentially selected between periods of one frame. The selector signals SEP0 to SEP5 are generated so that the periods T0 to T5 in which the signal levels of the select signals SEP0 to SEP5 increase are increased to powers of 2 as they move from the lower bits to the upper bits, respectively. . Thus, in this example, in the selection signal SEP0 associated with the lowest bit, in the period T0 in which the signal level is rising, SEP1 through SEP5 in relation to the higher side are the periods T1 to T5 in which the signal level is rising. Are set to periods of 2, 4, 8, 16, and 32 times, respectively (FIG. 14E). In this image display device 51, these timing generators 71, horizontal drive units 120, 12E and the like are integrally formed on the glass substrate of the display unit 52. As shown in FIG.

(2) Operation of Example 1

In the above configuration, the image display device 51 (FIG. 9) has image data SDI by serial data input via the interface 11 separated into odd lines and even lines, respectively, to the horizontal drive units 12O and 12E. Inputted to the signal line SIG of the display unit 52 (FIG. 5), and then converted into serial data by one bit and output to each signal line SIG of the display unit 52 (FIG. 6). In addition, the gate signal GATE is generated and supplied to the display unit 52 by the vertical driver 15 so as to correspond to the driving of the signal line SIG by the horizontal drivers 12O and 12E, thereby providing a higher level than the horizontal drivers 12O and 12E. The image data output to the signal line SIG is sequentially input to the corresponding pixels and used for display. Thereby, in this image display apparatus 51, the image by image data SDI is displayed on the display part 52. As shown in FIG.

In each pixel 52A of the display unit 52 (FIGS. 10, 11 and 13), the counter electrode is formed by one large electrode 53 to form a liquid crystal cell 55, and the switch circuit 56, By complementary on-off control of 57, the common voltage VCOM and in-phase driving signal FRP applied to the common electrode of the liquid crystal cell 55 and the reverse phase driving signal XFRP are selectively applied to the electrode 53. As a result, in the case of constituting the liquid crystal cell 55 by normally black, the in-phase driving signal FRP is applied to the electrode 53 by the control of the switch circuits 56 and 57 so that the pixel 52A is made non-displayed. In this case, the reverse-phase driving signal XFRP is applied to the electrode 53 so as to be in the display state.

The image display device 51 is a memory provided with a logic value of image data output to the signal line SIG by bit serial under control by the gate signals GATE0 to GATE5 provided in the drive circuits 58A to 58F for each bit. It is written sequentially at 62. In addition, the periods during which the switch circuits 56 and 57 are controlled by the written logic values, and the control of the switch circuits 56 and 57 to the respective drive circuits 58A to 58F are set by the selection signals SEP0 to SEP5. Each of the driving circuits 58A to 58F is set to correspond to the bits of the image data responsible for driving. Specifically, as the driving circuits 58A to 58F in charge of the upper layer become, the period in charge of driving increases by power of two.

As a result, the image display device 51 records the input image data in the memory unit of each pixel 52A and expresses the gray scale by driving time division according to the input image data held in the memory unit.

That is, in each pixel 52A, the periods of display and non-display are switched in accordance with the logic values of the respective bits recorded in the memory 62 of these drive circuits 58A to 58F, and the integration effect of the human eye is changed. The gray level corresponding to the number of bits of the image data SDI can be expressed. As a result, the image display device 51 can drive the liquid crystal cell 55 by a multi-bit memory system, and can express gray scales corresponding to the number of bits of the image data SDI. Since there is no need to provide a conversion circuit or the like, an image can be displayed with a simple configuration as a whole. In addition, power consumption can be reduced by not necessarily writing image data for each frame.

In this way, while displaying an image by a multi-bit memory system, in this image display device 51, one pixel 52A is formed by one electrode 53, and time division of driving of the electrode 53 is performed. By expressing the gray scales by switching to, the useless area not used for display between sub-pixels, such as the multi-bit memory system based on the area gray scale method described above with respect to FIG. 1, can be omitted. The fall of the transmittance | permeability and reflectance in a pixel can be prevented, and an image can be displayed efficiently.

In addition, since one pixel 52A can be configured by one electrode 53, it is possible to prevent a change in the position of the center of gravity due to the gray scale by the area gray scale method, thereby preventing the occurrence of a fixed pattern. Can be. In addition, the limitation of the resolution and the number of gray scales due to the processing accuracy of the smallest sub-pixel can be avoided. Also, as in the case of the multi-bit memory system, instead of providing switch circuits related to switching of in-phase and reverse-phase driving signals for each bit, the output of the memory 62 allocated to each bit is selectively switched circuit 56. By allocating the switch circuit outputted to the device 57 to each bit, the overall structure can be simplified by reducing the number of semiconductor elements, and the limitation of the resolution and the number of gray scales by the number of semiconductor elements can be avoided. Specifically, four transistors Q6 to Q9 (FIG. 3) are omitted from each bit, and instead, four transistors Q51 to 54 constituting the switch circuits 56 and 57 as a whole, and two transistors Q65 to each bit. By providing Q66, in the six-bit gray scale representation according to this embodiment, it is possible to reduce to 46 the number of 54 transistors required in the multi-bit memory system based on the area gray scale system.

As a result, images can be displayed with high image quality more efficiently than in the related art.

As a result, in the image display device 51 according to the present embodiment, gray scales are expressed by controlling the pulse width of the drive signal applied to the liquid crystal cell, and in the gray scale expression by this method, STN (Super Twisted) is conventionally used. Nematic) There is a gray scale expression method using a pulse width modulation method of liquid crystal. However, the pulse width modulation method of the STN liquid crystal is fundamentally different in that the driving method according to this embodiment is a multi-bit memory method, whereas the pulse width modulation method of the STN liquid crystal is driving of the display unit by the analog method.

(3) Effect of Example 1

According to the above structure, the input image data is recorded in the memory section of each pixel, and the gray scale is expressed by driving the time division according to the input image data held in the memory section, thereby making it conventionally possible to display images by the multi-bit memory system. In comparison, images can be displayed with high image quality efficiently.

More specifically, in each pixel, a plurality of one-bit memories for acquiring and recording logical values of the respective bits of the input image data are provided in each pixel, and in a period corresponding to the bit position of the input image data in charge of the plurality of memories, Each of the plurality of memories is selectively outputted by the switch circuit, and the output signal of the switch circuit switches the signal to be applied to the electrode of the pixel. I can display it.

In addition, the horizontal drive unit outputs the input image data to the signal line by serial data using the bit serial, and writes the logic value of each bit of the input image data in the memory at each pixel to use for display, thereby reducing the number of wiring lines of the signal line. It can reduce and simplify the structure of a display part.

(4) Example 2

FIG. 15 is a connection diagram showing one pixel of a display unit applied to the image display device according to the second embodiment of the present invention in contrast with FIG. 10. In the image display device according to this embodiment, an electrode 83 associated with this pixel 82A is formed by using a transparent electrode and a reflective electrode in combination. The image display device according to this embodiment is configured similarly to the image display device 51 of the first embodiment except that the configuration of these pixels is different.

According to this embodiment, even when the electrode of the liquid crystal cell is prepared by using the transparent electrode and the reflective electrode in combination, the same effects as in the first embodiment can be obtained.

(5) Example 3

FIG. 16 is a connection diagram showing one pixel of the display unit applied to the image display device according to the third embodiment of the present invention in contrast with FIG. 10. In the third embodiment, gradation is expressed by combination with the area gradation method. For this reason, in this embodiment, the electrodes of the liquid crystal cell are formed of a plurality of sub-electrodes, and in each bit of the input image data, the multiplication value of the area of the sub-electrode used for display and the length of the driving period is respectively a bit. It is set to be in a power-of-power relationship of two corresponding to the position.

That is, the pixel 92A is formed by three sub-electrodes 93A, 93B, 93C, which are smaller than the number of bits of the image data. These three sub-electrodes 93A, 93B, and 93C have an area of two powers and an area ratio of 1: 2: 4.

Each sub-electrode 93A, 93B, 93C is provided with two-bit pixel circuits 54A, 54B, 54C, respectively, and in each pixel circuit 54A, 54B, 54C, drive circuits 58A, 58B, respectively. The length of the period for letting the control of the switch circuits 56 and 57 be controlled is set to 1: 8, and the selection signals EPO and EP1 are supplied from the timing generator so as to correspond thereto.

In addition, from the smallest sub-electrode 93A to the sub-electrodes 93B and 93C on the larger area, three bits are sequentially assigned from the least significant bit of the input image data, and the subsequent upper three bits are sequentially. Is assigned. The image display apparatus according to this embodiment is configured in the same manner as the image display apparatus according to the above-described embodiment except that these configurations are different from each other.

According to this embodiment, by expressing the gray scale in combination with the area gray scale method, the kind of the selection signal SEP can be reduced, so that the wiring can be simplified and the layout efficiency can be improved. Can be obtained. In addition, the degree of freedom in pixel design can be increased by combining with the area gradation method.

(6) Example 4

FIG. 17 is a connection diagram showing one pixel of a display unit applied to the image display device according to the fourth embodiment of the present invention, in contrast with FIG. 16. In the image display device according to this embodiment, the sub-electrodes 103A, 103B, and 103C associated with this pixel 102A are formed by using a transparent electrode and a reflective electrode together. The image display device according to this embodiment is configured in the same manner as the image display device according to the above-described embodiment except that the configuration of these pixels is different.

According to this embodiment, even when the electrode of the liquid crystal cell is prepared by using the transparent electrode and the reflective electrode in combination, the same effect as in the third embodiment can be obtained.

(7) Example 5

18-20 is a top view which shows the gradation representation method by the combination with the area gradation method by another example different from Example 3, Example 4. FIG. The gradation representation by the combination with the area gradation method has a power of 2 where the multiplication value between the area of the sub-electrode used for display and the length of the driving period is in each bit of the input image data. Various combinations are conceivable, and in the example of FIG. 18, the area ratio of the sub-electrodes is set to 1: 4: 16, and the length ratio of the driving period is set to 1: 2. 19 is a case where the area ratio of the sub-electrodes is set to 1: 8 and the length ratio of the driving period is set to 1: 2: 4, and in FIG. 20, the area ratio of the sub-electrodes is set to 1: 2. This is the case where the length ratio of the driving period is set to 1: 4: 8. The image display apparatus according to this embodiment is configured in the same manner as the image display apparatus according to the above-described embodiment except that these configurations are different from each other.

As in this embodiment, even if the area ratio of the sub-electrodes and the length ratio of the driving period are changed in various ways, the same effects as in the third and fourth embodiments can be obtained.

(8) Example 6

21-23 is a connection diagram which shows the structure of the other drive circuit of a liquid crystal cell by contrast with FIG. Here, in the time division driving of the liquid crystal cell, various configurations can be applied. In the example of FIG. 21, the drive signal of the switch circuit 57 is inverted by the inverter 110 to drive the switch circuit 56. The switch circuit 65 is omitted, with the output from the drive circuits 118A and 118B as one system. 22, the drive signal of the switch circuit 56 is inverted by the inverter 120 to drive the switch circuit 57, and the output from the drive circuits 128A and 128B is one system, and the switch circuit is shown. (66) is omitted. FIG. 23 replaces the switch circuits 56 and 57 and the inverter 120 in FIG. 22 with the exclusive OR circuit 131 and generates the drive signal XFRP from the drive signal FRP in the pixel circuit. . The image display apparatus according to this embodiment is configured in the same manner as the image display apparatus according to the above-described embodiment except that these configurations are different from each other.

Like these examples, even if various configurations are applied to the driving circuit of the liquid crystal cell, the same effects as in the above-described embodiments can be obtained.

(9) Example 7

24 is a plan view showing a configuration of a display unit applied to the image display device according to the seventh embodiment of the present invention. The image display device according to this embodiment is configured in the same manner as in the above-described embodiment except that the configuration of the display unit 142 is different.

In this embodiment, the phases of the selection signals SEP0 to SEPN (SEP00 to SEPN0, SEP01 to SEPN1, SEP02 to SEPN2, ...) for controlling the drive by time division of the liquid crystal cell are set different from each other in the adjacent lines. This prevents flicker. Here, the method of changing the phases for each line may be such that the polarities of the selection signals SEP0 to SEPN may be reversed for each line, and as shown in FIG. 25, the selection signals SEP0 to one line for each line as shown in FIG. 25. The phases of the SEPNs may be shifted sequentially or they may be combined. In addition, the phases of these selection signals SEP0 to SEPN may be different from each other on the same line of successive frames.

As in this embodiment, by setting the phase of the selection signal for controlling the drive so as to be different from each other in the adjacent lines by time division of the liquid crystal cell, the flicker can be prevented and the same effect as in the above-described embodiment can be obtained.

(10) Example 8

FIG. 26 is a block diagram showing an image display device according to Embodiment 8 of the present invention in contrast with FIG. 9. The image display device 181 is, for example, a portable device such as a mobile phone, an electronic still camera, a video camera, or the like, and controls the overall operation by executing a program recorded in a memory (not shown) in response to an operation by a user. By the control of the controller 184, the display of the display unit 182 is switched.

Here, as shown in Fig. 27, the display unit 182 records the first data by the drive circuits 58AA, 58AB, ..., which drive the switch circuits 56, 57 by recording the image data output to the signal line SIG. The drive circuit group 186B according to the second system by the drive circuits 58BA, 58BB, ..., which drive the switch circuits 56 and 57 by recording the image data similarly to the drive circuit group 186A by the control circuit 186A The drive circuit is provided by two systems, and the switch circuits 56 and 57 are controlled by the output of these two drive circuits 58AA, 58AB, ..., 58BA, 58BB.

Correspondingly, the timing generator 183 (Fig. 26) is controlled by the controller 184 so as to correspond to these two systems of drive circuits 58AA, 58AB, ..., 58BA, 58BB, .... Select signals SEP0A to SEP5A and SEP0B to SEP5B are selectively outputted, whereby the drive circuits 58AA, 58AB, ..., 58BA, 58BB, ... are connected by the two circuits. Switch control.

That is, when a user is instructed to display a moving image by, for example, an imaging result or the like, as shown in FIG. 27, the switch circuits 56 and 57 are driven by the drive circuits 58AA, 58AB, ..., which are related to the first system. The select signals SEP0A to SEP5A and SEP0B to SEP5B are outputted to control. Further, when a display such as an electronic mail is instructed by the user, as shown in FIG. 28 in contrast with FIG. 27, the switch circuits 56, 57 are driven by the drive circuits 58BA, 58BB, ..., etc. of the second system. Outputs the selection signals SEP0A to SEP5A and SEPOB to SEP5B.

In this way, the interface (I / F) 185 is driven by the control of the controller 184, from the video data SDI and the image data DV generated by the controller 184. These two drive circuit groups 186A and 186B are used. The image data DATAA and DATAB associated with the data are output by time division. In addition, the vertical drive unit 186 outputs the gate signals GATEA and GATEB of the respective systems so as to correspond to the output of the image data DATAA and DATAB under the control of the same controller 184.

On the other hand, when an abnormality is detected by monitoring of the operation | movement of each part, the controller 184 produces | generates image data DV which displays the symbol, a message, etc. which recommend the detected abnormality to a user. Further, under the control of the timing generator 183, as shown in FIG. 29, this image data DV (DATAA) is stored in one of these two system drive circuit groups 186A and 186B. Furthermore, image data DV obtained by inverting the gradation of the image data DV is generated, and the image data DV (DATAB) in which the gradation is inverted is stored in the other system. When the image data is stored in each system in this manner, the control signal of the timing generator 183 switches the selection signals SEPA and SEPB in plural frame periods, thereby outputting plural frames of image display by two system driving circuits. It is switched by the cycle, and this recommended mark is indicated by blanking.

As shown in Fig. 30, for example, when the remaining battery power is low, and when the remaining capacity of the recording medium is small, one of these two systems displays an image by video data SDI. Then, image data DV for displaying a sign, a message, etc. to warn the user of these situations is generated, and the image data DV is stored in one remaining system. In the storage of the image data DV, for example, the image data DV may be executed in one or a plurality of vertical blanking periods. Furthermore, only one frame period stops writing of the video data SDI and executes in this stopped period. You may also do so.

In this case, when the controller 184 stores the image data DV in the remaining one system in this way, the display is switched in these two systems by the frame period, and the characters according to this warning are displayed on the image by the moving image. Superimpose and mark, and the like.

According to this embodiment, the memory unit for recording image data and the driving unit for driving the liquid crystal cell in time division by recording the memory unit are provided in each pixel, so that the display can be switched in these two systems for various functions. By ensuring that the same effects as in the above-described embodiment can be obtained.

(11) Example 9

FIG. 31 is a block diagram showing an image display device according to a ninth embodiment of the present invention in contrast with FIG. 26. This image display device 191 is a monitor device, for example, and receives video data SDI. In addition, video data SDI is video data used for stereoscopic display here, and image data for right eye and left eye are video data which alternately continuous in a frame period. The image display device 191 is configured in the same manner as the image display device 181 described above with respect to the eighth embodiment except that the configuration related to this video data SDI is different. The image display device 191 alternates the image data for the right eye and the left eye of the video data SDI used for this stereoscopic display in the frame period to the two system drive circuit groups 186A and 186B provided in the display unit 182. The display unit 182 alternately displays images by the image data stored in the two cycles and recorded in the two drive circuit groups 186A and 186B in the frame period.

This image display device 191 controls the operation of the parallax generating mechanism 196 by the controller 194 in conjunction with the switching of the display, whereby the display image for the right eye as shown in FIG. 182R) and disparity are set to the display image 182L for the left eye, and the viewer is provided with the image for the right eye and the left eye by the video data SDI. Moreover, such a parallax generating mechanism 196 can apply various mechanisms, such as the mechanism which used the deflection of light widely, for example.

In this embodiment, a memory unit for recording image data and a driving unit for driving a liquid crystal cell by time division by recording the memory unit are provided in two systems, and used for stereoscopic vision, thereby producing the same effects as in the above-described embodiment. You can get it.

(12) Example 10

Here, in the above-mentioned embodiment, although the drive by time division of each liquid crystal cell is performed in a frame period, you may set the period of this drive to several frames. As described above, when each liquid crystal cell is driven by time division for a plurality of frame periods, a time margin occurs for outputting image data to each signal line SIG. As a result, in this embodiment, this temporal margin is effectively used to express more gradations in a few drive circuits.

As a result, the image display device according to this embodiment is configured such that the pixels of the display portion correspond to the two-bit gray scales shown in Fig. 11, and express the gray scales by four bits. In this embodiment, the display unit and the configuration associated with the display unit are the same as those of the image display unit described above with respect to the first embodiment except that the configuration associated with the display unit is different, and the configuration of FIG. .

As shown in FIG. 33, in this embodiment, the horizontal driving units 12O and 12E are the least significant bit B0 of the image data by four bits, and two bits from the least significant bit B0 in the first frame of three consecutive frames. By the bit serial, the bit B2 that is higher by the bit is output to the signal line SIG, and in the subsequent two frames, the remaining bits B1 and B3 are output to the signal line SIG by the bit serial (Fig. 33 (A)).

The timing generator 71 divides the period of the first frame into a period of 1: 4, and in the subsequent two frame periods, similarly, the selection signal SEP0 to divide the period of these two frames into a period of 1: 4. , SEP1 is output (FIGS. 33B and 33C). In this embodiment, the period of two subsequent frames is divided into a period of 1: 4 by repetition of the selection signal output from this head frame.

The display unit 52 thereby acquires each bit B0 and B2 of the input image data output to the signal line SIG in the head frame to the drive circuits 58A and 58B, respectively, and uses them for driving the switch circuits 56 and 57. FIG. In the subsequent two frame periods, the bits B1 and B3 of the input image data output to the signal line SIG are respectively acquired by the driving circuits 58A and 58B and used for driving the switch circuits 56 and 57.

Thus, in this embodiment, by repetition of time division driving in three consecutive frames, a desired image is displayed by setting the period used for the display of each bit B0 to B3 in a relationship of 1: 2: 4: 8.

As in this embodiment, the entire structure can be further simplified by driving in time division according to the input image data by repetition by a plurality of frames.

(13) Example 11

FIG. 34 is a block diagram showing the image display device according to the eleventh embodiment of the present invention in contrast with FIG. 9. The image display device 201 is applied to, for example, a portable device operated by a battery such as a mobile phone, and when high gradation is required, the display unit 202 displays an image by driving with an analog signal. . On the other hand, when a high gradation such as text display such as an e-mail is unnecessary, and furthermore, when displaying power consumption at all times as in the display of a standby screen, the display unit 202 uses a multi-bit memory method with a small number of bits. Image display. For this reason, in this image display apparatus 201, the display part 202 etc. are comprised so that the switching of this drive system may be carried out. In this embodiment, the same configuration as in the above-described embodiment is denoted by the corresponding reference numerals, and redundant description is omitted.

35 is a connection diagram showing a configuration of one pixel of the display unit 202. This pixel 202A is provided with a configuration used for driving by an analog signal, in addition to the configuration by the 2-bit memory system described above with respect to FIG. In other words, the pixel 202A has two-bit outputs of the switch circuits 56 and 57 by the pixel circuit 54A through the switch circuit 203 for digital drive switching by the NMOS transistor Q200. 55).

The liquid crystal cell 55 is provided with a storage capacitor CS1 and is connected to the signal line SIG via a switch circuit 204 of the NMOS transistor Q201 that is turned on and off by the gate signal AGATE for analog drive switching. As a result, the pixel 202A sets the switch circuit 204 for the analog drive switching and the switch circuit 203 for the digital drive switching to an off state and an on state, respectively. The liquid crystal cell 55 is driven. On the other hand, on the contrary, the switch circuit 204 for analog drive switching and the switch circuit 203 for digital drive switching are set to the on state and the off state, respectively, and the gray level corresponding to the signal level of the drive signal output to the signal line SIG is set. By this, the liquid crystal cell 55 is driven.

The horizontal driving units 20 O and 206 E selectively output drive signals and input image data related to analog signal driving to signal lines SIG of odd lines and even lines of the display unit 202, respectively. That is, as shown in Fig. 36, the horizontal driving units 20O and 206E sequentially line the timing signal HST rising at the timing of the start of the horizontal scanning period by the shift registers SR (21A, 21B, ...). Direction, and the image data DATA is latched by the sampling latches SL (22A, 22B, ...) according to the timing signals output from the respective shift registers 21A, 21B, .... Is classified into the corresponding signal line SIG.

In addition, the latch results of these sampling latches 22A, 22B, ... by the second latches 23A, 23B, ... are latched and output, respectively, thereby matching the timing of the image data classified by the respective signal lines SIG. In parallel, the parallel serial conversion circuit (PS) 210A, 210B,... Is input to 6 bits output from the second latches 23A, 23B, ..., by the timing signal SERI output from the timing generator 205. The lower two bits of the image data are selectively acquired and converted into serial data.

The horizontal driving units 20O and 206E further convert digital image data by 6 bits outputted from the second latches 23A, 213B, ... by the digital analog conversion circuits (DACs) 211A, 211B,... The conversion process outputs the drive signal according to the analog signal drive.

The parallel drivers 206O and 206E are parallel serial via the switch circuits 213A and 214A, 213B and 214B,. Output data of the conversion circuits 210A, 210B, ..., and drive signals related to analog signal drive output to the digital analog conversion circuits 211A, 211B, ..., are selectively outputted to the signal line SIG.

As shown in FIG. 37, the vertical driver 207 sequentially shifts the timing signal VST in which the signal level rises in synchronization with the vertical synchronization signal in the vertical direction by the shift registers SR (41A, 41B, ...). send. The vertical driver 207 writes the lower bits and the upper bits in the AND circuits 211A to 211C, respectively, in the analog signal drive selection signal AENB and the multi-bit memory type drive output from the timing generator 205. Gate signals AGATE, DGATE0, which instruct the selection signals DENB0 and DENB1 to be instructed by the output signals of the shift registers 41A, 41B, ..., thereby selecting the respective bits of the analog signal drive and the multi-bit memory drive. DGATE1 is generated, and the gate signals AGATE, DGATE0, and DGATE1 are outputted to the display unit 202 through the buffer circuits 212A to 212C, respectively.

As a result, in this image display device 201, as shown in FIG. 38, the timing signals SERI0 and SERI1 (in FIG. 38) are set with the selection signal level SEL (FIG. 38A) set to the H level. Second latches 23A, 23B,... In synchronization with (B) and (C)); … 2 bit Lout0 and Lout1 of the image data latched in the circuit) are alternately output to the signal line SIG (Fig. 38 (D)). Further, the timing signals VST outputted from the shift register 41A by the selection signals DENB0 and DENB1 (FIG. 38 (F) and (G)) instructing the writing of the lower and upper bits, respectively, from the vertical driver 207. Gated by (E) in FIG. 38, gate signals DGATE0 and DGATE1 ((H) and (L) in FIG. 38) are output, and drive circuits 58A and 58B are respectively driven by these gate signals DGATE0 and DGATE1. Each bit of the image data output to the signal line SIG is recorded, and the liquid crystal cell 55 is driven by this recording.

On the other hand, as shown in Fig. 39, in the state where the selection signal level SEL (Fig. 39 (A)) is set to the L level, the drive signal by the digital-to-analog conversion circuits 211A, 211B, ..., is the signal line SIG. 39 (B), and the selection signal AENB (FIG. 39 (D)) for selecting analog signal driving is output to the timing signal VST (FIG. 39 (C)) output from the shift register 41A. By the gate signal AGATE (Fig. 39E), and the liquid crystal cell 55 is driven by the drive signal output to the signal line SIG by the gate signal AGATE.

FIG. 40 is a time chart showing a case where the drive is switched from analog drive to analog signal drive at time t1 in contrast with FIGS. 38 and 39.

As a result, the timing generator 205 generates and outputs various timing signals necessary for these operations to the horizontal driving units 20 O and 206 E, the vertical driving unit 207 and the display unit 202 under the control of the controller 208. .

The controller 208 is a control means for controlling the overall operation by executing a program recorded in a memory (not shown) in response to an operation by the user. When the user instructs the acquisition of an imaging result, the controller 208 Control to obtain the imaging result. The controller 208 inputs the video data SDI of the moving image and the still image according to this imaging result into the interface 11 and controls the operation of the timing generator 205 to operate by analog signal driving. The imaging result is recorded and held in a memory (not shown), and when the display of the recorded and held imaging result is instructed by the user, the imaging result is similarly displayed on the display unit 202. As a result, the controller 208 controls the entire operation to display an image on the display unit 202 by driving with an analog signal when a display with a high gradation is required.

On the other hand, in the standby screen display and the electronic mail display, the operation of the timing generator 205 is switched to display by the multi-bit memory system, thereby reducing the power consumption.

According to this embodiment, an analog signal drive configuration is provided and the display is switched so that the image can be displayed at high image quality while reducing the power consumption, and the same effect as in the first embodiment can be obtained.

(14) Example 12

Fig. 41 is a plan view showing a display screen of the image display device according to the twelfth embodiment of the present invention. The image display device according to this embodiment is applied to a mobile phone, and in the configuration of the image display device 201 described in Embodiment 11, the display screen is controlled by the timing generator 205 by the controller 208. Is divided into two areas ARA and ARB in the vertical direction, and the area ARA on the upper side of the screen is set as the partial display area.

Here, the partial display area is a display area for information which always needs to be notified of the status of the device, and for example, information such as remaining battery capacity and electric field strength is displayed.

In this embodiment, the controller 208 sets the operation of the timing generator 205 to display this partial display area ARA by the above-described multi-bit memory system. Moreover, only when the information in display is required to be updated, the image data recorded in the drive circuit related to this multi-bit memory system is updated, and power consumption is reduced by that amount.

On the other hand, in the remaining area ARB, the image is displayed by analog signal driving.

According to this embodiment, the image display is performed by a multi-bit memory system on a part of the display screen, and the image display by analog signal driving is performed, whereby power consumption can be reduced, and the same effect as in the eleventh embodiment can be obtained. In this case, the configuration of the display unit may be configured to be dedicated to each area so as to correspond to the switching of the display system by this area.

15.Other Embodiments

In the above-described embodiment, the case where the input image data of 2 bits or 6 bits is displayed by the multi-bit memory system has been described. However, the present invention is not limited to this, and the image data according to various bits is displayed. It is also widely applicable.

In the above-described embodiment, the case where the memory is provided in each drive circuit by the configuration of the SRAM has been described. However, the present invention is not limited to this, and various configurations such as the case of applying a memory using a DRAM, for example, are described. Can be widely applied.

In addition, in the above-described embodiment, the case where the input image data by the 6-bit red, green, and blue color data is received and the image is displayed is described. However, the present invention is not limited to this, and the present invention is not limited to this. Therefore, the present invention can be widely applied to a case where a color image is displayed.

Moreover, in the above-mentioned embodiment, although the case where this invention is applied to the liquid crystal display device which forms a display part etc. on a glass substrate was demonstrated, this invention is not limited to this, The EL (Electro Luminescence) display apparatus, etc. are various. Widely applicable to kinds of display devices.

The present invention can be applied to, for example, a liquid crystal display device using a multi-bit memory system.

Claims (16)

A display unit in which pixels are arranged in a matrix shape, a vertical driving unit for outputting a gate signal to the display unit, a horizontal driving unit for classifying and outputting input image data into signal lines of the display unit, the display unit, the horizontal driving unit, and the vertical driving unit An image display apparatus having a timing generator for outputting a timing signal for operation reference, The input image data is multi-bit image data, The pixel, A memory section for selectively receiving and holding the input image data output to the signal line by the gate signal, A gray level is represented by driving time division according to the input image data held in the memory unit. The method of claim 1, The memory unit, A plurality of one-bit memories each obtaining and retaining logical values of respective bits of the input image data; And a switch circuit for a memory output for selectively outputting respective recordings of the plurality of memories in a period corresponding to the bit position of the input image data in charge of the plurality of memories, The pixel, And a drive circuit for switching a drive signal for switching a signal applied to an electrode of the pixel by an output signal of the switch circuit for memory output. The method of claim 1, The horizontal drive unit, Outputting the input image data to a corresponding signal line by serial data, The vertical drive unit, Outputs a plurality of gate signals whose signal levels rise sequentially in synchronization with the serial data, The pixel, And the logical values of the respective bits of the serial data are sequentially obtained by the plurality of gate signals and recorded in the memory unit. The method of claim 1, The pixel, It has a plurality of sub-pixels which are small in number compared with the number of bits of the said input image data, and the area of the site | part used for display differs, And the gray scale corresponding to the input image data is driven by driving the time division of the sub-pixel according to a logic value of a bit corresponding to the input image data held in the memory unit. The method of claim 1, The pixel, An image display device characterized by being different in phase with respect to driving of the time division between adjacent lines. The method of claim 1, The pixel, Having a plurality of systems of the said memory part, An image display device, wherein the input image data used for driving the time division is switched by the plurality of systems. The method of claim 6, The image display apparatus characterized by the display of the image by blanking being the display of the image by switching of the said some system. The method of claim 6, The image display apparatus characterized by the display of the image by superimposing the display of the image by switching of the said some system. The method of claim 1, And the time division driving is a display in which a period of one frame is repeated. The method of claim 1, And the drive of the time division is a display in which a period of the plurality of frames is divided into a plurality of frames in which the driving by each bit of the input image data is classified as a repetition period. The method of claim 1, The horizontal drive unit, A digital analog converter for outputting an analog signal by digitally analog converting the input image data; A selection circuit for outputting the analog signal to the signal line instead of the input image data in accordance with a selection signal, The pixel, And an gradation to be represented by driving with an analog signal output to the signal line instead of driving by the time division in accordance with a selection signal. The method of claim 11, The pixel, An operation stop switch circuit for stopping driving by the time division according to the selection signal; And a switch circuit for analog signals for selectively inputting an analog signal output to the signal line. The method of claim 1, The horizontal drive unit, A digital analog converter for outputting an analog signal by digitally analog converting the input image data; A selection circuit for outputting the analog signal to the signal line instead of the input image data in accordance with a selection signal, The pixel of the partial region of the display unit, And an gradation to be represented by driving with an analog signal output to the signal line instead of driving by the time division in accordance with a selection signal. As an electronic apparatus which acquires input image data by an image acquisition means, and displays the input image data by an image display part, The image display unit, A display unit in which pixels are arranged in a matrix, a vertical driving unit for outputting a gate signal to the display unit, a horizontal driving unit for classifying and outputting the input image data into signal lines of the display unit, the display unit, the horizontal driving unit, and the vertical driving unit Has a timing generator for outputting a timing signal for operation reference, The input image data is multi-bit image data, The pixel, A memory section for selectively receiving and holding the input image data output to the signal line by the gate signal, The gray level is represented by driving time division according to the input image data held in the memory unit. A portable device operating by a battery, acquiring input image data by image acquisition means, and displaying the input image data by an image display unit, The image display unit, A display unit in which pixels are arranged in a matrix, a vertical driving unit for outputting a gate signal to the display unit, a horizontal driving unit for classifying and outputting the input image data into signal lines of the display unit, the display unit, the horizontal driving unit, and the vertical driving unit Has a timing generator for outputting a timing signal for operation reference, The input image data is multi-bit image data, The pixel, A memory section for selectively receiving and holding the input image data output to the signal line by the gate signal, And a gray scale by driving time division according to the input image data held in the memory unit. An image display method of driving pixels arranged in a matrix shape with corresponding input image data, and displaying an image by the input image data. A step of image data recording for recording the corresponding input image data in a multi-bit memory unit provided in one pixel; Step of display expressing gradation by driving of time division according to the input image data by driving by time intervals corresponding to each bit of the memory section The image display method characterized by the above-mentioned.

Images