KR20080063902A - Method for booting of multi-port semiconductor memory device - Google Patents

Abstract

A method for booting a multi-port semiconductor memory device is provided to control booting of one port through another port by using an EMRS(Extended Mode Register Set) mode even if individual operation is performed through each port in the multi-port semiconductor memory device. A first booting code related to a first port and stored in a flash memory connected to a first port among a plurality of ports is stored, and booting related to the first port is performed based on the first booting code(S112). The booting related to a second port is performed by reading the booting code stored in the flash memory connected to the first code through an EMRS mode(S118). A semiconductor memory device is a dual port semiconductor memory device, and includes a shared memory area accessible through first and second ports.

Description

Method for booting of multi-port semiconductor memory device

1 is a block diagram of a typical multiprocessor system employed in a portable communication device,

2 is a block diagram of a multiprocessor system employing a memory according to the present invention;

3 is a block diagram illustrating a memory array portion of a multiprocessor system according to the prior art;

4 is a block diagram of a multiprocessor system with a general multipath accessible DRAM,

5 is a block diagram of a multiprocessor system having a multipath accessible DRAM according to an embodiment of the present invention;

6 is a flowchart illustrating a boot operation of FIG. 5.

* Description of the symbols for the main parts of the drawings *

10: first processor 12; 2nd processor

17: DRAM 102: flash memory

The present invention relates to a booting method of a semiconductor memory device, and more particularly, to a booting method of a multipath accessible DRAM in a multiprocessor system.

In general, a semiconductor memory device having a plurality of access ports is called a multiport memory, and in particular, a memory device having two access ports is called a dual port memory. A typical dual port memory is well known in the art and is a video memory for image processing having a RAM port accessible in a random sequence and a SAM port accessible only in a serial sequence.

On the other hand, although it will be more clearly distinguished from the description of the present invention to be described later, unlike the configuration of such a video memory, a shared memory region of a memory cell array having no SAM port and consisting of DRAM cells is read or written through a plurality of access ports. In order to thoroughly distinguish the dynamic random access memory from the multiport memory, the present invention will be referred to as a multipath accessible semiconductor memory device in the present invention.

In line with the ubiquitous orientation of human life today, the electronic systems that humans deal with are developing remarkably. Recently, in order to speed up and facilitate performance of functions or operations in a portable electronic system such as a portable multimedia player, a handheld phone, or an electronic device such as a PDA, a manufacturer may use a plurality of processors as shown in FIG. We have implemented a multiprocessor system.

Referring to FIG. 1, the first processor 10 and the second processor 12 are connected to each other through a connection line L10, and the NOR memory 14 and the DRAM 16 are configured buses B1-B3. ) And the DRAM 18 and the NAND memory 20 are busted to the second processor 12 through the buses B4-B6. Here, the first processor 10 may have a modem function for performing modulation and demodulation of a communication signal, and the second processor 12 may have an application function for processing communication data, performing games, entertainment, and the like. Can have The NOR memory 14 having the NOR structure of the cell array and the NAND memory 20 having the NAND configuration of the cell array are both nonvolatile memories having transistor memory cells having floating gates, and the power supply is turned off. It is mounted for the storage of data which should not be erased even if it is unique, for example, the unique code of the portable device and the preservation data. The DRAMs 16 and 18 function as main memory for data processing of the processor.

However, in the multi-processor system as shown in FIG. 1, since each DRAM is allocated to each processor correspondingly and relatively low speed UART, SPI, and SRAM interfaces are used, data transfer rate is difficult to be secured sufficiently, resulting in size complexity. Memory configuration costs are also burdensome. Accordingly, a scheme for reducing the occupancy size, increasing the data transfer rate, and reducing the number of DRAM memories employed is illustrated in FIG. 2.

Referring to FIG. 2, it is unusual to see that one DRAM 17 is connected to the first and second processors 12 via buses B1 and B2 as compared to the system of FIG. 1. In order to enable each processor to access one DRAM 17 through two paths as in the structure of the multiprocessor system of FIG. 2, two ports may be connected to the buses B1 and B2. Is required. However, conventional DRAM is, as is well known, a memory having a single port.

Therefore, due to the structure of the memory bank and the structure of the port in the multi-processor system as shown in FIG. 2, it is difficult to apply to a conventional DRAM.

Similar to the intention of the inventors to basically implement a memory suitable for a multiprocessor system such as that of FIG. 2, the prior art with the configuration of FIG. 3 in which the shared memory region can be accessed by multiple processors is incorporated. No. US2003 / 0093628, invented by Matter et al. And published in the United States on May 15, 2003.

Referring to FIG. 3, the memory array 35 includes first, second, and third portions, and the first portion 33 of the memory array 35 is connected to the first processor 70 through the port 37. Are accessed only by the second processor 31 through port 38 and the third portion 32 is accessed by both the first and second processors 70 and 80. The multiprocessor system 50 is shown. In this case, the sizes of the first and second portions 33 and 31 of the memory array 35 may be changed depending on the operating load of the first and second processors 70 and 80, and the memory array 35 may be changed. ) Is implemented as a memory type or a disk storage type.

In order to implement the third portion 32 in the memory array 35 shared by the first and second processors 70 and 80 in the DRAM structure, some problems must be solved. As one of such challenges, the placement of memory regions and input / output sense amplifiers in the memory array 35 and proper read / write path control techniques for each port are of great importance.

In addition, UART, SPI, or SRAM interfaces have been used for communication between conventional processors, for example, a modem and an application processor (or a multimedia coprocessor). Such an interface has problems such as speed limitation and an increase in pin count. Entails. In particular, in order to provide a smooth implementation of 3D games, video communication, HDPDA, WiBro, etc., data traffic between a modem and a processor must be greatly increased, and thus, a need for a high speed interface between processors is increased.

Accordingly, there is a need for a more suitable solution that can share the shared memory area allocated within the DRAM memory cell array in a multiprocessor system with two or more processors, while eliminating the problem of low speed interfacing outside the memory. In order to solve this problem, the invention for DRAM interfacing is described in Korean Patent Application No. 2006-0071455 filed on July 28, 2006 by the applicant.

Meanwhile, booting of the DRAM through each processor (port) in the multi-processor (port) system is problematic. That is, when each processor (port) that performs separate operations with each other cannot boot individually, a booting method for this is problematic.

Accordingly, an object of the present invention is to provide a booting method of a semiconductor memory device that can overcome the above-described conventional problems.

Another object of the present invention is to provide a method of booting a semiconductor memory device capable of controlling booting through one port through another port even when performing individual operations through a plurality of ports.

According to an embodiment of the present invention for achieving some of the technical problems described above, a booting method of a semiconductor memory device (DRAM) having memory regions in a memory cell array accessed through a plurality of ports according to the present invention, Storing the first boot code related to the first port stored in a flash memory connected to the first port, which is one of the first ports, and performing booting related to the first port through the first boot code; And booting a boot code stored in a flash memory connected to the first port through another EMRS mode, which is one of a plurality of ports.

The semiconductor memory device may be a dual port semiconductor memory device, and the semiconductor memory device may include a shared memory region accessible through both the first port and the second port.

According to another embodiment of the present invention for achieving some of the above technical problems, there is provided a DRAM (DRAM) having at least two processors according to the present invention, a shared memory area accessed by both processors and A booting method of a multi-processor system having a flash memory connected to one of the two processors, the method comprising: storing boot codes of the two processors in the flash memory; Storing a boot code corresponding to one processor connected to the flash memory in the DRAM and performing booting through the DRAM; And storing a boot code corresponding to a remaining processor that does not boot through a preset EMRS mode in the DRAM and booting the remaining processor.

According to the above configuration, even if performing individual operations through a plurality of ports it is possible to control booting through any one port through another port.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, without any other intention than to provide a thorough understanding of the present invention to those skilled in the art.

 4 is a block diagram of a multiprocessor system with a general multipath accessible DRAM. For the understanding of the present invention, a general case will be described, and then embodiments of the present invention will be described.

Referring to the drawings, a portable communication system includes a first processor 10 performing a first operation, a second processor 12 performing a second operation, and the first and second processors 10 and 20. And a DRAM 17 having memory areas accessed by the memory cell array. The portable communication system also includes flash memories 101, 102 connected to the first and second processors 10, 12 via respective buses.

Although not limited, the DRAM 17 shown in FIG. 4 has two ports independent of each other. For convenience, if the port A to which the signal INTa is output is a first port, it is connected to the first processor 10 through a general-purpose input / output (GIPO) line. When the port B, from which the signal INTb is output, is referred to as a second port, it is connected to the second processor 12 through a general purpose input / output (GIPO) line. Here, the first processor 10 may have a modem function or a baseband processing function for processing modulation and demodulation of a communication signal as a processing function, and the second processor 12 may process communication data, a game, or a moving picture. Application functions for performing entertainment, entertainment, and the like. If necessary, the second processor 12 may be a multimedia coprocessor.

In addition, the flash memories 101 and 102 are nonvolatile memories in which a cell connection configuration of a memory cell array has a NOR structure or a NAND structure, and a memory transistor has a MOS transistor having a floating gate. The flash memories 101 and 102 are mounted as a memory for storing data, which is not to be erased even when the power is turned off, such as unique codes of the portable device and preserved data.

As shown in FIG. 4, the DRAM 17 having dual ports may be used to store instructions and data that may be executed on the processors 10 and 12. In addition, the DRAM 17 is responsible for an interfacing function between the first and second processors 10 and 12. The DRAM interface is used instead of the external interface in the communication between the processors 10 and 12. By utilizing an interface unit in the DRAM having a semaphorer area and a mailbox area, the processors 10 and 12 perform data communication through a common accessible memory area. When host interfacing between processors is provided through memory, a plurality of processors can access the allocated shared memory area at high speed, thereby improving data transfer and processing speed and making the system size compact.

The system of FIG. 4 may be a portable computing device or portable communication device, such as a mobile communication device (eg, cellular phone), a two-way radio communication system, a one-way pager, a two-way pager, a personal communication system, or a portable computer. It should be understood that the scope and application of the present invention is not limited thereto.

In the system of FIG. 4, the number of processors may be extended to three or more. The processor of the system may be a microprocessor, a CPU, a digital signal processor, a microcontroller, a reduced instruction set computer, a complex instruction set computer, or the like. However, it should be understood that the scope of the present invention is not limited by the number of processors in the system. In addition, the scope of the present invention is not limited to any particular combination of processors when the processors become identical or different.

In the system described above, when the DRAM is booted, booting is performed separately by each of the first processor 10 or the second processor 12 connected to each port. For example, booting is performed through a boot code stored in the flash memory 101 connected to the first processor 10 through the first processor 10, and through the second processor 12. Booting is performed through a boot code stored in the flash memory 102 connected to the second processor 10.

In this case, when any one of the flash memories 101 and 102 connected to the first processor 10 or the second processor 12 is not provided, for example, the first processor 10 is connected to the first processor 10. When the flash memory 101 is not provided, a problem may occur in that booting through the first processor 10 cannot be performed.

5 is a block diagram of a multiprocessor system having a multipath accessible DRAM according to an embodiment of the present invention.

As shown in FIG. 5, a multiprocessor system having a multipath accessible DRAM according to an embodiment of the present invention may include a first processor 10 performing a first operation and a second operation performing a second operation. And a DRAM 17 having memory regions in the memory cell array accessed by the first and second processors 10 and 20. The multiprocessor system also includes one flash memory 102 that is coupled to either one of the first and second processors 10 and 12 (eg, the second processor).

Although not limited, the DRAM 17 shown in FIG. 4 has two ports independent of each other. For convenience, if the port A from which the signal INTa is output is a first port, the port A is connected to the first processor 10 through a general-purpose input / output (GIPO) line. When the port B, from which the signal INTb is output, is referred to as a second port, it is connected to the second processor 12 through a general purpose input / output (GIPO) line. Here, the first processor 10 may have a modem function or a baseband processing function for processing modulation and demodulation of a communication signal as a processing function, and the second processor 12 may process communication data, a game, or a moving picture. Application functions for performing entertainment, entertainment, and the like. If necessary, the second processor 12 may be a multimedia coprocessor.

In addition, the flash memory 102 may be a nonvolatile memory in which a cell connection structure of a memory cell array has a NAND structure and the memory cell is a MOS transistor having a floating gate. The flash memory 102 is mounted as a memory for storing data, which is not to be erased even when the power is turned off, such as a unique code of the portable device and storage data. For example, save the boot code.

The booting operation in the system having the structure as described above may be performed through the EMRS mode. The extended mode register set (EMRS) is to set an operation mode of the memory device, that is, an additional operation mode other than a general operation mode such as column address strobe latency and burst length. Driver strength, Temperature Compensated Self Refresh (TCSR), and Partial Array Self Refresh (PASR) may be set. Therefore, it is set to control the boot operation of another port in EMRS mode.

In the case of FIG. 5, the booting operation will be described with reference to FIG. 6.

As shown in FIG. 6, first, a boot code of the NAND flash, which is the flash memory 102, is stored in the DRAM 17 (S110). For example, the boot code is stored in the C and D banks of the DRAM 17. A boot through the second processor (AP) 12 is performed using the boot code (S112). After that, the EMRS mode is started (S114). The boot code for the first processor 10 stored in the flash memory 102 is read and stored in the memory bank of the DRAM according to the operation set as the EMRS mode starts. For example, the data is stored in the B bank (S116). The boot of the first processor 10, which is a modem, is performed through the boot code for the first processor 10 (S118).

As described above, even if the semiconductor memory device performs an individual operation through a plurality of ports, booting through any one port can be controlled through another port.

The description of the above embodiments is merely given by way of example with reference to the drawings for a more thorough understanding of the present invention, and should not be construed as limiting the present invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention.

As described above, according to the present invention, even in the semiconductor memory device having a multi-port, even if the individual operation for each port, the effect of controlling the booting of the other port through any one port through the EMRS mode Has

Claims (5)

A booting method of a semiconductor memory device (DRAM) having memory areas accessed through a plurality of ports in a memory cell array, the method comprising: Storing the first port related first boot code stored in a flash memory connected to a first port, which is one of a plurality of ports, and performing booting related to the first port through the first boot code; Booting a second memory device, which is one of a plurality of ports, from a boot code stored in a flash memory connected to the first port through a preset EMRS mode; Way. The method of claim 1, The method of claim 1, wherein the semiconductor memory device is a dual port semiconductor memory device. The method of claim 2, And the semiconductor memory device has a shared memory region accessible through both the first port and the second port. A DRAM having at least two processors, a DRAM having at least a shared memory area accessed by both processors, and a flash memory coupled to one of the two processors. In the boot method: Storing boot codes of the two processors in the flash memory; Storing a boot code corresponding to one processor connected to the flash memory in the DRAM and performing booting through the DRAM; And storing booting codes corresponding to the remaining processors which are not booted through a preset EMRS mode in the DRAM and booting the remaining processors. The method of claim 5, And the flash memory is a NAND memory.

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