KR20080063894A - Gate electrode formation method of semiconductor device - Google Patents

Abstract

The present invention provides a method for forming a gate electrode of a semiconductor device capable of preventing damage to the underlying structure due to the problem that a fine hole is formed in the tungsten film when the photosensitive film strip after forming the hard mask when forming the gate electrode pattern using tungsten. To this end, the present invention comprises the steps of sequentially forming a gate insulating film, a first conductive film, a second conductive film, a hard mask film and a barrier film on a semiconductor substrate, and patterning the barrier film using a mask for a gate pattern Etching the hard mask layer and the second conductive layer using the patterned barrier layer, removing the barrier layer, and forming a capping layer on side surfaces of the hard mask layer and the second conductive layer. And etching the first conductive layer using the hard mask layer as an etching mask. A method of forming a gate electrode of a semiconductor device is provided.

Description

TECHNICAL FOR FORMING GATE ELECTRODE OF SEMICONDUCTOR DEVICE

1 is a SEM (Scanning Electron Microscope) photograph showing the pin hole (pin hole) generated on the surface of the tungsten film when forming the gate electrode of the semiconductor device according to the prior art.

2A to 2G are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device in accordance with an embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10 substrate 20 device isolation film

30 gate trench 40 gate insulating film

50: first conductive film 60: second conductive film

70: hard mask film 80, 90: barrier film

100 photosensitive film mask pattern 110 capping film

120: gate electrode pattern

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method for forming a gate electrode of a semiconductor device using tungsten.

In general, a gate electrode of a metal oxide semiconductor (MOS) transistor has been formed using a polysilicon film. Such a polysilicon gate electrode has an advantage that the forming process is stable. However, with the higher integration of semiconductor devices, various patterns including gate electrodes have been miniaturized, and in recent years, miniaturization has been progressed to 0.15 µm or less. Accordingly, the doped polysilicon used in the conventional gate electrode formation has a long delay time due to its high resistivity, which makes it difficult to apply to devices requiring high-speed operation.

This problem has become a more serious problem due to the high integration of semiconductor devices, and in order to improve this problem, many studies on the technology of using a high melting point metal such as tungsten (W) as a gate electrode by laminating it on polysilicon and Development is in progress. That is, a gate electrode in which a polysilicon film, a tungsten film, and a gate hard mask film are formed on the gate insulating film is used. In this case, the gate hard mask layer is etched first to etch the tungsten layer and then the tungsten layer underneath is etched. In this case, after the gate hard mask layer is etched, the photoresist used during the etching is removed in an O ₂ atmosphere.

However, the exposed tungsten after etching of the hard mask layer easily oxidizes the boundary between grains and grains in a subsequent high temperature and a large amount of O ₂ atmosphere. At this time, the oxide film is etched by a subsequent cleaning process using BOE (Buffered Oxide Etchant). In this cleaning process, the tungsten film is partially etched together with the oxide film, so that a fine pinhole is formed in the tungsten film as shown in FIG. 1. holes) are formed (see A of FIG. 1).

As described above, the pinhole formed in the tungsten film causes a problem of damage to the lower gate insulating film and the substrate during the subsequent etching of the tungsten film and the polysilicon film.

Therefore, the present invention has been proposed to solve the above-mentioned problems of the prior art, and can perform the photoresist removal process that can cause the pinholes of the tungsten film after the tungsten film etching to prevent damage to the lower thin film by the pinholes of the tungsten film. An object of the present invention is to provide a method for forming a gate electrode of a semiconductor device.

According to an aspect of the present invention, a gate insulating film, a first conductive film, a second conductive film, a hard mask film, and a barrier film are sequentially formed on a semiconductor substrate. Patterning the barrier layer using the semiconductor layer, etching the hard mask layer and the second conductive layer using the patterned barrier layer, removing the barrier layer, and removing the barrier layer from the hard mask layer and the second conductive layer. A method of forming a gate electrode of a semiconductor device, the method comprising: forming a capping layer on a side surface, and etching the first conductive layer using the hard mask layer as an etching mask.

In addition, the present invention according to another aspect for achieving the above object is a step of sequentially forming a gate insulating film, a first conductive film, a second conductive film, a hard mask film, a barrier film on a semiconductor substrate, Patterning the barrier layer using a mask, etching the hard mask layer and the second conductive layer using the patterned barrier layer, and capping layers on side surfaces of the etched hard mask layer and the second conductive layer. A method of forming a gate electrode of a semiconductor device, the method comprising: forming, removing the barrier layer, and etching the first conductive layer using the hard mask layer as an etching mask.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if a layer is said to be on another layer or substrate it may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween. In addition, parts denoted by the same reference numerals (reference numbers) throughout the specification represent the same components.

Example

2A to 2G are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, an isolation layer 20 defining an active region of the semiconductor substrate 10 is formed. The device isolation layer is manufactured through a shallow trench isolation (STI) process. That is, first, a trench (not shown) is formed on the semiconductor substrate 10, and the device isolation layer 20 is formed by filling the inside of the trench with an HDP (High Density Plasma) oxide film.

Subsequently, first and second pad films 31 and 32 are sequentially formed on the semiconductor substrate 10 on which the device isolation film 20 is formed. In this case, a polysilicon film is used as the first pad film 31, and at least one selected from the group consisting of an oxide film, a nitride film, a photosensitive film material, a SiGe film, and an amorphous carbon film is used as the second pad film 32.

In addition, a film that can protect the lower semiconductor substrate 10 is used as the first pad film 31. In this case, a pad oxide film may be used as the first pad film 31. As the second pad film 32, a film having a high etching selectivity with respect to the semiconductor substrate 10 is used. If necessary, the first pad layer 31 may not be formed.

Subsequently, a photoresist pattern (not shown) defining an organic ARC film (not shown) and a subsequent first trench 33 are formed on the second pad film 32.

Subsequently, the first and second pad layers 32 are etched using the photoresist pattern to expose a portion of the semiconductor substrate 10. Subsequently, a portion of the semiconductor substrate 10 exposed through the anisotropic dry etching using the second pad layer 32 as an etching mask is etched to form a first trench 33 having a first width and vertically recessed.

Subsequently, as shown in FIG. 2B, the first and second pad films 31 and 32 are removed. The buffer film 34 covering the inner sidewall of the first trench 33 is formed while covering the semiconductor substrate 10. Thereafter, the semiconductor substrate 10 under the first trench 33 is removed by isotropic wet etching to form a second trench 35 having a circular cross section. In this case, the isotropic wet etchant may use SC1, but is not limited thereto.

On the other hand, the first and second trenches 33 and 35 are the gate trenches 30 for forming the recess channel of this embodiment. Here, the second trench 35 may be formed without removing the first and second pad layers 31 and 32.

Subsequently, as shown in FIG. 2C, after the gate trench 30 is formed, the remaining buffer film 34 is removed. Subsequently, the gate insulating film 40 is formed on the entire structure along the step. The gate insulating layer 40 is formed on the exposed upper surface of the semiconductor substrate 10 and the inner surface region of the gate trench 30.

At this time, the gate insulating film 40 is dry oxidation using oxygen gas or wet oxidation using oxygen gas at a temperature of 800 to 1100 degrees, HCL oxidation using a mixed gas of O ₂ gas and HCl gas, O ₂ gas and C _It is formed by oxidation using a mixed gas of 2H ₃ Cl ₃ gas.

Subsequently, as shown in FIG. 2D, the first conductive film 50 for the gate electrode is formed on the semiconductor substrate 10 on which the gate insulating film 40 is formed. At this time, the inside of the gate trench 30 is filled with the first conductive film 50.

Next, the second conductive film 60 for the gate electrode is formed on the first conductive film 50 for the gate electrode, and the gate hard mask film 70 is formed on the second conductive film 60. At this time, it is preferable to use a polysilicon film doped with the first conductive film 50. It is preferable to use a tungsten film as the second conductive film 60. Of course, a tungsten silicide film may be used as the second conductive film 60.

Subsequently, first and second barrier layers 80 and 90 are formed on the gate hard mask layer 70, and a photoresist mask pattern 100 for forming a gate electrode is formed on the second barrier layer 90. do. In this embodiment, an amorphous carbon film is used as the first barrier film 80. This is because the etching selectivity with the gate hard mask layer 70 under the first barrier layer 80 can be infinite. As a result, pattern defects during gate electrode patterning can be eliminated.

Meanwhile, the first barrier layer 80 may use a material having a high etching selectivity with the lower gate hard mask layer 70 instead of an a-carbon. For example, a SiON film is used as the second barrier film 90. In this case, when the amorphous carbon film is used as the first barrier film 80, since the photoresist mask pattern 100 provided thereon does not act as a sufficient etching barrier, a second barrier film is formed and used as the etching barrier. In addition, the second barrier film 90 may be omitted as necessary.

Subsequently, a photoresist film is coated on the second barrier layer 90, and then an exposure and development process using a gate mask is performed to form the photoresist mask pattern 100. An anti-reflection film BARC (not shown) may be further formed on the second barrier layer 90 before the photoresist coating is applied.

Subsequently, as illustrated in FIG. 2E, the first and second barrier layers 80 and 90 are etched through an etching process using the photoresist mask pattern 100 as an etching mask. For example, the second barrier layer 90 under the photoresist mask pattern is first etched, and then the first barrier layer 80 made of the amorphous carbon film is etched. At this time, since the first barrier film 80 is made of an amorphous carbon film, the first barrier film 80 is preferably removed using O ₂ gas, N ₂ gas and Ar gas. When the first barrier layer 80 is removed, the upper photoresist mask pattern 100 may also be removed.

Subsequently, the gate hard mask layer 70 is etched through an etching process using the etched first barrier layer 80 as an etch mask. In this case, when the nitride film is used as the gate hard mask film 70, the gate hard mask film 70 may be removed using an etching gas such as a CF ₄ / Ar mixed gas and a CHF ₃ / Ar mixed gas.

Next, the second conductive film 60 for the gate electrode of the tungsten film is removed through an etching process using the etched first and second barrier films 80 and 90 and the gate hard mask film 70 as an etching mask. In this case, the second conductive layer 60 may be removed using a fluorine-based etching gas such as SF ₆ , NF ₄ , C ₂ F ₆ , CF _4, or the like.

In this case, although not shown, a part of the first conductive film 50 under the second conductive film 60 may also be removed.

Thus, in the present embodiment, the first and second barrier films 80 and 90, the gate hard mask film 70, and the second conductive film 60 are etched at once. In other words, they can be performed in a single chamber at this time. Of course, it is possible to perform in different chambers or use different chambers locally.

As described above, in the present exemplary embodiment, the second conductive layer is removed without removing the first and second barrier layers 80 and 90 on the gate hard mask layer 70. As a result, pinhole generation of the tungsten film, which may occur when the first and second barrier layers 80 and 90 are removed, may be prevented.

Next, as shown in FIG. 2F, the first and second barrier films 80 and 90 remaining on the gate hard mask film 70 are removed. At this time, since the amorphous carbon film is used as the first barrier film 80, etching thereof is performed in an oxygen atmosphere. When etching the first barrier layer 80, it is preferable to perform wet etching using H ₂ SO ₄ / H ₂ O ₂ . Of course, the etching of the first barrier layer 80 is not limited thereto, and various etching methods such as dry etching using oxygen gas may be used.

As described above, in the present embodiment, since the second conductive film 60 of the tungsten film is etched in advance in the above process, the oxidation that has occurred between the surface grains of the exposed tungsten film does not occur. As a result, the fine holes described in the related art are not formed. That is, the source of the pinhole may be removed by skipping a PR strip process for removing the first barrier layer 80 after etching the gate hard mask layer 70. By removing such pinholes, damage to the lower gate insulating layer 40 and the semiconductor substrate 10 can be prevented, thereby improving the production yield of the semiconductor device.

Subsequently, the first and second barrier layers 80 and 90 on the gate hard mask layer 70 are removed, and then the capping layer 110 is formed along the step on the entire structure. As the capping film 110, a silicon nitride film is preferably used as a film for preventing abnormal oxidation of the sidewall surface of the etched second conductive film 60.

Of course, the present invention is not limited thereto, and in this embodiment, the capping layer 110 is formed on the entire surface of the gate hard mask layer 70 without the first and second barrier layers 80 and 90 being removed. A portion of the 110 and the first and second barrier films 80 and 90 may be removed. As a result, the side surface of the second conductive layer 60 may be prevented from being oxidized abnormally when the first and second barrier layers 80 and 90 are removed.

Subsequently, as shown in FIG. 2G, the capping film 110 in the region except for the sidewall surface region of the gate hard mask film 70 and the second conductive film 60 is removed. Subsequently, the first conductive layer 50 is etched through an etching process using the gate hard mask layer 70 having the capping layer 110 formed on the sidewall thereof as an etching mask. 60, a gate electrode pattern 120 including the gate hard mask layer 70 and the capping layer 110 is formed.

Thereafter, impurity ions may be implanted into both regions of the gate electrode pattern 120 to form a source and a drain electrode.

Thus far, the present invention has been described with respect to the recessed gate electrode having an increased length of the channel through the embodiment. However, the present invention is not limited thereto, and the present invention can be applied to the manufacturing process of all semiconductor devices having a gate electrode including a double film of a tungsten film and a polysilicon film.

Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, a process of removing the amorphous carbon film after etching the tungsten film may be performed to prevent the occurrence of minute holes in the tungsten film, thereby preventing damage to the lower gate insulating film and the semiconductor substrate. .

Claims (7)

Sequentially forming a gate insulating film, a first conductive film, a second conductive film, a hard mask film, and a barrier film on the semiconductor substrate; Patterning the barrier layer using a mask for a gate pattern; Etching the hard mask layer and the second conductive layer using the patterned barrier layer; Removing the barrier layer; Forming a capping film on side surfaces of the hard mask film and the second conductive film; And Etching the first conductive layer using the hard mask layer as an etching mask Gate electrode forming method of a semiconductor device comprising a. The method of claim 1, A polysilicon film is used as the first conductive film, a tungsten film is used as the second conductive film, and an amorphous carbon film is used as the barrier film. The method of claim 1, The barrier layer may be removed by wet etching using H ₂ SO ₄ / H ₂ O ₂ . Sequentially forming a gate insulating film, a first conductive film, a second conductive film, a hard mask film, and a barrier film on the semiconductor substrate; Patterning the barrier layer using a mask for a gate pattern; Etching the hard mask layer and the second conductive layer using the patterned barrier layer; Forming a capping layer on side surfaces of the etched hard mask layer and the second conductive layer; Removing the barrier layer; And Etching the first conductive layer using the hard mask layer as an etching mask Gate electrode forming method of a semiconductor device comprising a. The method of claim 4, wherein Forming the capping film on the side surfaces of the hard mask film and the second conductive film, Forming the capping layer along a step on the entire structure of the hard mask layer and the second conductive layer etched; And Removing the barrier layer and the capping layer remaining on the hard mask layer, and the capping layer provided in the region between the hard mask layer. Gate electrode forming method of a semiconductor device comprising a. The method of claim 4, wherein A polysilicon film is used as the first conductive film, a tungsten film is used as the second conductive film, and an amorphous carbon film is used as the barrier film. The method of claim 4, wherein The barrier layer may be removed by wet etching using H ₂ SO ₄ / H ₂ O ₂ .

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