KR20080053831A - LCD and its driving method - Google Patents

Abstract

Provided are a liquid crystal display device and a driving method thereof capable of improving the display quality of a liquid crystal panel. The liquid crystal display includes a gate line formed in a first direction and intersecting the gate line in a second direction, and a data line including a source and a drain electrode overlapping the gate electrode, and the gate. A first dummy line including a first dummy electrode overlapping the gate electrode, a pixel electrode electrically connected to the first dummy electrode, and overlapping one long side and a short side of the pixel electrode A storage electrode line including a storage electrode overlapping the gate electrode, a second dummy line formed in the same direction as the data line and including a second dummy electrode overlapping the gate electrode; And a third dummy electrode overlapping the gate electrode.

Description

Liquid crystal display and driving method thereof

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention.

3A is a layout view of a thin film transistor substrate manufactured by a manufacturing method according to an embodiment of the present invention.

3B is an enlarged view of a portion A of FIG. 3A.

4A is a cross-sectional view taken along the line IVa-IVa 'of FIG. 3A.

4B is a cross-sectional view taken along the lines IVb-IVb ', IVc-IVc', and IVd-IVd 'of FIG. 3A.

5 is a waveform diagram illustrating charging of a pixel electrode according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

300: liquid crystal panel 400L, 400R: gate driver

500: data driving 600: timing control unit

700: voltage generator 800: gray voltage generator

The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof capable of improving the display quality of a liquid crystal panel.

In general, a liquid crystal display (Liquid Crystal Display) is a flat panel display device that displays an image using a liquid crystal (Liquid Crystal), is thinner and lighter than other display devices, has the advantage of low power consumption and low driving voltage There is this.

The liquid crystal display (hereinafter referred to as LCD) includes a color filter display panel on which reference electrodes and color filters are formed, a thin film transistor on which switching elements and pixel electrodes are formed, and a liquid crystal layer between the two substrates. Interposed therebetween, an electric field is formed by applying different potentials to the pixel electrode and the reference electrode to change the arrangement of the liquid crystal molecules, thereby controlling the light transmittance to express an image.

Recently, R, G, and B pixels are arranged in the horizontal direction in order to reduce the gate driving frequency and reduce the number of data driving units by disposing the gate drivers on both sides of the liquid crystal panel. When the R, G, and B pixels are arranged in the horizontal direction, the number of data lines is reduced by 1/3 while the gate lines are increased by three times, thereby reducing the charging time of each gate line by 1/3.

However, the number of data lines is relatively reduced, resulting in unevenness of the screen due to insufficient charge of the pixel, and in order to solve this problem, a method of precharging a voltage to the pixel is used. This method is not a problem for large panels, but it is a problem for small panels such as laptops and monitors. Therefore, in the panel having a small size, a gate driver in which odd-numbered gate lines are connected to one side of the panel and a gate driver in which even-numbered gate lines are connected to the other side of the panel are used, and a preliminary charging method is used. Doing. However, such a method also causes a voltage deviation between the pixels, causing a luminance difference, resulting in poor pixel bleeding.

An object of the present invention is to provide a liquid crystal display device capable of improving the display quality of a liquid crystal panel.

An object of the present invention is to provide a method of driving a liquid crystal display device capable of improving the display quality of a liquid crystal panel.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, a liquid crystal display device includes a gate line formed in a first direction and intersecting the gate line in a second direction, and formed in the second direction. A data line including a source and drain electrode overlapping the first and second electrodes; a first dummy line formed in the same direction as the gate line and including a first dummy electrode overlapping the gate electrode; and electrically connected to the first dummy electrode. A storage electrode line overlapping a pixel electrode, one long side and a short side of the pixel electrode, the storage electrode line including a storage electrode overlapping the gate electrode, and a second dummy formed in the same direction as the data line and overlapping the gate electrode Is formed between the second dummy line and the second dummy electrode including an electrode, And a third dummy electrode which overlaps with the gate electrode group.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display, the method comprising: providing a first vertical synchronization start signal and receiving the first vertical synchronization start signal to a gate at an N-th gate line; Applying an on voltage, turning on the thin film transistor connected to the corresponding gate line and precharging the pixel connected to the thin film transistor, applying a gate on voltage to the (N + 2) th gate line, Charging the data voltage by turning on the thin film transistor connected to the corresponding gate line, providing a second vertical synchronizing start signal, and receiving the second vertical synchronizing start signal to a gate at the (N + 1) th gate line. The charged data voltage is applied by applying an on voltage and turning on the thin film transistor connected to the corresponding gate line. And a step of charging in the pixel.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, in the liquid crystal display according to the exemplary embodiment, a gray scale connected to the liquid crystal panel 300 and the gate drivers 400L and 400R, the data driver 500, and the data driver 500 connected thereto. The voltage generator 800 includes a timing controller 600 and a voltage generator 700 for controlling the voltage generator 800.

The liquid crystal panel 300 is connected to a plurality of display signal lines G1-Gn and D1 -Dm as an equivalent circuit, and includes a plurality of unit pixels Px arranged in a matrix form.

Here, the display signal lines G1-Gn and D1-Dm include a plurality of gate lines G1-Gn transferring gate signals and data lines D1-Dm transferring data signals. The gate lines G1-Gn extend in the row direction and are substantially parallel to each other, and the data lines D1-Dm extend in the column direction and are substantially parallel to each other.

Although not shown, each unit pixel PX includes a switching element connected to the display signal lines G1-Gn and D1-Dm, a liquid crystal capacitor, and a storage capacitor connected thereto. The storage capacitor can be omitted as needed.

On the other hand, in order to implement color display, each unit pixel should be able to display color, which is possible by providing a red, green, or blue color filter in a region corresponding to the pixel electrode. In addition, although the color filter is formed in a corresponding region of the second display panel, the color filter may be formed above or below the pixel electrode of the first display panel.

A polarizer (not shown) for polarizing light is attached to an outer surface of at least one of the first display panel and the second display panel of the liquid crystal panel 300.

The gray voltage generator 800 may generate two sets of gray voltages related to transmittance of a unit pixel. That is, one of the two sets is the positive voltage, and the other is the negative voltage. The positive voltage and the negative voltage mean voltages whose polarities of the data voltages are opposite to the common voltage Vcom, and are alternately provided to the liquid crystal panel during inversion driving.

The gate drivers 400L and 400R are disposed on the left and right sides of the liquid crystal panel 300 and are connected to the respective gate lines G1 to Gn, and a combination of the gate on voltage Von and the gate off voltage Voff is provided. The first and second gate clock signals CPV1 and CPV2 may be applied to the gate lines G1 to Gn.

The data driver 500 is connected to the data lines D1-Dm of the liquid crystal panel 300, generates a plurality of gray voltages based on voltages provided from the gray voltage generator 800, and generates the generated gray voltages. Is applied to the unit pixel as a data signal, and is usually composed of a plurality of integrated circuits.

The timing controller 600 generates control signals for controlling operations of the gate drivers 400L and 400R and the data driver 500, and transmits corresponding control signals to the gate drivers 400L and 400R and the data driver 500. To provide.

The voltage generator 700 generates a plurality of driving voltages. For example, the first and second gate clock signals CPV1 and CPV2 and the common voltage Vcom formed by a combination of the gate on voltage Von and the gate off voltage Voff are generated. Here, the first and second gate clock signals CPV1 and CPV2 are gate-on voltages Von at high levels to drive the switching elements, and gate-off voltages Voff at low levels. do.

Hereinafter, the display operation of the liquid crystal display will be described in more detail.

The timing controller 600 controls an RGB image signal R, G, and B and an input control signal, for example, a vertical sync signal Vsync and a horizontal sync signal, from an external graphic controller (not shown). Hsync), main clock MCLK, and data enable signal DE are provided. The timing controller 600 generates a gate control signal CONT1, a data control signal CONT2, and the like based on the input control signal and appropriately adjusts the image signals R, G, and B according to the operating conditions of the liquid crystal panel 300. After the processing, the gate control signal CONT1 is provided to the gate drivers 400L and 400R, and the data control signal CONT2 and the processed image signals R ', G', and B 'are transferred to the data driver 500. to provide.

Here, the gate control signal CONT1 is an output enable signal OE that defines the width of the vertical synchronization start signals STV1 and STV2 and the gate on voltage Von indicating the start of the output of the gate-on voltage Von period. And the like.

The data control signal CONT2 is a horizontal load start signal STH indicating the start of input of the image data R ', G', and B 'and a data load signal for applying a corresponding data voltage to the data lines D1-Dm. (TP), an inversion signal (RVS) and a data clock signal that inverts the polarity of the data voltage with respect to the common voltage (Vcom) (hereinafter referred to as 'polarity of the data voltage by reducing the polarity of the data voltage for the common voltage'). (HCLK) and the like.

The data driver 500 sequentially receives the image data R ′, G ′, and B ′ corresponding to one row of unit pixels according to the data control signal CONT2 from the timing controller 600. By selecting the gray scale voltages corresponding to the image data R ', G', and B ', the image data R', G ', and B' are converted into the corresponding data voltages.

The gate drivers 400L and 400R apply the gate-on voltage Von to the gate lines G1-Gn according to the gate control signal CONT1 to turn on the switching elements connected to the gate lines G1-Gn.

While the gate-on voltage Von is applied to one gate line G1-Gn, and a row of switching elements connected thereto is turned on (this period is referred to as '1H' or '1 horizontal period'). ], The data driver 500 supplies each data voltage to the corresponding data lines D1-Dm. The data voltage supplied to the data lines D1-Dm is applied to the corresponding unit pixel through the turned-on switching element.

The liquid crystal molecules change their arrangement according to the electric field generated by the pixel electrode and the common electrode, and thus the polarization of light passing through the liquid crystal layer changes. This change in polarization is represented by a change in transmittance of light by a polarizer (not shown) attached to the first display panel and the second display panel.

In this manner, the gate-on voltages Von are sequentially applied to all the gate lines G1 -Gn during one frame to apply data voltages to all the unit pixels. When one frame ends, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each unit pixel is opposite to that of the previous frame ('frame' reversal'). In this case, the polarity of the data voltage flowing through one data line may be changed ('line inversion') or the polarity of the data voltage applied to one pixel row may be different according to the characteristics of the inversion signal RVS within one frame ( 'Dot reversal').

2 is an equivalent circuit diagram of a pixel according to an exemplary embodiment of the present invention.

Referring to FIG. 2, one pixel crosses the gate line G1, the storage electrode line SL1, the gate line G1, and the storage electrode line SL1 extending in the same direction as the gate line G1. The line D1 includes a plurality of switching elements Q1 to Q3 and the pixel electrode PX1. In this case, the switching elements Q1 to Q3 are connected to the gate line G1.

The switching elements Q1 to Q3 may be implemented as thin film transistors. The switching elements Q1 may be, for example, a control terminal connected to the gate line G ₁ and an input terminal connected to the storage electrode line SL ₁ . And an output terminal connected to the liquid crystal capacitor Clc.

In addition, the liquid crystal capacitor Clc has two terminals as the common electrodes of the pixel electrodes PX1 and PX2 of the thin film transistor array panel 100 and the color filter display panel (not shown), and the liquid crystal layer between the two electrodes is a dielectric Function as. The pixel electrodes PX1 and PX2 are connected to the switching element, and the common electrode is formed on the front surface of the second display panel and receives the common voltage Vcom. In addition, a common electrode may be provided in the first display panel, and both electrodes may be made in a linear or bar shape.

The storage capacitor Cst serving as an auxiliary of the liquid crystal capacitor Clc may be formed by overlapping the storage electrode line SL ₁ and the pixel electrode PX1 with an insulator interposed therebetween. The storage electrode line (SL _1), the common voltage (Vcom) can be a fixed voltage, such as applied, and (independent wiring scheme), and the storage electrode lines gate of the (SL ₁₎ is omitted, the pixel electrode (PX1) and the front end Lines may overlap each other via an insulator to form a storage capacitor Cst (shear gate method).

Meanwhile, in order to implement color display, each unit pixel should display a color, which includes a red, green, or blue color filter in a predetermined region of the color filter display panel corresponding to the pixel electrodes PX1 and PX2. It is possible by doing. Here, the color filter may be formed in a corresponding region of the color filter display panel, or may be formed above or below the pixel electrodes PX1 and PX2 of the thin film transistor array panel 100.

The pixels PX1 and PX2 of the liquid crystal panel 300 according to the exemplary embodiment of the present invention are arranged in a matrix form, and R pixels having the same color are arranged in the first direction of the matrix, and in the second direction. R, G, and B pixels are repeatedly arranged. In this case, the first direction and the second direction represent a row direction and a column direction, respectively.

3A is a layout view of a thin film transistor substrate manufactured by a manufacturing method according to an exemplary embodiment of the present invention, FIG. 3B is an enlarged view of a portion A of FIG. 3A, and FIG. 4A is a line IVa-IVa 'of FIG. 3A. 4B is a cross-sectional view taken along lines IVb-IVb ', IVc-IVc', and IVd-IVd 'of FIG. 3A.

3A through 4B, a plurality of gate wires for transmitting a gate signal are formed on the insulating substrate 10. The gate wires 22, 24, and 25 are connected to the gate line 22 extending in the horizontal direction, the gate end 25 which receives the gate signal from the outside and transmits the gate signal to the gate line. It is connected to the gate line 22 includes a gate electrode 24 of the thin film transistor formed in the shape of a projection.

The gate wirings 22, 24, and 25 may be formed of, for example, aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, and copper-based metals such as copper (Cu) and copper alloys. Metal, molybdenum (Mo) and molybdenum alloys such as molybdenum-based metal, it may be made of chromium (Cr), titanium (Ti), tantalum (Ta). In addition, the gate lines 22, 24, and 25 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive films is made of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce the signal delay or voltage drop of the gate wirings 22, 24, and 25. However, the present invention is not limited thereto and may be made of various various metals and conductors.

 A gate insulating film 30 made of silicon nitride (SiNx) or the like is formed on the substrate 10 and the gate wirings 22, 24, and 25.

On the gate insulating film 30 of the gate electrode 24, semiconductor layers 40a, 40b and 40c made of a semiconductor such as hydrogenated amorphous silicon or polycrystalline silicon are formed in an island shape, and the semiconductor layers 40a, 40b and 40c. An ohmic contact layer 55a, 55b, 55c formed of a material such as n + hydrogenated amorphous silicon doped with a high concentration of silicide or n-type impurities is formed on the upper portion of the upper portion of the resistive contact layer.

Data wires 62, 65, 66, and 68 are formed on the ohmic contacts 55a, 55b, and 55c and the gate insulating film 30. The data wires 62, 65, 66, and 68 are formed in the vertical direction and intersect the gate line 22 to define the pixel, the branch of the data line 62, the data line 62, and the resistive contact layer 55b. A source electrode 65 formed at an upper portion, a data end 68 connected to one end of the data line 62 to receive an image signal from the outside, and separated from the source electrode 65 and a gate electrode 26 or The drain electrode 66 is formed on the ohmic contact layer 55b between the source electrode 65 and the channel portion of the thin film transistor.

The data lines 62, 65, 66, and 68 may be formed of, for example, aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper (Cu), and copper alloys. It may be made of a copper-based metal, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloy, chromium (Cr), titanium (Ti), tantalum (Ta). In addition, the data lines 62, 65, 66, and 68 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive films may be formed of a low resistivity metal such as an aluminum-based metal, a silver-based metal, or a copper-based metal to reduce signal delay or voltage drop of the data lines 62, 65, 66, and 68. Is done.

The source electrode 65 and the drain electrode 66 overlap at least a portion of the semiconductor layer 40b, and the source electrode 65 is formed on both sides of the drain electrode 66. Here, the ohmic contact layer 55b is present between the lower semiconductor layer 40b and the source electrode 65 and the drain electrode 66 thereon, and serves to lower the contact resistance.

3A and 4A, the resistive contact layer 55a is formed in a zigzag form so as to overlap one long side and one short side positioned at one side and the other side of the pixel electrode 82 and overlap the gate electrode 24. The first dummy including a storage electrode line 71 including the storage electrode 75, and a first dummy electrode 76 formed in the same direction as the gate line 22 and overlapping the gate electrode 24. Line 72 is formed. In this case, the storage electrode 75 and the first dummy electrode 76 are formed in the same direction as the source and drain electrodes 65 and 66.

Here, the storage electrode line 71 and the first dummy line 72 are connected to the storage electrode 75 and the first dummy electrode 76, respectively, and the storage electrode line 71, the storage electrode 75, and The first dummy electrode 76 may be formed of the same material as the source electrode 65 and the drain electrode 66. In this case, the first dummy electrode 76 is electrically connected to the pixel electrode 82.

In addition, on the ohmic contact layer 55c, a second dummy line 91 is formed in a zigzag form so that at least a portion of the ohmic contact layer overlaps the gate electrode 24 on one side and the other side of the data line 62. The second dummy electrode 77 and the third dummy electrode 95 are formed in the same direction as the drain electrodes 65 and 66.

Here, the second dummy line 91 is connected to the third dummy electrode 95, and the second dummy line 91, the second dummy electrode 77, and the third dummy electrode 95 are the source electrode 65. And the drain electrode 66 may be formed of the same material. The second dummy electrode 77 may be formed together when the first dummy electrode 76 is formed, and the third dummy electrode 95 may be formed in the same shape as the source electrode 65.

Here, as shown in FIG. 4B, the storage electrode line 71 overlaps the pixel electrode 82 to be described later with the gate insulating layer 30 interposed therebetween to form a storage capacitor that improves charge storage capability of the pixel. Such shapes and arrangements of the storage electrode line 71 and the storage electrode 75 may be modified in various forms.

As illustrated in FIG. 3B, a first thin film transistor TFT1 having a storage electrode 75 and a first dummy electrode 76 serving as a source electrode and a drain electrode, respectively, is formed on the semiconductor layer 40a. The second thin film transistor TFT2 including the source and drain electrodes 65 and 66 is formed on the 40b, and the second and third dummy electrodes 77 and 95 are respectively disposed on the semiconductor layer 40c. A third thin film transistor TFT3 serving as a source electrode is formed. Therefore, in the present invention, the first, second, and third thin film transistors TFT1, TFT2, and TFT3 are used to charge a voltage to one pixel electrode 82, which will be described in detail later with reference to FIG. 5. Let's explain.

The passivation layer 70 is formed on the data lines 62, 65, 66, and 68 and the semiconductor layers 40a, 40b, and 40c which are not covered. The protective film 70 is formed of, for example, a-Si: C: O or a-Si: It may be formed of a low dielectric constant insulating material such as O: F, or silicon nitride (SiNx), which is an inorganic material. In the case where the protective film 70 is formed of an organic material, silicon nitride (SiNx) is disposed under the organic film to prevent the organic material of the protective film 70 from contacting the exposed semiconductor layers 40a, 40b, and 40c. Alternatively, an insulating film (not shown) made of silicon oxide (SiO ₂ ) may be further formed.

In the passivation layer 70, contact holes 73, 74, and 78 exposing the first dummy electrode extension part (not shown) and the data line end 68, respectively, are formed, and in the passivation layer 70 and the gate insulating layer 30. The contact hole 75 exposing the gate line end 25 is formed. The pixel electrode 82, which is electrically connected to the first dummy electrode 76 and positioned in the pixel, is formed on the passivation layer 70 through the contact holes 73 and 74. The pixel electrode 82 to which the data voltage is applied generates an electric field together with the common electrode of the upper panel to determine the arrangement of liquid crystal molecules of the liquid crystal layer between the pixel electrode 82 and the common electrode.

In addition, an auxiliary gate end 85 and an auxiliary data end 88 connected to the gate end 25 and the data end 68, respectively, are formed on the passivation layer 70 through the contact holes 75 and 78. The pixel electrode 82, the auxiliary gate, and the data ends 85 and 88 are made of ITO.

5 is a waveform diagram illustrating charging of a pixel electrode according to an exemplary embodiment of the present invention.

In the present invention, the odd gate line and the even gate line are divided and driven, and the odd gate line is connected to the gate driver 400L, and the even gate line is connected to the gate driver 400R. As shown in FIG. 5, since the data voltage is applied twice during the time 2H when the first gate line G1 is turned on, the gate line G1 is turned on using the two switching elements Q5 and Q6. The data voltage is applied once during the time 2H. Hereinafter, a charging form of the first pixel electrode PX1 according to an exemplary embodiment will be described.

2 and 5, the gate driver 400L receives the first vertical synchronization start signal STV1 from the timing controller 600 and applies a gate-on voltage Von to the first gate line G1. . Then, the switching element Q1 connected to the first gate line G1 is turned on so that the storage voltage Vcst is pre-charged to the first pixel electrode PX1 through the storage electrode line SL1. (a). In this case, the first pixel electrode PX1 is charged with a voltage having the same voltage level as the common voltage Vcom.

Thereafter, when the gate-on voltage Von is applied to the third gate line G3, the switching element Q7 is turned on so that the data voltage applied through the data line D1 is transferred to the switching element Q6 and charged. .

Next, the gate driver 400R receives the second vertical synchronization start signal STV2 from the timing controller 600 and applies the gate-on voltage Von to the second gate line G ₂ . Then, the switching element Q6 connected to the second gate line G ₂ is turned on so that the data voltage charged in the switching element Q6 is main-charged to the first pixel electrode PX1. )do. In this case, the switching element Q4 is turned on to precharge the storage voltage Vcst to the second pixel electrode PX2. Through this process, the data voltage is charged in the pixel for one frame.

When the liquid crystal display is driven as described above, the pixel electrode is precharged with the storage voltage Vst during the time when the gate-on voltage is applied to the corresponding gate line (2H), and thus has the opposite polarity in the previous frame. Even when a data voltage is applied, bleeding defects caused by poor charging rates can be prevented.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

The liquid crystal display and the driving method thereof according to the present invention as described above can prevent the pixel bleeding defect by preventing the voltage deviation between the pixels using three thin film transistors. Therefore, the screen quality of the liquid crystal display device can be improved.

Claims (13)

A gate line formed in a first direction and including a gate electrode; A data line formed to cross the gate line in a second direction, the data line including a source and a drain electrode overlapping the gate electrode; A first dummy line formed in the same direction as the gate line and including a first dummy electrode overlapping the gate electrode; A pixel electrode electrically connected to the first dummy electrode; A storage electrode line overlapping one long side and one short side of the pixel electrode, the storage electrode line including a storage electrode overlapping the gate electrode; A second dummy line formed in the same direction as the data line and including a second dummy electrode overlapping the gate electrode; And And a third dummy electrode formed between the second dummy electrode and overlapping the gate electrode. The method of claim 1, A first thin film transistor including the storage electrode and the first dummy electrode formed on the gate electrode; A second thin film transistor including the source and drain electrodes formed on the gate electrode; And And a third thin film transistor including the second and third dummy electrodes formed on the gate electrode. The method of claim 1, The pixel electrode is formed in a first direction. The method of claim 1, The storage electrode line is formed in a zigzag form so as to overlap with one long side and short side positioned on one side and the other side of the pixel electrode. The method of claim 1, The storage electrode line and the first dummy line are formed of the same material as the source and drain electrodes. The method of claim 1, And the second dummy line is formed in a zigzag form such that at least a portion of the second dummy line overlaps the gate electrode on one side and the other side of the data line. The method of claim 6, The second dummy line is formed of the same material as the drain electrode. The method of claim 1, The third dummy electrode is formed when the first dummy electrode is formed. Providing a first vertical synchronization start signal; Receiving the first vertical synchronization start signal, applying a gate-on voltage to an N-th gate line, turning on the thin film transistor connected to the gate line, and precharging the pixel connected to the thin film transistor; Applying a gate-on voltage to the (N + 2) -th gate line and turning on the thin film transistor connected to the gate line to charge the data voltage; Providing a second vertical synchronization start signal; And Receiving the second vertical synchronization start signal, applying a gate-on voltage to the (N + 1) -th gate line, turning on the thin film transistor connected to the corresponding gate line, and charging the charged data voltage to the pixel. A method of driving a liquid crystal display comprising the step. The method of claim 9, The precharging of the corresponding pixel may include charging at the same voltage level as the common voltage. The method of claim 9, And the gate-on voltage has two horizontal periods. The method of claim 9, The gate-on voltage applied to the N-th gate line and the gate-on voltage applied to the (N + 1) -th gate line overlap one horizontal period. The method of claim 9, The odd-numbered gate line is connected to the first gate driver, and the even-numbered gate line is connected to the second gate driver.

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