KR20080050220A - True random number generation device using oscillator sampling method - Google Patents

Abstract

A device for generating a true random number by using an oscillator sampling method is provided to generate a true random number at low cost with low power consumption while fast generating the true random number by digitally designing the device and using an oscillator control function. A device(100) for generating a true random number includes a first oscillating circuit(110) providing output of oneself as data input; a second oscillating circuit(120) providing output of oneself as clock input; a POR(Power On Reset) circuit(130) providing output of oneself as reset input; a first D-flipflop(140) operating with the input of the data, clock, and reset; an inverter(160) inverting output of the second oscillating circuit; and a second D-flipflop(150) having output of the first D-flipflop as data input, output of the inverter as clock input, and operated by a reset signal applied from the outside to generate a true random number. The POR circuit provides an operation starting signal to the first and second oscillating circuits and provides a reset signal to the first D-flipflop.

Description

True Random Number Generation Device using Oscillator Sampling Method

1 is a block diagram showing the configuration of a real random number generator according to an embodiment of the present invention;

Figure 2 is a block diagram showing the configuration of a real random number generator according to another embodiment of the present invention,

3 is a block diagram showing a jitter circuit of the real-real water generator according to an embodiment of the present invention;

4 is a block diagram showing an oscillation circuit of a real-real water generator in accordance with a preferred embodiment of the present invention;

5 is a circuit configuration diagram of a POR circuit of a real water generator according to a preferred embodiment of the present invention;

6 is a signal timing diagram of a real random number generator according to an exemplary embodiment of the present invention;

7 is a block diagram showing a parallel real random number generator of a repeating structure according to an embodiment of the present invention,

8 is a block diagram for conceptually explaining a resource sharing real random number generator according to an embodiment of the present invention; and

FIG. 9 is a block diagram conceptually illustrating a resource sharing real random number generating device according to another exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100: real number generator 110: first oscillation circuit

120: second oscillation circuit 130: POR (Power-On-Reset) circuit

140: first D-flip flop 150: second D-flip flop

160: inverter 170: jitter circuit

180: third oscillation circuit

The present invention relates to a real number generator using an oscillator sampling method, and more particularly, to a real number generator capable of being integrated into an IC chip and capable of generating high-speed operation and low power characteristics using an oscillator sampling method.

Generally, random number generators are classified into real number generator and pseudo random number generator.

Typically, a pseudo random number generator uses a method of generating random numbers by logic circuits and software, such as generating a random number of a personal computer, and has a simple advantage in that it is a small circuit, but the same seed has the same random number. Since the initial state is known, random numbers can be easily predicted, and thus have insufficient disadvantages in terms of confidentiality protection.

The real random number generating device is safer than the pseudo random number generating method by using a method of generating random numbers using physical phenomena such as thermal noise of a resistor, short noise (noise) in a semiconductor, and optically generated wave of radiation. It guarantees random number generation and is implemented with methods and techniques such as amplification, oscillator sampling, chaos, etc.

However, when the noise level is small and the noise level needs to be increased for the random number extraction, the real number generator has a disadvantage in that the IC chip implementation suitability is solved by the operating voltage lowered by IC refinement.

Looking at the implementation method of such a real number generator, first, the amplification method is typically composed of a signal amplification means and AD conversion means, and performs a function to amplify a low signal level.

However, the amplification method requires a high gain amplifier to raise the low signal level, resulting in an increase in power consumption due to an increase in the amplifier circuit scale by signal amplification, isolation from digital circuits, and spikes from a power supply. It requires a large resistor and capacitor for noise control has a problem of lowering the integration.

Next, the oscillator sampling method is composed of signal oscillation means and signal sampling means. Here, the signal oscillation means is composed of a plurality of delay circuits connected on a loop like a ring oscillator. For example, voltage controlled oscillation (VCO), crystal oscillation, etc., but the increase in power consumption and random data due to the characteristics of the oscillation circuit. There is a fear that the periodicity of is exposed.

The chaos method is composed of a chaos processing method and a means to which signal theory is applied.

In fact, because of the low level of noise in random number generation, very large attenuation interferences take away both the output or entropy (statistical independence) of the random number generator.

Thus, amplification and sampling of the noise signal generally biases the band limitations and boundaries that the amplifier cannot avoid, further reducing entropy and making it difficult to achieve high and low cost of high-entropy bits. To overcome this problem, chaos processing method and signal theory are applied.

However, the chaos method is implemented with digital logic that digitizes an analog signal and post-processes it with an application algorithm by the noise of the real number generator being implemented in analog. Thus, the Chaos method does not implement a complete digital design, but also impedes the possibility of rapid system prototyping and production of small scale products and the ease of transition to new technologies. In manufacturing, there is a problem of increasing the unit cost of the random number generator by the gap.

In order to solve complex circuits and physical / circuit sizes that are a common problem of physical phenomena used to generate real numbers, incomplete transmission (meta-stability), phase and / or frequency (without using vulnerable circuits) Applying phase and / or frequency jitter requires combining voltage and frequency variations, verifying physical sources and verifying resistance to electrical attacks. In addition, thermal or shot noise can be applied individually or in an integrated form, enabling vacuum tube shot noise, radioactive decay, and neon lamp discharge. Although clock jitter and PC hard drive fluctuations can be used as noise sources, the large attenuation interference reduces entropy because the signal level of the actual noise source is very low. To improve entropy, digital nonlinear filtering or lossy compression may be applied, but the bit-rate is reduced.

Meanwhile, in order to overcome the disadvantages of the random number generator as described above, efforts have been made to implement a random number generator using amplification, oscillator sampling, and chaotic methods.

One such effort was Fairfield, Mortenson and Coulthart [Ref. 1], which consisted of a high / low frequency sampling oscillator, a parity filter to eliminate bias, and a scrambled LFSR.

Intel [Ref. 2] also consists of a VCO and an oscillator that samples as a means of amplifying thermal noise.

Stojanovski et al. [3] is a technology that generates random numbers by configuring a real number generator using a switched current technique.

[Reference 1] R.C. Fair_eld, R.L. Mortenson, and K.B. Coulthart. An LSI Random Number Generator (RNG). In Advances in Cryptography: Proceedings of Crypto 84, pages 203.230. LNCS 0196, Springer-Verlag, 1984.

[Reference 2] B. Jun and P. Kocher. The intel random number generator. White paper by Cryptographic Research Inc., 1999.

ftp://download.intel.com/design/security/rng/CRIwp.pdf.

[Reference 3] T. Stojanovski, J. Pil, and L. Kocarev. Chaos-based random number generators. Part II: practical realization. IEEE Transactions on Circuits and Systems. I: fundamental Theory and Application, 48 (3): 382.385, March 2001.

However, the technique according to the above-mentioned efforts has disadvantages such as application of LFSR to scrambler, combined use of amplification and sampling, software structure of SHA-1 based mixing function, and analog based design.

In addition, since the technique according to the examples is low in terms of performance, the technique according to the effort example has a problem that is difficult to apply to the low-power real-time random number generating apparatus required in a mobile device.

An object of the present invention for solving the above problems is to provide a real number generator using an oscillator sampling method that is easy to implement, and can generate a low power random number.

In addition, another object of the present invention for solving the above problems is to provide a real number generator using an oscillator sampling method for generating a parallel real number.

A real-real number generator using an oscillator sampling method according to an embodiment of the present invention for achieving the above object, the first oscillation circuit for providing its own output as a data input; A second oscillating circuit providing its own output as a clock input; Power-On-Reset (POR) circuitry providing its own output as a reset input; A first D flip-flop that operates with the data, clock, and reset as inputs; An inverter for inverting and outputting the output of the second oscillation circuit; A second D flip-flop that generates a real number by operating an output of the first D-flip flop as a data input, an output of the inverter as a clock input, and an externally applied reset signal as an input; The POR circuit provides an operation start signal to the first and second oscillator circuits and a reset signal to the first D-flip flop.

The first and second oscillator circuits include a ring oscillator for inverting and outputting an input; And an NAND gate configured to generate an output of the oscillation circuit by using the output of the ring oscillator and an external application signal as inputs, wherein the NAND gate feeds the output back to the ring oscillator.

The POR circuit includes a resistor connected to a power supply; And a capacitor connected to ground, wherein the resistor and the capacitor are connected in series, so that the series connection point is an output terminal.

The POR circuit is characterized in that it comprises a logic module having an arbitrary delay time and whose output performs a high level at a low level or vice versa.

Preferably, the real random number generating device is configured in parallel in a repeated structure to generate a real number having a random bit size.

Preferably, the real random number generator is configured to share the first and second oscillation circuit, the POR circuit, and the inverter, and to configure the rest in parallel in a repeated structure, thereby generating a random bit size random number. It is characterized by.

According to another aspect of the present invention, an apparatus for generating a real number using an oscillator sampling method includes: a jitter circuit for providing its own output as a data input; A second oscillating circuit providing its own output as a clock input; A POR circuit providing its output as a reset input; A third oscillation circuit operating as an input of the output of the POR circuit and providing its own output as an operation start signal of the jitter circuit; A first D flip-flop that operates with the data, clock, and reset as inputs; An inverter for inverting and outputting the output of the second oscillation circuit; A second D flip-flop that generates a real number by operating an output of the first D-flip flop as a data input, an output of the inverter as a clock input, and an externally applied reset signal as an input; The POR circuit provides an operation start signal to the second and third oscillator circuits, and provides a reset signal to the first D-flip flop.

The jitter circuit may include: a noise source for inputting at least one of heat, temperature, current, voltage, and frequency obtainable in a semiconductor integrated circuit and outputting a signal; An amplifier for amplifying the signal output from the noise source to generate a digital signal; And a buffer for outputting the signal generated by the amplifier according to an external input signal.

The second and third oscillator circuits include a ring oscillator functioning to invert and output an input; And an NAND gate configured to generate an output of the oscillation circuit by using the output of the ring oscillator and an external application signal as inputs, wherein the NAND gate feeds the output back to the ring oscillator.

Preferably, the real random number generating device is configured in parallel in a repeated structure to generate a real number having a random bit size.

Preferably, the real random number generator is configured to share the second and the third oscillation circuit, the POR circuit, the jitter circuit and the inverter, and the rest of which is configured in parallel in a repeated structure, the actual random bit size It is characterized by generating a random number.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, in describing in detail the operating principle of the preferred embodiment of the present invention, if it is determined that the detailed description of the related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

In addition, the same reference numerals are used for parts having similar functions and functions throughout the drawings.

1 is a block diagram showing the configuration of a real-real number generator according to an embodiment of the present invention.

Referring to FIG. 1, the real water generator 100 according to the present invention includes first and second oscillation circuits 110 and 120, power-on-reset circuit 130, and first and second D−. The flip-flops 140 and 150 and the inverter 160 may be configured as basic elements, and a TR (Test Reset) signal is input and an RN (Random Number) signal is output.

In the real random number generator 100 having such a configuration, the POR circuit 130 generates a POR signal after a predetermined time after the power is turned on, and generates the generated POR signals through the first and second oscillation circuits 110 and 120. ) And the first D-flip-flop 140.

Accordingly, the first oscillator circuit 110 receives the POR signal, which is the output signal of the POR circuit 130, and outputs the data of the first D-flip-flop 140 to the output RO1 ((Ring-oscillator Output 1)). Provide as input.

The second oscillation circuit 120 receives a POR signal, which is an output signal of the POR circuit 130, and provides an output RO2 as a clock of the first D-flip flop 140.

The first D-flip-flop 140 uses the output RO2 of the second oscillating circuit 120 as a clock and the output RO of the first oscillating circuit 110 as a data input so that the clock is a rising edge trigger. Output data to output terminal Q. In addition, the first D-flip-flop 140 initializes the value of the first D-flip-flop 140 according to the POR signal value input to the reset terminal.

The second D-flip-flop 150 uses the output of the first D-flip-flop 140 as a data input and uses a random number (i.e., a clock signal of the inverted signal RO2 'of which the output of the second oscillation circuit 120 is inverted. RN) outputs the function. In addition, the second D flip-flop 150 initializes the value of the second D flip-flop 150 according to the TR signal value input to the reset terminal.

Meanwhile, the inverter 160 inverts the output of the second oscillation circuit 120 to provide the clock of the second D flip-flop 150.

2 is a block diagram showing the configuration of a real random number generator according to another embodiment of the present invention.

Referring to FIG. 2, the real water generator 100 of the present invention includes a jitter circuit 170, second and third oscillation circuits 120 and 180, a POR circuit 130, and first and second D-flips. The flops 140 and 150 and the inverter 160 may be configured as basic elements, and the TR signal is input and the RN signal is output.

First, in the real temperature generator 100 having such a configuration, the POR circuit 130 generates a POR signal after a predetermined time passes after the power is turned on, and thus the second and third oscillation circuits 120 and 180 are formed. 1 D-flip flop 140 performs a function provided.

Accordingly, the second oscillation circuit 120 receives a POR, which is an output signal of the POR circuit 130, and provides an output RO2 as a clock of the first D-flip flop 140.

The third oscillator circuit 180 performs a function of inputting POR, which is an output signal of the POR circuit 130, and providing an output to an input of the jitter circuit 170.

The jitter circuit 170 inputs the output signal of the third oscillation circuit 180 and provides an output JO as a data input of the first D-flip-flop 140. In this case, the output JO is typically a waveform having a faster cycle than the output of the second oscillation circuit 120.

The first D-flip-flop 140 uses the output RO2 of the second oscillating circuit 120 as a clock and the output JO of the jitter circuit 170 as a data input, so that the clock is a rising edge trigger. Output data to terminal Q. In addition, the first D-flip-flop 140 initializes the value of the first D-flip-flop 140 according to the POR signal value input to the reset terminal.

The second D flip-flop 150 uses the output of the first D flip-flop 140 as a data input, and uses the clock signal RO2 ′ where the output of the second oscillation circuit 120 is inverted as a clock. Performs the function of outputting (RN). In addition, the second D flip-flop 150 initializes the value of the second D flip-flop 150 according to the TR signal value input to the reset terminal.

Meanwhile, the inverter 160 inverts the output of the second oscillation circuit 120 to provide the clock of the second D flip-flop 150.

Next, each configuration of the real random number generator 100 described with reference to FIGS. 1 and 2 will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram illustrating a jitter circuit of a real water generator according to a preferred embodiment of the present invention.

As illustrated in FIG. 3, the jitter circuit 170 configured by the real number generator 100 of FIG. 2 may include a noise source 171, an amplifier 172, and a buffer 173. Input 'Enable' signal which is an output signal of oscillation circuit and input JO (Jitter Output) signal.

In the jitter circuit 170, the noise source 171 outputs a signal by inputting heat (temperature), current, voltage, frequency, and the like that can be integrated in a chip, and the amplifier 172 outputs from the noise source 171. A digital signal is generated by amplifying the low level signal.

The buffer 173 performs a function of outputting a digital signal generated by the amplifier 172 according to an external input signal (Enable). Here, the external input signal 'Enable' generates the output of the jitter circuit 170 in the operation of the real number generator 100, and outputs the output of the jitter circuit 170 when the operation of the real number generator 100 is completed. Has a characteristic of blocking.

FIG. 4 is a block diagram illustrating an oscillation circuit of a real random water generator according to a preferred embodiment of the present invention.

As shown in FIG. 4, the first, second, and third oscillator circuits 120, 130, and 180 in FIGS. 1 and 2 may include a ring oscillator 121 and a NAND gate 122. , 'Enable' signal is input and 'RO' signal is output.

Here, the ring oscillator 121 performs a function of inverting and outputting an input.

The input of the ring oscillator 121 is an input signal of the NAND gate 122, and the output of the ring oscillator 121 is supplied to one of the inputs of the NAND gate 122.

The ring oscillator 121 may be composed of an even number of logic gates having a function of inverting an input, for example, an inverter, a NAND gate, a NOR gate, and the like. It consists mainly.

Meanwhile, the NAND gate 122 generates an output RO of the corresponding oscillator circuit by inputting the output of the ring oscillator 121 and the external 'Enable' signal.

The NAND gate controls the operation of the ring oscillator 121 according to the 'Enable' signal. For example, the NAND gate inverts another input signal when 'Enable = 1', and when the 'Enable = 0', the output is always maintained at '1' to control the operation of the ring oscillator 121. have.

Such a NAND gate may be replaced by an arbitrary logic gate that outputs the result of signal inversion or previous output, or vice versa, when the value of the 'Enable' signal is '1' or '0', respectively. have.

5 is a circuit configuration diagram of a POR circuit of a real-real water generator according to a preferred embodiment of the present invention.

As shown in FIG. 5, the POR circuit 130 in FIGS. 1 to 2 includes a resistor R and a capacitor C connected in series, and after the power is turned on, the resistor R and the capacitor C When the time t is determined by the value of), the output POR between the resistor R and the capacitor C is switched from the low level to the high level.

Here, the time t determined by the values of the resistor R and the capacitor C can be changed using another circuit in another embodiment. For example, a multi-bit counter can be used to determine the 't' time until a particular value is counted, and a resistor connected in series with a logic module that performs an arbitrary level of delay and a high level or vice versa. It can be replaced by the configuration of (R) and condenser (C).

6 is a signal timing diagram of a real random number generator according to an exemplary embodiment of the present invention.

Referring to FIG. 6, the signals generated from the real random number generator 100 after the power supply (power supply voltage Vdd) is turned on in FIGS. 1 and 2 to 5 are output POR and jitter circuit 170 of the POR circuit 130. The output JO of the first and second oscillation circuit (110, 120) of the output RO1, RO2 and the final output RN signal.

In FIG. 6, the time 't' is a time determined by the POR circuit 130.

In addition, the first oscillator 120 outputs 'RO1' at a time after the time 't' is determined by its own circuit configuration, and the jitter circuit 170 output 'JO' is also set by the third oscillator circuit 180. Since the value is determined by the output, it cannot be represented as a timing diagram.

However, 'RO2', which is the output of the second oscillation circuit 120, is generated as the clock of FIG. 6 and provided to the first D-flip-flop 140, and 'RN, which is the output of the second D-flip-flop 150. 'Is generated as a random number value generated in the falling transition section of the' RO2 '.

On the other hand, the real number generator 100 having such a configuration and configuration operation is repeatedly implemented to generate a real number of the size desired by the user.

7 is a block diagram illustrating an apparatus for generating a parallel real random number having a repeating structure according to an exemplary embodiment of the present invention.

Referring to FIG. 7, the parallel real number generator 100 may generate a real number having a desired size by repeatedly implementing the real number generator 100 of FIGS. 1 and 2 described above. .

That is, the parallel real random number generator 100 may generate, for example, 8-bit random numbers RN0 to RN7 using eight parallel real random number generators 100 as shown in FIG. 7.

In addition, the random realization generating device 100 of FIGS. 1 and 2 described above may share only certain components so that the real random number having a desired size can be generated.

FIG. 8 is a block diagram conceptually illustrating a resource sharing real random number generating device according to an exemplary embodiment of the present invention.

Referring to FIG. 8, the resource sharing type real number generator 200 may share a single first and second oscillation circuit 110 and 120, a POR circuit 130, and an inverter 160, respectively. In FIGS. 1 to 7, the components of the remaining circuits may be implemented as a plurality of blocks 210 to generate a real random number having a desired size.

That is, as shown in FIG. 8, the resource sharing type real number generator 100 has the remaining components except for the first and second oscillation circuits 110 and 120, the POR circuit 130, and the inverter 160. Realized random number of desired size by generating different blocks for each RN7.

FIG. 9 is a block diagram conceptually illustrating a resource sharing real random number generating device according to another exemplary embodiment of the present invention.

Referring to FIG. 9, the resource sharing type real number generator 200 may include one jitter circuit 170, a POR circuit 130, second and third oscillation circuits 110 and 120, and an inverter 160, respectively. 2 and 7, the components of the remaining circuits may be implemented as a plurality of blocks 220 in FIG. 2 to FIG. 7 to generate a real random number having a desired size.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those skilled in the art.

The real random number generator using the oscillator sampling method according to the present invention as described above is digitally designed and uses an oscillator control function, which is easy to implement, and has an effect of generating high speed, low power consumption, and low cost real number. Have

The real number generator using the oscillator sampling method according to the present invention as described above has an effect of generating a real number having a desired size by being applied to a parallel type or a resource sharing type of a repeating structure.

Claims (11)

A first oscillating circuit providing its own output as a data input; A second oscillating circuit providing its own output as a clock input; Power-On-Reset (POR) circuitry providing its own output as a reset input; A first D flip-flop that operates with the data, clock, and reset as inputs; An inverter for inverting and outputting the output of the second oscillation circuit; And A second D flip-flop that generates a real number by operating an output of the first D-flip flop as a data input, an output of the inverter as a clock input, and an externally applied reset signal as an input; And the POR circuit provides an operation start signal to the first and second oscillation circuits, and a reset signal to the first D-flip-flop. The method of claim 1, The first and second oscillation circuit, A ring oscillator for inverting and outputting an input; And It includes a NAND gate for generating the output of the oscillation circuit by the output of the ring oscillator and the external application signal, And the NAND gate feeds an output back to a ring oscillator, thereby providing a real oscillator sampling method. The method of claim 1, The POR circuit, A resistor connected to the power supply; And Includes a capacitor connected to ground, The resistor and the condenser are connected in series, the real number generator using an oscillator sampling method, characterized in that the series connection point as an output terminal. The method of claim 1, The POR circuit, An apparatus for generating a real number using an oscillator sampling method, comprising: a logic module having an arbitrary delay time and outputting from a low level to a high level or vice versa. The method of claim 1, The real number generator, Real number generator using an oscillator sampling method characterized in that the parallel structure is configured in a repeated structure to generate a real number of an arbitrary bit size. The method of claim 1, The real number generator, Using the oscillator sampling method, the first and second oscillator circuits, the POR circuit, and the inverter are shared in resources, and the rest of them are configured in parallel in a repeated structure to generate a real bit number having an arbitrary bit size. Real water generator. Jitter circuitry providing its own output as a data input; A second oscillating circuit providing its own output as a clock input; A POR circuit providing its output as a reset input; A third oscillation circuit operating as an input of the output of the POR circuit and providing its own output as an operation start signal of the jitter circuit; A first D flip-flop that operates with the data, clock, and reset as inputs; An inverter for inverting and outputting the output of the second oscillation circuit; And A second D flip-flop that generates a real number by operating an output of the first D-flip flop as a data input, an output of the inverter as a clock input, and an externally applied reset signal as an input; And the POR circuit provides an operation start signal to the second and third oscillation circuits and a reset signal to the first D-flip-flop. The method of claim 7, wherein The jitter circuit is, A noise source for inputting at least one of heat, temperature, current, voltage, and frequency obtainable in the semiconductor integrated circuit to output a signal; An amplifier for amplifying the signal output from the noise source to generate a digital signal; And And a buffer for outputting the signal generated by the amplifier according to an external input signal. The method of claim 7, wherein The second and third oscillation circuit, A ring oscillator functioning to invert and output an input; And It includes a NAND gate for generating the output of the oscillation circuit by the output of the ring oscillator and the external application signal, And the NAND gate feeds an output back to a ring oscillator, thereby providing a real oscillator sampling method. The method of claim 7, wherein The real number generator, Real number generator using an oscillator sampling method characterized in that the parallel structure is configured in a repeated structure to generate a real number of an arbitrary bit size. The method of claim 7, wherein The real number generator, The second and third oscillator circuit, the POR circuit, the jitter circuit and the inverter, the resource sharing, and the rest is configured in parallel in a repeated structure, the oscillator characterized in that to generate a real bit number of arbitrary bit size Real number generator using sampling method.

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