KR20080047806A - Array substrate, liquid crystal display using the same and fabricating method thereof - Google Patents

Abstract

An array substrate, a liquid crystal display using the array substrate, and its fabrication method are provided to minimize degradation of a front side luminance and other operation characteristics in controlling a viewing angle. An array substrate(100) includes a plurality of pixels on which a display region(RC) and a viewing angle control region(RV) are defined, and controls a data voltage applied to the display region and a viewing angle control voltage applied to the viewing angle control region. A color filter substrate(200) is disposed to face the array substrate and includes a light control layer(230) formed at a region corresponding to the viewing angle control region. A liquid crystal layer(300) is formed between the array substrate and the color filter substrate. A viewing angle varies by the light control layer that controls the direction in which light is outputted and the viewing angle control region to which the viewing angle control voltage is applied.

Description

Array substrate, liquid crystal display device using the array substrate and manufacturing method thereof {Array substrate, liquid crystal display using the same and fabricating method

1 and 2 are schematic diagrams of a liquid crystal display according to the related art.

3 is a schematic exploded perspective view of a liquid crystal display according to an exemplary embodiment of the present invention.

4A and 4B are schematic cross-sectional views of FIG. 3, respectively.

5 is a plan view of an array substrate according to an embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating the line II ′ of FIG. 5.

7 is a plan view of an array substrate according to another embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating the II-II ′ line of FIG. 7.

9A to 9D are perspective views illustrating processes of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention.

10A through 10E are cross-sectional views of processes in detail by dividing some steps of FIG. 9A.

(Explanation of symbols for the main parts of the drawing)

100: array substrate 110: gate line

121, 120: data line 130: lower polarizer

PXL: Pixel RC: Display Area

RV: viewing angle control area 200: color filter substrate

210: color filter layer 220: black matrix

230: light control layer 240: upper polarizing plate

300: liquid crystal layer

The present invention relates to an array substrate capable of viewing angle control, a liquid crystal display device using the array substrate, and a method of manufacturing the same.

The liquid crystal display device forms a liquid crystal layer having anisotropic dielectric constant between the array substrate and the color filter substrate, which are transparent insulating substrates, and then adjusts the intensity of the electric field formed in the liquid crystal layer to change the molecular arrangement of the liquid crystal material, thereby displaying the liquid crystal layer. It is a display device which expresses a desired image by adjusting the amount of light transmitted to a color filter substrate which is a surface.

FIG. 1 and FIG. 2 are schematic diagrams of a liquid crystal display according to the related art. In particular, FIGS. 1 and 2 illustrate a case in which a liquid crystal display having a view angle control mode is driven in a wide viewing angle mode and a narrow viewing angle mode, respectively. .

Basic principles of the viewing angle control method shown in FIGS. 1 and 2 are as follows.

First, a liquid crystal panel having a transverse electric field structure having a wide viewing angle is configured for image display, a liquid crystal panel for adjusting the viewing angle is added to the upper or lower portion of the liquid crystal panel, and then the added liquid crystal panel is driven to narrow the wide viewing angle. To adjust the viewing angle mode. The liquid crystal panel added for adjusting the viewing angle basically has a function of not inhibiting the wide viewing angle characteristic of the liquid crystal panel displaying an image and a function of inducing a narrow viewing angle necessary in terms of security or privacy.

1 and 2, the liquid crystal panel including the first liquid crystal layer 80 is a panel for adjusting the viewing angle, and the liquid crystal panel including the second liquid crystal layer 90 is a panel for displaying an image to have a wide viewing angle. . If no voltage is applied to the first liquid crystal layer 80, the liquid crystal molecules 81 are arranged in parallel between the two substrates 10 and 21 to maintain the original wide viewing angle, thereby forming a wide viewing angle mode. When voltage is applied to the 80, the liquid crystal molecules 81 are arranged vertically between the two substrates 10 and 21, and thus the viewing angle is reduced, thereby entering the narrow viewing angle mode.

1 and 2, the first, second, third, and fourth substrates 10, 21, 22, and 30 are disposed in parallel to each other, and the first substrate 10 and the second substrate 21 are arranged in parallel. Transparent electrodes 70 and 60 are formed to face each other on the inner surface of each other, and two linear electrodes 40 and 50 are formed parallel to each other on the upper surface of the third substrate 22.

The first and second liquid crystal layers 80 and 90 are formed between the first substrate 10, the second substrate 21, the third substrate 22, and the fourth substrate 30, respectively.

The liquid crystal panel including the first and second substrates 10 and 21 and the first liquid crystal layer 80 between the two substrates 10 and 21 is a viewing angle control liquid crystal panel capable of adjusting a wide viewing angle and a narrow viewing angle. .

In the state in which no electric field is applied, as shown in FIG. 1, the liquid crystal molecules 81 of the first liquid crystal layer 80 are aligned parallel to the first and second substrates 10 and 21. In the wide viewing angle mode shown in FIG. 1, since the liquid crystal molecules 91 of the second liquid crystal layer 90 are also aligned in the same direction, the liquid crystal molecules 91 have the same viewing angle as that of the liquid crystal display having a general transverse electric field structure having one liquid crystal panel. It does not affect other characteristics of the transverse electric field structure.

On the outer surfaces of the first substrate 10 and the third substrate 30, two polarizing plates 11 and 31 are respectively attached to polarize the light passing therethrough. At this time, the transmission axis directions of the polarizing plates 11 and 31 are arranged to be perpendicular or parallel to the alignment direction of the liquid crystal molecules 81 and 91.

FIG. 2 illustrates a case where the liquid crystal display of FIG. 1 is used in the narrow viewing angle mode.

When a voltage is applied to the two transparent electrodes 70 and 60 to form an electric field in the vertical direction between the first and second substrates 10 and 21, the liquid crystal molecules 81 of the first liquid crystal layer 80 are filled with the electric field. It is arranged perpendicular to the two substrates (10, 21) along the direction of. In this case, the liquid crystal molecules 82 adjacent to the two substrates 10 and 21 are arranged in parallel to the two substrates 10 and 21 because the orientation force due to rubbing is greater than the force exerted by the electric field.

In this narrow viewing angle mode, the liquid crystal molecules 81 arranged perpendicular to the two substrates 10 and 21 do not affect the retardation of light traveling to the front of the two substrates 10 and 21.

However, as the polarized light passes through the first liquid crystal layer 80 made of the liquid crystal molecules 81, the polarization state is changed by a delay. The rain decreases and the viewing angle becomes narrower.

That is, by applying an electric field to the first liquid crystal layer 80 added for the purpose of controlling the viewing angle, the viewing angle of the liquid crystal display is lowered, thereby narrowing the viewing angle.

As described above, since the narrow viewing angle and the wide viewing angle mode may be switched through one liquid crystal display, a flexible viewing angle characteristic may be exhibited as needed.

However, when the viewing angle characteristic of the liquid crystal display device is adjusted through such a structure, a separate liquid crystal panel for adjusting the viewing angle is used in addition to the liquid crystal panel displaying an image.

Therefore, the overall thickness of the liquid crystal display device is excessively increased, a cost and a manufacturing process are additionally generated, and it is difficult to perform a process such as rubbing, scribing, or bonding the substrate.

In addition to the technology for controlling viewing angle characteristics using two liquid crystal panels as shown in FIGS. 1 and 2, a method of easily changing the wide / narrow viewing angle mode according to whether the film is attached or detached by attaching a film for adjusting the viewing angle is used. .

This method uses the principle of absorbing the light passing in the oblique direction of the side when the film is attached to implement a narrow viewing angle mode, and implements a wide viewing angle mode by transmitting both the front and side light when the film is detached.

However, even in the case of the method using the film, in the narrow viewing angle mode to which the film is attached, there is a disadvantage that the front brightness is lowered by the attached film.

Accordingly, an object of the present invention is to provide an array substrate capable of controlling light blocking / transmission and viewing angle characteristics within a range in which a manufacturing process is easier and a cost is lower than a method using a double liquid crystal panel, and an array thereof. A liquid crystal display using a substrate and a method of manufacturing the same are provided.

Another object of the present invention is to provide a liquid crystal display and a method of manufacturing the same capable of minimizing degradation of front luminance and other operating characteristics when adjusting the viewing angle.

Technical problems to be achieved by the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned above will be clearly understood by those skilled in the art from the following description. Could be.

According to an aspect of the present invention, a liquid crystal display device includes a plurality of pixels in which a display area and a viewing angle control area are defined, and a data voltage applied to the display area and a viewing angle control voltage applied to the viewing angle control area. An array substrate for controlling the light source, a color filter substrate disposed to face the array substrate, and having a light control layer formed in a region corresponding to the viewing angle control region, and a liquid crystal layer formed between the array substrate and the color filter substrate. It includes, characterized in that the viewing angle is changed by the light control layer for controlling the direction in which light is emitted and the viewing angle control region to which the viewing angle control voltage is applied.

In one aspect, an array substrate according to the present invention includes a gate line formed on a substrate, and first and second data lines intersecting with the gate line to define the pixel, and parallel to each other at left and right outer portions of the pixel. And a first pixel electrode and a first common electrode formed parallel to each other in the display area of the pixel, a second pixel electrode and a second common electrode formed parallel to each other in the viewing angle control area of the pixel, and the first data line. A first thin film transistor connected to the first pixel electrode and supplying a data voltage to the first pixel electrode, and a second thin film transistor connected to the second data line and supplying a viewing angle control voltage to the second pixel electrode. The viewing angle is changed by the change of the data voltage and the viewing angle control voltage to switch between wide viewing angle mode and narrow viewing angle mode. do.

In another aspect, an array substrate according to the present invention includes a gate line formed on a substrate, first and second data lines intersecting with the gate line to define a pixel, and parallel to each other at an outer portion of the pixel; A first pixel electrode and a common electrode formed in parallel with each other in the display area of the pixel, a second pixel electrode formed in the viewing angle control area of the pixel, and connected to the first data line and positioned in the display area of the pixel; A first thin film transistor supplying a data voltage to the first pixel electrode, and a second thin film connected to the second data line and supplying a viewing angle control voltage to the second pixel electrode positioned in the viewing angle control region of the pixel. And a transistor, the viewing angle of which is varied by the change of the data voltage and the viewing angle control voltage to narrow the wide viewing angle mode. Yagak between modes and operates so that conversion is made.

A method of manufacturing a liquid crystal display according to the present invention includes a) a plurality of pixels in which a display area and a viewing angle control area are defined, and controlling a data voltage applied to the display area and a viewing angle control voltage applied to the viewing angle control area. Forming an array substrate having a variable viewing angle; b) forming a color filter substrate having a light control layer formed in a region corresponding to the viewing angle control region; and c) the array substrate or the color filter substrate. Forming a liquid crystal layer on the substrate; and bonding the array substrate and the color filter substrate with the liquid crystal layer interposed therebetween.

Specific details of other embodiments are included in the detailed description and the drawings. Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. Like reference numerals refer to like elements throughout.

Hereinafter, an array substrate, a liquid crystal display using the array substrate, and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a schematic exploded perspective view of a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 4A and 4B are schematic cross-sectional views of FIG. 3, respectively.

In the liquid crystal display according to the exemplary embodiment of the present invention, as shown in FIG. 3, the array substrate 100, the color filter substrate 200, and the two substrates 100 and 200 that are bonded to face each other at predetermined intervals are illustrated in FIG. 3. It consists of the liquid crystal layer 300 formed in between.

3 to 4B, a light control layer 230 is disposed in the color filter substrate 200 to separate light from two different regions RV and RC in the pixel PXL in a frontal or viewing angle direction. .

In one pixel PXL on the array substrate 100, an image different from the front image is input to the first thin film transistor TFT1 for inputting the front image to the display region RV and the viewing angle control region RC. The second thin film transistor TFT2 for controlling the viewing angle is disposed.

The light control layer adjusts the light emitted from the two regions (RV, RC) to the color filter substrate 200 bonded to the array substrate 100 having the pixel PXL structure so as to exit only in the front direction or the viewing angle direction. 230 is arranged as shown in FIG. 4A.

Light emitted from the display area RV by the light control layer 230 always exits in the front direction, and light emitted from the viewing angle control area RC always exits in the viewing angle direction.

Here, when a data voltage for displaying a constant image is input to the display region RV, and a viewing angle control voltage having the same value as the data voltage is input to the viewing angle control region RC, the same image in the front direction and the viewing angle direction is inputted. This is indicated so that a wide viewing angle is implemented.

However, when the viewing angle control voltage is input at a value different from the data voltage, for example, when the viewing angle control voltage is input at the same value as the common voltage or the gamma voltage of the black level, the viewing angle control area RC is the display area. Unlike (RV), a black or near black image is displayed, so that a narrow viewing angle that can see a correct image only in the front direction is realized.

Through this structure, as shown in FIG. 4A, switching between light / narrow viewing angle modes is performed by inputting an image of the area RC where light is emitted in the viewing angle direction differently from the image in the front direction to control light in the viewing angle direction. Can be achieved.

The color filter substrate 200 adjusts the light from the viewing angle direction by using the light control layer 230 that separates the light from the two regions (RV and RC) in the front direction and the viewing angle direction, thereby controlling the wide viewing angle mode and the narrow viewing angle. Implement the mode optionally.

As shown in FIG. 3, the color filter layer 210 and the black matrix 220 are formed on one surface of the color filter substrate 200 facing the array substrate 100.

The color filter layer 210 includes red, green, blue, and white color filters R, G, B, and W arranged to correspond to each of the plurality of pixels PXL, and represent a color. Is located between adjacent color filters to block light leakage.

Here, the color filter layer 210 may be composed of only the color filters of red, green, and blue (R, G, B), but when the white color filter (W) is included, it may have an improved effect in terms of aperture ratio. .

On the other side of the color filter substrate 200 is formed a light control layer 230 for blocking light in the lateral direction in the narrow viewing angle mode.

The array substrate 100 includes a plurality of pixels PXL arranged in a matrix form. Each pixel PXL includes a display area RV and a viewing angle control area RC, and is applied to the display area RV. The viewing angle is varied by controlling the data voltage and the viewing angle control voltage applied to the viewing angle control region RC.

In one pixel PXL, two thin film transistors TFT1 and TFT2 connected to two regions RV and RC, respectively, are included. Each pixel PXL applies two kinds of voltages to the different regions RV and RC through two thin film transistors TFT1 and TFT2, that is, a viewing angle control voltage for varying the viewing angle and a data voltage for displaying images. It has a structure that can

The array substrate 100 includes a plurality of gate lines 110 and 110 ′ which are arranged in one direction at regular intervals to define the pixel PXL and a plurality of data lines which are arranged in a direction perpendicular to the gate line 110. 120 and 121 are formed.

Here, based on the arbitrary Nth pixel PXL, the Nth gate line 110 in the horizontal direction is positioned below the Nth pixel PXL, and the 2Nth, 2N + 1st data arranged in the vertical direction. Lines 120 and 121 are formed parallel to each other at the left and right outer portions of the N-th pixel PXL.

Each pixel PXL constituting the array substrate 100 includes a display area RV in the center and a viewing angle control area RC positioned at both left and right sides of the display area RV. The display area RV of the pixel PXL receives a data voltage and displays an image corresponding thereto, and the viewing angle control area RC receives the viewing angle control voltage and transmits / blocks light according to the received voltage. Adjust

Based on one pixel PXL, the viewing angle control region RC of the array substrate 100 is formed with the light control layer 230 of the color filter substrate 200 as shown in FIGS. 4A and 4B. The display area RV of the array substrate 100 is a region corresponding to the portion, and the display region RV of the array substrate 100 corresponds to an opening except for a portion where the light control layer 230 is formed.

As shown in FIG. 3, an upper polarizer 240 and a lower polarizer 130, in which optical axes are configured in a direction perpendicular to each other, are disposed above the color filter substrate 200 and below the array substrate 100.

As such, the light control layer 230 is disposed on the color filter substrate 200 to separate light from two different regions RV and RC in the pixel PXL in a front direction or a viewing angle direction. In addition, in one pixel PXL of the array substrate 100, another image applied to the viewing angle control region RC in addition to the first thin film transistor TFT1 for inputting an image of the front applied to the display region RV. A second thin film transistor TFT2 for input is further disposed.

In the narrow viewing angle mode, when the viewing angle control voltage of the viewing angle control region RC in which light is emitted in the viewing angle direction is input differently from the data voltage of the display region RV, the narrow viewing angle mode is realized while the light in the viewing angle direction is controlled. .

When the light control layer 230 of the color filter substrate 200 is disposed inside the upper polarizing plate 240 in contact with the color filter substrate 200 and is configured on the color filter substrate 200, light is emitted from the pixel PXL. The distance to the control layer 230 can be designed more easily.

Referring to FIG. 4B, the distance d from the pixel PXL to the light control layer 230 may be expressed by equations (1) and (2).

Where? Is the desired viewing angle, n is the refractive index of the substrate, and A is the size of the opening of one pixel PXL.

It is effective that the size A of the opening of one pixel PXL is about 1/2 to 1/4 of the pitch P corresponding to the left and right sizes of the pixel PXL.

If the size of the opening is smaller than 1/4 of the total size P of the pixel PXL, the aperture ratio may be lowered and display characteristics may deteriorate. If the size of the opening is larger than 1/2, the size of the viewing angle control area RC may be too small to control the viewing angle. The characteristics may deteriorate.

If the size A of the opening of the pixel PXL is A ≒ P / 3 with respect to the pitch P corresponding to the left and right sizes of one pixel PXL, the pixel PXL of the array substrate 100 The distance d to the light control layer 230 of the color filter substrate 200 satisfies Equation 3

For example, let the designer designate the desired narrow viewing angle Φ (the viewing angle in the narrow viewing mode in which the viewing angle is minimized) to about 20 °, and the pitch P of 1 pixel (PXL) of the 15 "panel to about 100 µm. When the refractive index n is calculated as about 1.48, the distance d from the pixel PXL to the light control layer 230 is about 70 μm.

5 is a plan view of an array substrate according to an exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view illustrating a line II ′ of FIG. 5.

Referring to FIG. 5, one pixel PXL includes a display area RV in the center and a viewing angle control area RC positioned at both sides of the display area RV.

In the display area RV, the plurality of first pixel electrodes 151 and the plurality of first common electrodes 141 parallel to each other are formed to cross each other, and the data voltage applied to the first pixel electrode 151 and the first An image is displayed according to the horizontal electric field generated by the voltage difference of the common voltage applied to the common electrode 141.

The data voltage is supplied through the first data line 120, and according to the on / off operation of the first thin film transistor TFT1 connected to the first data line 120, the first pixel electrode of the display area RV ( 151).

The first thin film transistor TFT1 is positioned at the intersection of the gate line 110 and the first data line 120 under the pixel PXL and responds to the scan signal supplied from the gate line 110. The data voltage of the data line 120 is applied to the first pixel electrode 151.

In the viewing angle control region RC, the second pixel electrode 161 and the second common electrode 142 which are parallel to each other are formed to cross each other. The viewing angle is varied according to the horizontal electric field generated by the voltage difference between the common voltage applied to the second common electrode 142 and the viewing angle control voltage applied to the second pixel electrode 161.

The viewing angle control voltage is supplied through the second data line 121, and the viewing angle control voltage is applied to the viewing angle control region RC according to the on / off operation of the second thin film transistor TFT2 connected to the second data line 121. Is transferred to the second pixel electrode 161.

The second thin film transistor TFT2 is positioned at a portion where the front gate line 110 ′ and the second data line 121 cross each other, and the second data line in response to a scan signal supplied from the front gate line 110 ′. The viewing angle control voltage of 121 is applied to the second pixel electrode 161.

The first and second common electrodes 141 and 142 are connected to each other through the common line 140, the first pixel electrode 151 is connected to the first lead line 150, and the second pixel electrode 161 is The second lead line 160 is connected to each other.

The vertical cross-sectional structure of the pixel PXL is shown in FIG. 6.

Referring to FIG. 6, the first thin film transistor TFT1 includes the first gate electrode 111 on the array substrate 100, the gate insulating layer 101, the first semiconductor layer 120_3, and the first semiconductor layer thereon. Interposed between the first source electrode 120_1 and the first drain electrode 120_2, the first source electrode 120_1, and the first drain electrode 120_2 and the first semiconductor layer 120_3 spaced apart from both sides of the 120_3. Consisting of a first ohmic contact layer 120_4.

The first gate electrode 111 is a portion of the gate line 110, the first source electrode 120_1 is an extended portion of the first data line 120, and the first drain electrode 120_2 is the first source. A portion formed spaced apart from the electrode 120_1 by a predetermined distance.

Similarly, the second thin film transistor TFT2 may be formed on the second gate electrode 111 ′ on the array substrate 100, the gate insulating layer 101, the second semiconductor layer 121_3, and the second data line 121 thereon. The second drain electrode 121_2, the second source electrode 121_1, the second drain electrode 121_2, and the second semiconductor spaced apart from the extended second source electrode 121_1 and the second source electrode 121_1 by a predetermined distance. The second ohmic contact layer 121_4 is interposed between the layers 121_3. The second gate electrode 111 'is a partial region of the front gate line 110'.

The passivation layer 102 is covered on the first and second thin film transistors TFT1 and TFT2, and the first and second contact holes H1 and H2 are formed on the passivation layer 102. The first pixel electrode 151 is in electrical contact with the first drain electrode 120_2 through the first lead line 150 connected to the first contact hole H1, and the second pixel electrode 161 is in contact with the second contact. The second drain electrode 121_2 is electrically contacted through the second lead line 160 connected to the hole H2.

On the array substrate 100 where the gate electrodes 111 and 111 ′ are formed, the first and second common electrodes 141 and 142 alternately and parallel to the first and second pixel electrodes 151 and 161 are together. Is formed.

6 illustrates a case where the first and second common electrodes 141 and 142 are formed on the same plane as the gate electrodes 111 and 111 ＇, but the present invention is not limited thereto. It may be modified in various forms within the scope of the included technical idea.

For example, the common line 140 connecting the first and second common electrodes 141 and 142 and the plurality of first and second common electrodes 141 and 142 to each other is the first and second pixel electrodes 151. And 161 may be formed on the passivation layer 102.

On the other hand, when the data voltage supplied to the first pixel electrode 151 of the display area RV and the viewing angle control voltage supplied to the second pixel electrode 161 of the viewing angle control area RC are adjusted, Switching between viewing and narrow viewing angle modes is possible.

The first pixel electrode 151 connected to the first thin film transistor TFT1 and the second pixel electrode 161 connected to the second thin film transistor TFT2 are formed in different regions RV and RC. In FIG. 5, the first pixel electrode 151 is positioned in the display area RV positioned at the center of the pixel PXL, and the second pixel electrode 161 is positioned in the outer portion of the pixel PXL. RC), respectively.

In addition, the first data line 120 and the second data line 121 exist in one pixel PXL. Therefore, a wide viewing angle mode is implemented by supplying the same voltage to the display area RV and the viewing angle control area RC as shown in FIG. 5, or different images are displayed in the two areas RV and RC by applying different voltages. Thus, narrow viewing angle mode can be implemented.

In the wide viewing angle mode, the viewing angle control voltage applied to the second pixel electrode 161 is equal to the display voltage applied to the first pixel electrode 151. Therefore, the image in the steady state is displayed in all the front / side directions.

In the narrow viewing angle mode, the display voltage applied to the first pixel electrode 151 is different from the viewing angle control voltage applied to the second pixel electrode 161. Therefore, an image of a steady state is displayed only in the front direction, and another image corresponding to the viewing angle control voltage is displayed in the side direction.

7 is a plan view of an array substrate according to another exemplary embodiment of the present invention, and FIG. 8 is a cross-sectional view illustrating the II-II ′ line of FIG. 7.

Referring to FIG. 7, an area of one pixel PXL is defined by a gate line 110 in a horizontal direction and first and second data lines 120 and 121 in a vertical direction intersecting with the gate line 110. do.

The first and second data lines 120 and 121 are formed parallel to each other in the left and right outer portions of the pixel PXL and are connected to the first and second thin film transistors TFT3 and TFT4, respectively.

Each pixel PXL includes a display area RV in which the first pixel electrode 181 and the common electrode 171 cross in parallel with each other, and a viewing angle control area RC in which the second pixel electrode 183 is formed. It consists of.

The first thin film transistor TFT3 is connected to the first data line 120 to supply a data voltage to the first pixel electrode 181 positioned in the display area RV of the pixel PXL.

The second thin film transistor TFT4 is connected to the second data line 121 to supply a viewing angle control voltage to the second pixel electrode 183 positioned in the viewing angle control region RC of the pixel PXL.

FIG. 8 illustrates a vertical cross-sectional structure of the pixel shown in FIG. 7.

Referring to FIG. 8, the first thin film transistor TFT3 includes a gate electrode 111, a gate insulating film 101, a first semiconductor layer 190, and a first ohmic contact layer corresponding to a portion of the gate line 110. 191, the source electrode 120_5 and the drain electrode 120_6.

The first thin film transistor TFT3 is connected to the first lead line 180 and the first pixel electrode 181 through the first contact hole H3.

Similarly, the second thin film transistor TFT4 may include the gate electrode 112, the gate insulating layer 101, the second semiconductor layer 192, the second ohmic contact layer 193, corresponding to another region of the gate line 110. The source electrode 121_5 and the drain electrode 121_6 are included.

The second thin film transistor TFT4 is connected to the second pixel electrode 183 through the second contact hole H4.

When the array substrate 100 has the pixel PXL structure as shown in FIGS. 7 and 8, the first pixel electrode of the display area RV is opposite to the case in which the array substrate 100 has the pixel PXL structure of FIGS. 5 and 6. If the data voltage applied to the 181 is different from the viewing angle control voltage applied to the second pixel electrode 183 of the viewing angle control region RC, a wide viewing angle mode in which the same image can be viewed from the front and side surfaces is obtained. For example, in the wide viewing angle mode, a value such as a common voltage or a gamma voltage of a black level is applied as the viewing angle control voltage.

When the viewing angle control voltage applied to the viewing angle control region RC of the outer portion of the pixel PXL is equal to the data voltage applied to the display region RV of the center portion of the pixel PXL, black or the like in the lateral direction may be used. A near picture is implemented to enter the narrow viewing angle mode.

That is, when there is no potential difference between the data voltage applied to the first pixel electrode 181 and the viewing angle control voltage applied to the second pixel electrode 183, the narrow viewing angle mode is implemented. In addition, when the potential difference between the two voltages occurs because the data voltage applied to the first pixel electrode 181 and the viewing angle control voltage applied to the second pixel electrode 183 are different, the wide viewing angle mode is implemented. In this case, as the viewing angle control voltage applied to the second pixel electrode 183, a common voltage, a white level gamma voltage, or the like may be applied.

9A to 9D are perspective views illustrating processes of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention.

First, as illustrated in FIG. 9A, a plurality of pixels PXL arranged in a matrix form is formed on the array substrate 100. Each pixel PXL constituting the array substrate 100 includes a display area RV and a viewing angle control area RC, and includes a data voltage applied to the display area RV and a viewing angle applied to the viewing angle control area RC. It is configured to control the control voltage to vary the viewing angle.

Next, as illustrated in FIG. 9B, the color filter layer 210, the black matrix 220, the light control layer 230, and the like including the red, green, blue, and white color filters on the color filter substrate 200 may be used. To form.

Here, the color filter layer 210 and the black matrix 220 are formed on one surface of the color filter substrate 200 facing the array substrate 100 in a bonding process, and the light control layer 230 is a color filter substrate ( 200 is formed on the other side. The light control layer 230 is formed in a region corresponding to the viewing angle control region RC of the array substrate 100.

Next, as shown in FIGS. 9C and 9D, after the liquid crystal material LC is dropped on the array substrate 100 to form the liquid crystal layer 300, the color filter substrate is disposed with the liquid crystal layer 300 interposed therebetween. The 200 and the array substrate 100 are bonded to each other. In this case, the substrate for dropping the liquid crystal material LC may be the color filter substrate 200.

Here, the viewing angle Φ in the narrow viewing angle mode in which the viewing angle is minimized, the refractive index n of the substrate, the size A of the opening of the pixel PXL, and the pitch P of the pixel are configured to satisfy the above-described equations (1) to (3). Is efficient.

In addition, the size A of the opening of the pixel PXL is configured to be 1/2 to 1/4 of the pitch P of the pixel PXL so that the opening ratio securing side and the viewing angle control side can be balanced.

Subsequently, upper and lower polarizers 240 and 130 may be attached to the upper portion of the color filter substrate 200 and the lower portion of the array substrate 100 so that optical axes are perpendicular to each other.

10A to 10E are cross-sectional views illustrating the process of subdividing some steps of FIG. 9A. When the array substrate 100 of FIG. 9A has the pixel PXL structure as shown in FIGS. 5 and 6, the array substrate 100 is manufactured. The steps are illustrated in more detail.

First, the gate metal layer deposited on the array substrate 100 is patterned by a photo process and an etching process using a mask to form first and second gate electrodes 111 and 111 ′ as shown in FIG. 10A. .

Here, as shown in FIG. 5, first and second gate lines 110 and 110 s spaced up and down the pixel PXL are formed, and a portion of the first and second gate lines 110 and 110 s is formed. The region is defined by the first and second gate electrodes 111 and 111 '.

In this case, the first and second common electrodes 141 and 142 and the common line 140 connecting the common electrodes 141 and 142 to each other are formed together.

Next, as shown in FIG. 10B, the gate insulating film 101 is deposited on the entire surface.

In addition, an undoped amorphous silicon layer (ACT layer) and an n + amorphous silicon layer (Ohmic contact layer) and a source / drain metal layer (S / D layer) doped with a high concentration of n-type impurities are formed on the gate insulating layer 101. In order to deposit.

Next, as shown in FIG. 10C through the mask process, the first and second semiconductor layers 120_3 and 121_3 and the first and second ohmic contact layers 120_4 and 121_4 are formed on the gate insulating layer 101. A semiconductor pattern is formed. The source / drain metal pattern group including the first and second data lines 120 and 121, the first and second source electrodes 120_1 and 121_1, and the first and second drain electrodes 120_2 and 121_2 may be formed. Is formed.

Here, the first source electrode 120_1 and the second source electrode 121_1 are first and second data lines 120 and 121 spaced apart from each other in parallel to the left and right of the pixel PXL, as shown in FIG. 5. Extending from.

In more detail,

First, a photoresist pattern is formed on a source / drain metal layer by a photolithography process using a mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portions CH of the first and second thin film transistors TFT1 and TFT2 as a mask, the height of the photoresist pattern of the channel portion CH is lower than that of other portions. To have.

Subsequently, the source / drain metal layer (S / D layer) is patterned by a wet etching process using a photoresist pattern. Thus, the source / drain metal pattern group including the first and second data lines 120 and 121, the first and second source electrodes 120_1 and 121_1, and the first and second drain electrodes 120_2 and 121_2. Is formed.

Subsequently, the n + ohmic contact layer and the amorphous silicon layer (ACT layer) are simultaneously patterned by a dry etching process using the same photoresist pattern so that the first and second ohmic contacts 120_4 and 121_4 and the first and second The semiconductor pattern including the second semiconductor layers 120_3 and 121_3 is formed.

The photoresist pattern having a relatively low height is removed from the channel portion CH through an ashing process, and then the source / drain metal pattern and the channel portion CH of the channel portion CH are removed by a dry etching process. Some regions of the corresponding first and second ohmic contacts 120_4 and 121_4 are etched.

As a portion of the first ohmic contact layer 120_4 is etched in the channel portion CH, the first source electrode 120_1 and the first drain electrode 120_2 are separated. As the second resistive contact layer 121_4 is partially etched in the channel portion CH, the second source electrode 121_1 and the second drain electrode 121_2 are separated from each other.

Subsequently, the photoresist pattern remaining on the source / drain metal pattern group is removed by a stripping process.

Next, as shown in FIG. 10D, a protective film 101 covering the entire surface of the array substrate 100 is formed.

Next, as shown in FIG. 10E, after forming the passivation layer 101 covering the entire surface of the array substrate 100, the first and second drain electrodes 120_2 and 121_2 are exposed through the passivation layer 101. First and second contact holes H1 and H2 are formed.

After depositing the transparent conductive layer and etching, the first and second pixel electrodes 151 and 161 are formed on the passivation layer 101 as shown in FIG. 10E, and the plurality of first pixel electrodes 151 are formed. A second lead line 160 connecting the first lead line 150 and the second pixel electrode 161 to each other is formed.

The first pixel electrode 151 and the first common electrode 141 are formed parallel to each other on the display area RV of the pixel PXL, and the first pixel electrode 151 opens the first contact hole H1. It is connected to the first drain electrode 121_1 of the first thin film transistor TFT1 through and receives a viewing angle control voltage from the first data line 120.

The second pixel electrode 161 and the second common electrode 142 are formed parallel to each other on the viewing angle control region RC of the pixel PXL, and the second pixel electrode 161 is formed in the second contact hole H2. It is connected to the second drain electrode 121_2 of the second thin film transistor TFT2 through and receives a viewing angle control voltage from the second data line 121.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that.

Therefore, since the embodiments described above are provided to completely inform the scope of the invention to those skilled in the art, it should be understood that they are exemplary in all respects and not limited. The invention is only defined by the scope of the claims.

The array substrate according to the present invention, the liquid crystal display device using the array substrate, and the manufacturing method thereof according to the present invention made as described above are easier to manufacture compared to the method using a double liquid crystal panel, and the light is blocked within a range where cost is reduced. Can control transmission and viewing angle characteristics.

In addition, the array substrate according to the present invention, the liquid crystal display device using the array substrate, and a method of manufacturing the same can minimize the degradation of the front brightness or other operating characteristics when adjusting the viewing angle.

Claims (25)

An array substrate including a plurality of pixels in which a display area and a viewing angle control area are defined, and configured to control a data voltage applied to the display area and a viewing angle control voltage applied to the viewing angle control area; A color filter substrate disposed to face the array substrate and having a light control layer formed in a region corresponding to the viewing angle control region; And Liquid crystal layer formed between the array substrate and the color filter substrate Including; And a viewing angle is varied by the light control layer controlling the direction in which light is emitted and the viewing angle control region to which the viewing angle control voltage is applied. The method of claim 1, The display area and the viewing angle control area constituting the pixel, And forming a horizontal electric field to control the alignment of the liquid crystal layer. The method of claim 1, wherein the array substrate, A gate line formed on the substrate; First and second data lines intersecting with the gate line to define the pixel, and parallel to each other at left and right edges of the pixel; A first pixel electrode and a first common electrode formed to be parallel to each other in the display area of the pixel; A second pixel electrode and a second common electrode formed to be parallel to each other in the viewing angle control region of the pixel; A first thin film transistor connected to the first data line and supplying a data voltage to the first pixel electrode; And A second thin film transistor connected to the second data line and supplying a viewing angle control voltage to the second pixel electrode Liquid crystal display comprising a. The method of claim 1, wherein the array substrate, A gate line formed on the substrate; First and second data lines intersecting with the gate line to define the pixel, and parallel to each other at left and right edges of the pixel; A first pixel electrode and a common electrode formed in parallel with each other in the display area of the pixel; A second pixel electrode formed in the viewing angle control region of the pixel; A first thin film transistor connected to the first data line and supplying a data voltage to the first pixel electrode; And A second thin film transistor connected to the second data line and supplying a viewing angle control voltage to the second pixel electrode Liquid crystal display comprising a. The method of claim 1, The distance d from the pixel to the light control layer is relative to the viewing angle Φ in the narrow viewing angle mode, the refractive index n of the substrate, the size A of the opening of the pixel, and the pitch P of the pixel,

A liquid crystal display device characterized by satisfying the following equation. The method of claim 5, The size A of the opening of the pixel is 1/2 to 1/4 of the pitch P of the pixel. The method of claim 1, The display area is formed at the center of the pixel, And the viewing angle control area is formed by being divided into both sides of the display area. The method of claim 1, And the light control layer is a barrier of a metallic material or a lenticular lens. The method of claim 1, The color filter substrate includes a red, green, blue, and white color filter corresponding to each of the plurality of pixels. The method of claim 1, An upper polarizer positioned on the color filter substrate; And A lower polarizer disposed under the array substrate and having an optical axis in a direction perpendicular to the optical axis of the upper polarizer; Liquid crystal display further comprising. The method of claim 1, And the light control layer is positioned inside the upper polarizer in contact with the color filter substrate. A gate line formed on the substrate; First and second data lines intersecting with the gate line to define the pixel, and parallel to each other at left and right edges of the pixel; A first pixel electrode and a first common electrode formed parallel to each other in the display area of the pixel; A second pixel electrode and a second common electrode formed in parallel to each other in the viewing angle control region of the pixel; A first thin film transistor connected to the first data line and supplying a data voltage to the first pixel electrode; And A second thin film transistor connected to the second data line and supplying a viewing angle control voltage to the second pixel electrode; And the viewing angle is changed by the change of the data voltage and the viewing angle control voltage to switch between wide viewing angle mode and narrow viewing angle mode. The method of claim 12, And in the wide viewing angle mode, the data voltage applied to the first pixel electrode and the viewing angle control voltage applied to the second pixel electrode have the same value. The method of claim 12, And in the narrow viewing angle mode, the data voltage applied to the first pixel electrode and the viewing angle control voltage applied to the second pixel electrode have different values. The method of claim 14, The viewing angle control voltage is the same value as the common voltage applied to the first common electrode and the second common electrode. The method of claim 14, And the viewing angle control voltage is a gamma voltage of a black level. A gate line formed on the substrate; First and second data lines intersecting with the gate line to define a pixel, wherein the first and second data lines are formed parallel to each other at an outer portion of the pixel; A first pixel electrode formed in the display area of the pixel; A second pixel electrode and a common electrode formed in parallel to each other in the viewing angle control region of the pixel; A first thin film transistor connected to the first data line and configured to supply a data voltage to the first pixel electrode positioned in the display area of the pixel; And A second thin film transistor connected to the second data line and configured to supply a viewing angle control voltage to the second pixel electrode positioned in the viewing angle control region of the pixel; And the viewing angle is changed by the change of the data voltage and the viewing angle control voltage to switch between wide viewing angle mode and narrow viewing angle mode. The method of claim 17, And in the narrow viewing angle mode, the data voltage applied to the first pixel electrode and the viewing angle control voltage applied to the second pixel electrode have the same value. The method of claim 17, In the wide viewing angle mode, the data voltage applied to the first pixel electrode and the viewing angle control voltage applied to the second pixel electrode are different values. The method of claim 19, And the viewing angle control voltage is equal to a common voltage applied to the common electrode. The method of claim 19, And said viewing angle control voltage is a gamma voltage of a white level. a) forming an array substrate having a display area and a viewing angle control area formed of a plurality of pixels and controlling a data voltage applied to the display area and a viewing angle control voltage applied to the viewing angle control area to vary the viewing angle; ; b) forming a color filter substrate having a light control layer formed in a region corresponding to the viewing angle control region; And c) forming a liquid crystal layer on the array substrate or the color filter substrate, and then bonding the array substrate and the color filter substrate with the liquid crystal layer interposed therebetween. Method of manufacturing a liquid crystal display comprising a. The method of claim 22, wherein step a) a-1) forming first and second gate lines spaced above and below the pixel on a substrate, and intersecting the first and second gate lines on the display area and the viewing angle control area of the pixel; Forming first and second common electrodes disposed thereon, respectively; a-2) forming a gate insulating film covering the entire surface of the substrate; a-3) forming a first and a second semiconductor layer on the gate insulating layer so as to overlap a part of the first and second gate lines, the first source electrode and the first drain spaced apart from both sides of the first semiconductor layer Forming an electrode, a second source electrode and a second drain electrode spaced apart from both sides of the second semiconductor layer; a-4) forming a protective film covering the entire surface of the substrate; And a-5) forming a first pixel electrode connected to the first drain electrode on the display area, and forming a second pixel electrode connected to the second drain electrode on the viewing angle control area Method of manufacturing a liquid crystal display comprising a. The method of claim 22, In the above steps a) to c), the distance d from the pixel to the light control layer is determined by the viewing angle Φ in the narrow viewing angle mode, the refractive index n of the substrate, the size A of the opening of the pixel, and the pitch P of the pixel. about,

The manufacturing method of the liquid crystal display device characterized by including so that the following formula may be satisfied. The method of claim 24, The size A of the opening of the pixel is configured to be 1/2 to 1/4 of the pitch P of the pixel.

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