KR20080043153A - Command buffer of semiconductor memory device - Google Patents

Abstract

The present invention provides a buffer for receiving and buffering an external command, a delay unit for delaying and outputting a clock signal by a predetermined delay time, a pulse width adjusting unit for adjusting a pulse width of a command output from the buffer, and adjusting the pulse width. And a latch for latching the command using the clock signal output from the delay unit.

Description

Command Buffer for Semiconductor Memory Apparatus

1 is a block diagram of a command buffer of a semiconductor memory device according to the prior art;

2 is a waveform diagram of each part of a command buffer of a conventional semiconductor memory device;

3 is a block diagram of a command buffer of a semiconductor memory device according to the present invention;

4 is a block diagram illustrating an internal configuration of a first delay unit of FIG. 3;

5 is a circuit diagram of the pulse width adjusting unit of FIG. 3;

6 is an output waveform diagram of the pulse width adjusting unit of FIG. 3;

7 is a waveform diagram of each part of the command buffer of the semiconductor memory device according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10: buffer 20: latch

100: first delay unit 200: pulse width adjusting unit

210: second delay unit

The present invention relates to a command buffer of a semiconductor memory device which receives an input external command and outputs an internal command that can be used in the semiconductor memory device.

The command buffer of the semiconductor memory device according to the related art is provided for each command. As shown in FIG. 1, a buffer 10 for receiving and buffering an external command and outputting the command is shown in FIG. And a latch 20 for latching the output of the buffer.

The operation of the command buffer according to the conventional technology described above is as follows.

The buffer 10 receives an external command and converts the signal level into a level (eg, a CMOS level) that can be processed in the semiconductor memory device.

The latch 20 latches the output cmd of the buffer 10 according to a clock signal clkp to match the timing of the semiconductor memory device and outputs the internal command icmd.

In order for the latch 20 to latch the output cmd of the buffer 10, the setup time ts1 and the hold time th1 must be maintained for a predetermined time or more as shown in FIG. 2.

That is, the setup time ts1 is required to read the output cmd level of the buffer 10, and the output icmd level of the read buffer 10 may be recognized by another circuit configuration connected to the command buffer. Hold time (th1) is needed to keep it.

Currently, the frequency of the command input to the semiconductor memory device is gradually increasing, and as the frequency of the command is increased, the setup time and the hold time are decreasing.

However, since the command buffer of the semiconductor memory device according to the related art performs a command latch operation without a corresponding increase in frequency, the timing margin between the command and the clock signal clkp is insufficient and eventually does not latch the command normally. There is a problem.

An object of the present invention is to provide a command buffer of a semiconductor memory device capable of stably latching an input command in response to an increase in frequency.

The command buffer of the semiconductor memory device according to the present invention may include a buffer configured to receive and buffer an external command; A delay unit for delaying and outputting a clock signal by a predetermined delay time; A pulse width adjusting unit controlling a pulse width of the command output from the buffer; And a latch configured to latch the command in which the pulse width is adjusted by using a clock signal output from the delay unit.

Hereinafter, a preferred embodiment of a command buffer of a semiconductor memory device according to the present invention will be described with reference to the accompanying drawings.

As shown in FIG. 3, the command buffer of the semiconductor memory device according to the present invention is configured to delay and output a buffer 10 that receives and buffers an external command and a clock signal clkp by a predetermined delay time. The first delay unit 100, the pulse width control unit 200 for receiving a command (cmd) output from the buffer 10 to adjust the pulse width, that is, output the increased command (wide_cmd), and the pulse width A latch 20 for latching the increased command wide_cmd using the clock signal clkp_d output from the first delay unit 100 is provided.

The first delay unit 100 may be configured to have a fixed delay time, or may be configured to selectively use one of various delay times. When configured to have a fixed delay time may be composed of a resistor and a capacitor, or an inverter chain. In addition, an example in which one of various delay times can be selectively used is illustrated in FIG. 4.

As illustrated in FIG. 4, the first delay unit 100 includes a delay time controller 110 for outputting a control signal for adjusting a delay time, and a time corresponding to the clock signal clkp. The variable delay unit 120 outputs the delayed clock signal clkp_d by delaying by. The delay time controller 110 outputs the first control signal inc and incb to increase the delay time according to whether the first fuse F1 is cut, and the second fuse. And a second delay time controller 112 for outputting a second control signal (dec, decb) for reducing the delay time depending on whether or not F2 is cut.

The first delay time controller 111 may include a first fuse F1 having one end connected to a power supply terminal VDD, a first latch LT1 having an input terminal connected to the other end of the first fuse F1, and the first latch. The second inverter IV2 receiving the output of the LT1, the third inverter IV3 receiving the output of the second inverter IV2, the other end of the first fuse F1 and the first latch A source is connected between the input terminals of the LT1, a drain is connected to the ground terminal VSS, and the second transistor M2 receives the power-up pulse pwrup_p at the gate. The first latch LT1 has a first transistor M1 having a source connected to the other end of the first fuse F1 and a drain connected to the ground terminal VSS, and an input terminal connected to the other end of the first fuse F1. A first inverter IV1 connected to a stage and connected to a gate of the second transistor IV2 and the first transistor M1 is provided. The first control signal incb is output from the second inverter IV2, and the first control signal inc is output from the third inverter IV3.

The second delay time controller 112 may include a second fuse F2 having one end connected to a power supply terminal VDD, a second latch LT2 having an input terminal connected to the other end of the first fuse F2, and the second latch. A fifth inverter IV5 that receives the output of LT1, a sixth inverter IV6 that receives the output of the fifth inverter IV5, and the other end of the second fuse F2 and the second latch A source is connected between the input terminals of the LT2, a drain is connected to the ground terminal VSS, and a fourth transistor M4 receives the power-up pulse pwrup_p at a gate thereof. The second latch LT1 includes a third transistor M3 having a source connected to the other end of the second fuse F1 and a drain connected to the ground terminal VSS, and an input terminal connected to the other end of the second fuse F1. A fourth inverter IV4 connected to the stage and connected to the gate of the fifth inverter IV5 and the third transistor M3 is provided. The second control signal decb is output from the fifth inverter IV5, and the second control signal dec is output from the sixth inverter IV6.

The variable delay unit 120 receives the first and second delays delay_A and delay_B receiving the clock signal clkp and the output of the first delay_A at an input terminal and receives first and second control. A first pass gate PG1 receiving the second control signals dec and decb at a terminal, an output of the second delay_B at an input terminal, and receiving the second control signal at first and second control terminals. a second pass gate PG2 having a (decb, dec) input and an output terminal connected to the first pass gate PG1 in common, and an input terminal commonly connected to the output terminals of the first and second pass gates PG1 and PG2. A third pass gate PG3 that receives the first control signals inc and incb from first and second control terminals, and a third input terminal connected to output terminals of the first and second pass gates PG1 and PG2. Delay (delay_C), the output of the third delay (delay_C) is input to the input terminal and the first and second control terminals A fourth pass gate PG4 receives the first control signals inc and inc and has an output terminal connected to the third pass gate PG3 in common. The delayed clock signal clkp_d is output through the output terminals of the commonly connected third and fourth pass gates PG3 and PG4.

The first to third delays delay_A, delay_B, and delay_C of the variable delay unit 120 of the first delay unit 100 have different delay times. That is, the first delay delay_A has a delay time of 1/2 * d1, the second delay delay_B has 1/2 * d1−α, and the third delay delay_C has a delay time. Accordingly, a desired delay time may be set by selectively cutting the first fuse F1 and the second fuse F2 of the delay time controller 110. It is assumed that the delay time of the first delay unit 100 is d2.

If neither the first fuse F1 nor the second fuse F2 is cut, inc = low, incb = high, dec = low, and decb = high, so the delay time d2 of the first delay unit 100 is set to zero. The delay time of one delay (delay_A) is 1/2 * d1. Therefore, the clock signal clkp is delayed by 1/2 * d1 and output.

When only the first fuse F1 is cut, inc = high, incb = low, dec = low, and decb = high. Therefore, the delay time d2 of the first delay unit 100 is the first delay (delay_A) and the third delay. The delay time of (delay_C) is 1/2 * d1 + α. Therefore, the clock signal clkp is output by being delayed by 1/2 * d1 + α. That is, the delay time d2 when only the first fuse F1 is cut is increased compared to the delay time d2 when neither the first fuse F1 nor the second fuse F2 is cut.

When only the second fuse F2 is cut, inc = low, incb = high, dec = high, and decb = low, so the delay time d2 of the first delay unit 100 is delay time 1 of the second delay delay_B. / 2 * d1-a. Therefore, the clock signal clkp is output by being delayed by 1/2 * d1-α. That is, the delay time d2 when only the second fuse F2 is cut is reduced compared to the delay time d2 when neither the first fuse F1 nor the second fuse F2 is cut.

Therefore, the delay time may be adjusted by selectively cutting the first fuse F1 and the second fuse F2.

As shown in FIG. 5, the pulse width control unit 200 may delay the command cmd output from the buffer 10 by a predetermined time, and the buffer 10 from the second delay unit 210. And a logic element configured to perform an AND operation on the output command cmd and the output signal of the second delay unit 210 to output a command wide_cmd having an increased pulse width. The logic element receives a command cmd output from the buffer 10 and a NAND gate ND11 that receives an output signal of the second delay unit 210, and an output of the NAND gate ND11. An inverter IV11 outputting a command wide_cmd having an increased pulse width is included.

The second delay unit 210 may be configured in the same manner as the first delay unit 100 only with a difference in delay time. That is, the first delay unit 100 may be configured to have a fixed delay time or may be configured to selectively use one of various delay times.

The setup time and the hold time of the latch 20 are determined according to the delay time of the first delay unit 100, and the command cmd according to the delay time of the second delay unit 210. ) Pulse width is determined. In order for the setup time and the hold time to be the same, the delay time of the first delay unit 100 may be set to 1/2 of the delay time of the second delay unit 210. Details regarding the delay time setting will be described later.

The operation of the command buffer of the semiconductor memory device according to the exemplary embodiment configured as described above will be described with reference to FIGS. 6 and 7 as follows.

When a command is input from the outside, the buffer 10 performs a buffering operation of converting the signal level of the command to a level (eg, a CMOS level) that can be processed inside the semiconductor memory device.

The pulse width adjusting unit 200 delays the command cmd output from the buffer 10 by a predetermined delay time d1 of the second delay unit 210 and executes the command wide_cmd whose pulse width is increased. Output

The second delay unit 210 of FIG. 5 has a fixed delay time or a desired delay time is selected through selective cutting of the first and second fuses F1 and F2 when the configuration of FIG. 4 is used. to be. Assume that the delay time of the second delay unit 210 is d1. Therefore, as shown in FIG. 6, the command cmd output from the buffer 10 is delayed through the second delay unit 210 so that cmd_dly is output, and through the NAND gate ND11 and the inverter IV11. wide_cmd is printed with the pulse width increased by d1.

The first delay unit 100 receives the clock signal clkp and delays by a predetermined delay time d2 to output the delayed clock signal clkp_d.

The setup time ts2 and the hold time th2 are determined according to the delay time d2 of the first delay unit 100.

As shown in FIG. 7, the setup time ts2 and hold time th2 according to the present invention are increased compared to the setup time ts1 and hold time th1 according to the related art, and the following relationship is established. do.

Ts2 = ts1 + d2, th2 = th1 + d2

For example, the delay time d2 of the pulse signal clkp, that is, the delay time d2 of the first delay unit 100 is 1/2 of the increase time of the pulse width, that is, the delay time d1 of the second delay unit 210. When set to, the pulse width of the command cmd increased, but the clock signal clkp was also delayed by half of the increased pulse width. Therefore, the setup time ts2 and the hold time th2 become equal to each other.

According to the principle described above, when the delay time d2 of the first delay unit 100 is set to be larger than 1/2 of the delay time d1 of the second delay unit 210, the setup time ts2 is set to hold time ( longer than th2).

Similarly, when the delay time d2 of the first delay unit 100 is set to be smaller than 1/2 of the delay time d1 of the second delay unit 210, the hold time th2 is compared with the setup time ts2. Longer

As described above, the pulse width of the command cmd may be increased by setting the delay time d1 of the second delay unit 210 as desired, and the delay time of the first delay unit 100 may be increased. d2) to adjust the setup time (ts2) and hold time (th2).

By setting the delay time d2 of the first delay unit 100 to 1/2 of the delay time d1 of the second delay unit 210 so that the setup time ts2 and the hold time th2 are the same. Most preferably, the command cmd can be reliably latched.

However, when designing a semiconductor memory device, a setup time ts2 may be longer or a hold time th2 may be long depending on model-specific characteristics. Therefore, the present invention allows the setup time ts2 and hold time th2 to be adjusted to a desired level as necessary.

The latch 20 latches the command wide_cmd whose pulse width is increased according to the delayed clock signal clkp_d during the setup time ts2 and the hold time th2 and outputs the internal command icmd.

As described above, the setup time ts2 and hold time th2 according to the present invention have been increased in comparison with the prior art. Therefore, the latch 20 can perform a stable latch operation compared to the prior art.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The command buffer of the semiconductor memory device according to the present invention has the following effects.

First, since the setup time and hold time margin for latching the command can be secured as desired, a stable command latch is possible, thereby improving the high-speed operation characteristics of the semiconductor memory device.

Second, since the setup time and hold time ratio for latching the command can be adjusted as desired, it is possible to flexibly cope with the characteristic change of the semiconductor memory device.

Claims (13)

A buffer that receives and buffers an external command; A delay unit for delaying and outputting a clock signal by a predetermined delay time; A pulse width adjusting unit controlling a pulse width of the command output from the buffer; And And a latch configured to latch the command whose pulse width is adjusted using the clock signal output from the delay unit. The method of claim 1, The delay unit A delay time controller for outputting a control signal for adjusting the delay time; And a variable delay unit configured to delay and output the clock signal by a time corresponding to the control signal. The method of claim 1, The pulse width adjusting unit A second delay unit which delays the command output from the buffer by a predetermined time period, and And a logic element for calculating a command output from the buffer and an output signal of the second delay unit, and increasing the pulse width of the command output from the buffer to output the same. The method of claim 3, wherein The second delay unit A delay time controller for outputting a control signal for adjusting the delay time; And a variable delay unit configured to delay and output the clock signal by a time corresponding to the control signal. The method of claim 3, wherein And the logic element is configured to perform an AND operation. The method according to claim 2 or 4, The delay time controller A first delay time controller outputting a first control signal for increasing a delay time according to whether a fuse is cut or not; and And a second delay time controller for outputting a second control signal for reducing the delay time according to whether the fuse is cut. The method of claim 6, The first delay time controller Once the fuse connected to the power stage, A latch having an input terminal connected to the other end of the first fuse, A first inverting element receiving the output of the latch and outputting the first control signal; A second inverting element which receives the output of the first inverting element and outputs an inverted first control signal; and And a switching element connected between the other end of the fuse and the input end of the first inverting element to operate according to a power-up signal. The method of claim 6, The second delay time controller Once the fuse connected to the power stage, A latch having an input terminal connected to the other end of the first fuse, A first inverting element receiving the output of the latch and outputting the second control signal; A second inverting element which receives the output of the first inverting element and outputs an inverted second control signal; and And a switching element connected between the other end of the fuse and the input end of the first inverting element to operate according to a power-up signal. The method according to claim 2 or 4, The variable delay unit First delay, Second delay, A first switching device receiving an output of the first delay at an input terminal and a second control signal at first and second control terminals; A second switching element receiving an output of the second delay at an input terminal and receiving the inverted second control signal at first and second control terminals and having an output terminal commonly connected to the first switching element; A third switching element having an input terminal commonly connected to the output terminals of the first and second switching elements and receiving the first control signal to the first and second control terminals; A third delay at which an input terminal is connected to output terminals of the first and second switching elements, and A semiconductor comprising: a fourth switching element having an input of an output of the third delay and an inverted first control signal at a first and a second control terminal and having an output terminal commonly connected to the third switching element; Command buffer of the memory device. The method of claim 9, The first to third delays are different in delay time from the command buffer of the semiconductor memory device. The method of claim 1, And a delay time corresponding to the pulse width adjusted by the pulse width control unit and a delay time of the delay unit. The method of claim 1, And a delay time of the delay unit is 1/2 of a time corresponding to the pulse width adjusted by the pulse width adjusting unit. The method of claim 1, The delay time of the delay unit is determined according to a setup time and a hold time of the latch.

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