KR20080034603A - Method of manufacturig thin film transistor substrate and liquid display panel having the same - Google Patents

Abstract

A TFT(Thin Film Transistor) substrate manufacturing method and an LCD(Liquid Crystal Display) panel having the same are provided to form a connection electrode to be adjacent to an end of one pixel area, thereby displaying a stable texture in the pixel area by preventing formation of a singular point by the connection electrode and accordingly improving display quality of the LCD panel. An LCD panel comprises a color filter substrate, a TFT substrate and LC. The TFT substrate comprises the followings. In a TFT, source and drain electrodes(108,110) are formed. A pixel electrode unit is connected with the TFT, and comprises first and second pixel electrodes(150,160). A storage electrode is formed between the first and second pixel electrodes. A first connection electrode(152) is prolonged from the drain electrode to the storage electrode. A second connection electrode(162) is prolonged from the storage electrode to the second pixel electrode.

Description

A manufacturing method of a thin film transistor substrate, and a liquid crystal display panel having the same {METHOD OF MANUFACTURIG THIN FILM TRANSISTOR SUBSTRATE AND LIQUID DISPLAY PANEL HAVING THE SAME}

1 is a plan view illustrating a liquid crystal display panel according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal display panel taken along the line II ′ of FIG. 1.

3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

4 is a plan view illustrating a liquid crystal display panel according to a second exemplary embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor substrate taken along line II-II ′ of FIG. 4.

6A to 6G are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

102,202: gate line 106,206: gate electrode

104,204: data line 108,208: source electrode

110, 210: drain electrode 115: semiconductor layer

144,242 storage lower electrode 146,246 storage upper electrode

150,250: first pixel electrode 160,260: second pixel electrode

152,256: first connection electrode 162,266: second connection electrode

The present invention relates to a liquid crystal display panel, and more particularly, to a manufacturing method of a thin film transistor substrate capable of improving the display quality of a liquid crystal display panel and a liquid crystal display panel having the same.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display device includes a liquid crystal display panel for displaying an image and a driving circuit for driving the liquid crystal display panel.

The liquid crystal display panel includes a plurality of gate lines and data lines to drive sub pixels. The driving circuit includes a plurality of data integrated circuits for driving a plurality of data lines and a plurality of gate integrated circuits for driving a plurality of gate lines.

Since the liquid crystal display panel implements an image by transmitting light only in a direction that is not shielded by the liquid crystal, a viewing angle is relatively narrower than that of other display devices. Accordingly, a patterned vertical alignment (PVA) mode defining multiple domains has been proposed to realize a wide viewing angle. In a PVA mode in which one pixel area is divided into a plurality of pixel areas and one or more holes are formed on a common electrode corresponding to the plurality of pixel areas, a texture displayed on the pixel area is unstable. Therefore, the liquid crystal display panel of such a mode does not easily recover the liquid crystal even when a weak pressure is applied from the outside, causing a problem in display quality.

Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor substrate capable of improving the display quality of a liquid crystal display panel and a liquid crystal display panel having the same.

In order to achieve the above technical problem, the liquid crystal display panel of the present invention includes a color filter substrate; A thin film transistor substrate formed to face the color filter substrate; A liquid crystal formed between the color filter substrate and the thin film transistor substrate, the thin film transistor substrate comprising: a thin film transistor having source and drain electrodes formed thereon; A pixel electrode part connected to the thin film transistor and formed of first and second pixel electrodes; A storage electrode formed with the first and second pixel electrodes interposed therebetween; A first connection electrode extending from the drain electrode to the storage electrode; And a second connection electrode extending from the storage electrode and extending to the second pixel electrode.

Here, the first connection electrode is formed overlapping with the first pixel electrode and the organic passivation layer therebetween, and the second connection electrode is formed overlapping with the second pixel electrode and the organic passivation layer therebetween. do.

The first and second connection electrodes may be formed of the same material as the drain electrode.

In order to achieve the above technical problem, the liquid crystal display panel of the present invention includes a color filter substrate; A thin film transistor substrate formed to face the color filter substrate; A liquid crystal formed between the color filter substrate and the thin film transistor substrate, the thin film transistor substrate comprising: a thin film transistor having source and drain electrodes formed thereon; Source and drain regions of an active layer connected to the source and drain electrodes; A pixel electrode part connected to the thin film transistor and formed of first and second pixel electrodes; A plurality of storage capacitors for preventing a change in pixel voltage charged in the pixel electrode unit; And the first and second connection electrodes formed by extending the drain electrode and the drain region.

The first and second connection electrodes may be formed of the same material as the drain electrode, and may be formed of an active layer having conductivity by doping the same material or n + impurities as the drain region.

In order to achieve the above technical problem, a method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate electrode, a gate line, and a storage lower electrode on the substrate; Stacking a gate insulating film on a substrate on which the first conductive pattern group is formed; Forming a source and a drain electrode on the gate insulating film; Extending the first connection electrode to form a storage upper electrode; Extending from the storage upper electrode to form a second connection electrode; Stacking an organic passivation layer having a contact hole on a substrate on which the source and drain electrodes, the first and second connection electrodes, and the storage upper electrode are formed; And forming first and second pixel electrodes formed on the organic passivation layer.

Here, the first connection electrode overlaps the first pixel electrode and the organic passivation layer, and the second connection electrode overlaps the second pixel electrode and the organic passivation layer. do.

The first and second connection electrodes may be formed at the same time as the drain electrode, and may be formed of the same material.

According to an aspect of the present invention, there is provided a method of fabricating a thin film transistor substrate, the method comprising: forming a storage lower electrode by doping impurities with an active layer of a source and a drain region, and extending the drain region; Source and drain electrodes connected to the source and drain regions, and the drain electrode extending to form a storage upper electrode; Forming a first connection electrode by connecting the drain region to the lower storage electrode and connecting the drain electrode to the upper storage electrode; And extending the storage upper electrode and extending the storage lower electrode to form a second connection electrode.

The first and second connection electrodes may be formed of the same material as the drain electrode, and may be formed of an active layer having conductivity by doping the same material or n + impurities as the drain region.

Other technical problems and advantages of the present invention in addition to the above technical problem will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

1 is a plan view illustrating a liquid crystal display panel according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the liquid crystal display panel taken along line II ′ of FIG. 1.

1 and 2, the liquid crystal display panel includes a liquid crystal 100 between the thin film transistor substrate, the color filter substrate, and the thin film transistor substrate and the color filter substrate.

The color filter substrate includes a black matrix 170 for preventing light leakage, a color filter 172 for implementing color, a flattening layer 174 for compensating for the step by the color filter 172, and pixel electrode parts 150 and 160. A color filter array including a common electrode 178 forming a vertical electric field and holes 176 formed on a common electrode 178 corresponding to the first and second pixel electrodes 150 and 160 is formed on the upper substrate 101. Is formed.

The black matrix 170 divides the upper substrate 101 into a plurality of pixel areas in which the color filter 172 is to be formed, and prevents light interference and external light reflection between adjacent pixel areas. To this end, the black matrix 170 is formed on the upper substrate 101 to overlap at least one of the data line 104, the gate line 102, and the thin film transistor formed on the lower substrate 201.

The color filter 172 is formed for each of red (R), green (G), and blue (B) in the pixel area provided by the black matrix 170 to realize red (R), green (G), and blue (B). do.

The common electrode 178 is formed on the upper substrate 101 to control the movement of the liquid crystal using the supplied common voltage. Here, the common electrode 178 forms one or more holes 176 on the common electrode 178 corresponding to each of the first and second pixel electrodes 150 and 160. Meanwhile, the liquid crystal 100 rotates facing the hole 176 by a potential difference between the pixel electrode parts 150 and 160 and the common electrode 178.

The thin film transistor substrate illustrated in FIG. 2 includes a gate line 102 and a data line 104 formed to intersect on a lower substrate 101 with a gate insulating layer 126 interposed therebetween, and a thin film transistor TFT formed at each intersection thereof. And the pixel electrode parts 150 and 160 separated by the first and second pixel electrodes 150 and 160, and the storage capacitor Cst to prevent a change in the pixel voltage signal charged in the pixel electrode parts 150 and 160. Second connection electrodes 152 and 162 are provided.

The gate line 102 supplies a scan signal from the gate driver to the gate electrode 106 of the thin film transistor TFT. The data line 104 supplies a video signal to the source electrode 108 of the thin film transistor (TFT) from the data driver. The gate line 102 and the data line 104 are formed to cross each other to form a pixel area.

The thin film transistor TFT supplies a video signal of the data line 104 to the pixel electrode units 150 and 160 in response to the scan signal of the gate line 102. To this end, the thin film transistor TFT includes a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a drain electrode 110 connected to the pixel electrode parts 150 and 160. ) And an active layer 114 and a source electrode of the semiconductor pattern 115 that overlap the gate electrode 106 with the gate insulating layer 126 therebetween to form a channel between the source electrode 108 and the drain electrode 110. 108 and an ohmic contact layer 116 of the semiconductor pattern 115 formed on the active layer 114 except for the channel portion for ohmic contact with the drain electrode 110.

The drain electrode 110 is connected to the first and second connection electrodes 152 and 162. In other words, the first connection electrode 152 extends from the drain electrode 110 to the storage upper electrode 146, and the second connection electrode 162 is connected to the storage upper electrode 146 from the second pixel electrode ( 160). In detail, the first connection electrode 152 extends from the drain electrode 110 and overlaps the first pixel electrode 150 with the organic passivation layer 218 therebetween. In addition, the second connection electrode 118 extends from the storage upper electrode 146 and overlaps the second pixel electrode 160 with the organic passivation layer 118 therebetween. Meanwhile, the first and second connection electrodes 152 and 162 may be made of the same material as the drain electrode 110, for example, molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or an alloy thereof. do.

The pixel electrode parts 150 and 160 are positioned in the pixel area provided at the intersection of the data line 104 and the gate line 102 and are made of a transparent conductive material having high transmittance. The pixel electrode parts 150 and 160 are connected to the drain electrode 110 and the storage upper electrode 146 through the contact hole 120, and are formed on the organic passivation layer 118 applied to the entire surface of the substrate 101. The pixel electrode parts 150 and 160 generate a potential difference from the common electrode 178 by the data signal supplied through the thin film transistor TFT. The liquid crystal 100 rotates by this potential difference, and the light transmittance is determined according to the degree of rotation of the liquid crystal 100. Here, the pixel electrode unit is divided into first and second pixel electrodes 150 and 160. The first and second pixel electrodes 150 and 160 are formed to face each other with the storage upper electrode 146 therebetween.

The pixel area is divided into a first pixel area in which the first pixel electrode 150 is formed and a second pixel area in which the second pixel electrode 150 is formed. The liquid crystal 100 of the first pixel region rotates to face the hole 176 by a potential difference between the first pixel electrode 150 and the common electrode 178. When the first pixel region overlaps the first connection electrode 152 with the first pixel electrode 160 and the organic passivation layer 118 therebetween, no singular point is formed. In other words, the texture of the first pixel region is stably displayed because the first connection electrode 152 formed in the first pixel region does not form a singular point. Here, when the texture displayed in the first pixel area is, for example, X-shaped, a stable X-shaped texture is displayed by the first connection electrode 152. Conventionally, the texture displayed in the second pixel area has an unstable texture due to the singular point. In other words, when the texture displayed in the second pixel area is, for example, X-shaped, an unstable texture in which one end of the X-shaped is collected by the singular point is displayed. Accordingly, the second connection electrode 162 is formed to overlap the second pixel region with the second pixel electrode 160 and the organic passivation layer 118 interposed therebetween. In other words, the texture of the second pixel region is stably displayed similarly to the texture displayed on the first pixel region because no singular point is formed by the second connection electrode 162 formed in the second pixel region.

The storage capacitor Cst serves to suppress voltage fluctuations of the pixel electrode units 150 and 160. The storage capacitor Cst is formed by the storage upper electrode 146 connected to the pixel electrode parts 150 and 160 overlapping the storage lower electrode 144 with the gate insulating layer 126 interposed therebetween. The storage upper electrode 146 is formed to extend from the drain electrode 110 with the same material as the drain electrode 110. The storage upper electrode 146 is connected to the pixel electrode parts 150 and 160 through the pixel contact hole 120. The storage lower electrode 144 is supplied with a storage voltage through a storage line formed in parallel with the gate line 102.

3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

As shown in FIG. 3A, a first conductive pattern group including a gate line 102, a gate electrode 106, and a storage lower electrode 144 is formed on the lower substrate 101.

Specifically, after the gate metal layer is stacked on the lower substrate 101, the gate metal layer is patterned by a photolithography process and an etching process to include the gate line 102, the gate electrode 106, and the storage lower electrode 144. A first conductive pattern group is formed. Here, as the gate metal layer, a metal material such as molybdenum (Mo), copper (Cu), aluminum alloy (AlNd), aluminum (Al), chromium (Cr), or the like is used as a single layer or the metal material is laminated in two or more layers. It is used as a structure.

Referring to FIG. 3B, the gate insulating layer 126 is formed on the lower substrate 101 on which the first conductive pattern group is formed, and the semiconductor pattern 115 including the active layer 114 and the ohmic contact layer 116 is formed. Is formed.

In detail, the gate insulating layer 126 is formed by depositing an inorganic insulating material on the lower substrate 101 on which the first conductive pattern group is formed by a deposition method such as plasma enhanced chemical vapor deposition (PECVD). An amorphous silicon layer and an amorphous silicon layer doped with impurities are sequentially formed by the gate insulating layer 126 deposition method. Subsequently, the semiconductor pattern 115 including the active layer 114 and the ohmic contact layer 116 is formed by patterning the amorphous silicon layer and the amorphous silicon layer doped with impurities through a photolithography process and an etching process. As the gate insulating layer 126, an inorganic insulating material such as silicon nitride (SiOx), silicon oxide (SiNx), or the like is used.

Referring to FIG. 3C, the data line 104, the source electrode 108, the drain electrode 110, the storage upper electrode 146, and the first connection electrode are formed on the gate insulating layer 126 on which the semiconductor pattern 115 is formed. 152 and a second conductive pattern group including the second connection electrode 162 is formed.

In detail, the source / drain metal layer is formed on the gate insulating layer 126 on which the semiconductor pattern 115 is formed by a deposition method such as sputtering. As the source / drain metal layer, molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al) or alloys thereof are used in a single layer or a multilayer structure. The source / drain metal layer is patterned by a photolithography process and an etching process to thereby form the data line 104, the source electrode 108, the drain electrode 110, the first and second connection electrodes 152 and 162, and the storage upper electrode 146. A second conductive pattern group including a is formed. Subsequently, the ohmic contact layer 116 exposed between the two electrodes 108 and 110 is removed using the source electrode 108 and the drain electrode 110 as a mask so that the active layer 114 is exposed.

Referring to FIG. 3D, the passivation layer 118 including the pixel contact hole 120 is formed on the gate insulating layer 126 on which the second conductive pattern group is formed.

Specifically, a passivation layer is formed on the gate insulating layer 126 on which the second conductive pattern group is formed by a method such as plasma enhanced chemical vapor deposition (PECVD), spin coating, or spinless coating. In addition, the passivation layer 118 is patterned by a photolithography process and an etching process to form the pixel contact hole 120. In this case, an inorganic insulating material such as the gate insulating layer 126 may be used as the passivation layer 118, or an organic insulating material such as acrylic may be used.

Referring to FIG. 3E, a transparent conductive pattern including pixel electrode parts 150 and 160 is formed on the passivation layer 118.

Specifically, the transparent conductive layer is formed on the protective film 118 by a deposition method such as sputtering. Indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and the like are used as the transparent conductive layer. The pixel electrode parts 150 and 160 are connected to the storage upper electrode 146 through the pixel contact hole 120 and to the drain electrode 110 extended from the storage upper electrode 146.

4 is a plan view illustrating a liquid crystal display panel according to a second exemplary embodiment of the present invention, and FIG. 5 is a cross-sectional view of a thin film transistor substrate taken along line II-II ′ of FIG. 4.

The thin film transistor substrate shown in FIGS. 4 and 5 has a gate line 202 and a data line 204 formed to intersect on the lower substrate 201 with a gate insulating film 226 interposed therebetween, and the thin film transistor formed at each intersection thereof. (TFT), the pixel electrode portions 250 and 260 separated by the first and second pixel electrodes 250 and 260, and the first and second storages for preventing the variation of the pixel voltage signal charged in the pixel electrode portions 250 and 260. Capacitors Cst1 and Cst2 and first and second connection electrodes 256 and 266 are provided.

The gate line 202 supplies a scan signal from the gate driver to the gate electrode 206 of the thin film transistor TFT. The data line 204 supplies a video signal to the source electrode 208 of the thin film transistor (TFT) from the data driver. The gate line 202 and the data line 204 are formed to cross each other to form a pixel area.

The thin film transistor TFT charges a video signal to the pixel electrode units 250 and 260. To this end, the thin film transistor TFT may include a gate electrode 206 connected to the gate line 202, a source electrode 208 included in the data line 204, and a pixel contact hole 220 passing through the passivation layer 218. An active layer 214 is formed to form a channel between the source electrode 208 and the drain electrode 210 by the drain electrode 210 and the gate electrode 206 connected to the pixel electrode parts 250 and 260 through the gate electrode 206. Here, the thin film transistor TFT is formed of an N type or a P type, but only a case where the thin film transistor is formed of an N type will be described.

The active layer 214 is formed on the lower substrate 201 with the buffer layer 216 therebetween. The gate electrode 206 connected to the gate line 202 is formed to overlap the channel region 214C of the active layer 214 with the gate insulating film 226 interposed therebetween. The source electrode 208 and the drain electrode 210 are formed to be insulated with the gate electrode 206 and the interlayer insulating film 212 interposed therebetween. The source electrode 208 and the drain electrode 210 included in the data line 204 and the source contact hole 224S and the drain contact hole 224D that pass through the interlayer insulating film 212 and the gate insulating film 226. The n + impurity is connected to each of the source region 214S and the drain region 214D through each of them. In addition, the active layer 214 (Lightly Doped Drain (LDD) region (not shown) implanted with n- impurity between the channel region 214C and the source and drain regions 214S and 214D to reduce the off current. ) May be further provided. Here, the drain electrode 210 and the drain region 214D are connected to the first and second connection electrodes 256 and 266.

The first connection electrode 256 extends from the first upper connection electrode 252 and the drain region 214D extending from the drain electrode 210 to the storage upper electrode 246 to the storage lower electrode 242. The first lower connection electrode 254 is formed. The first connection electrode 256 extends from the drain electrode 210 and the drain region 214D and is formed in the first pixel region. The second connection electrode 266 extends from the second upper connection electrode 262 and the storage lower electrode 242 extending to the storage upper electrode 246 to the second pixel electrode 260 to extend the second pixel electrode ( A second lower connection electrode 264 formed up to 260 is formed. In addition, the second connection electrode 266 extends from the upper and lower storage electrodes 246 and 242 and is formed in the second pixel area. The first and second upper connection electrodes 252 and 262 may be made of the same material as the drain electrode 210, for example, molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or an alloy thereof. Is used. The second lower connection electrode 264 extends from the active layer 214, and a storage lower electrode 242 formed of an LTPS thin film doped with n + impurities extends to the second pixel electrode 260.

The pixel electrodes 250 and 260 are connected to each other by extending through the drain electrode 210 of the thin film transistor TFT, the pixel contact hole 220, and the storage upper electrode 246. 218 is formed. The pixel electrode parts 250 and 260 are formed of a transparent conductive film.

The storage capacitor Cst serves to suppress voltage variations of the pixel electrode units 250 and 260. The storage capacitor Cst is formed of first and second storage capacitors Cst1 and Cst2.

The first storage capacitor Cst1 overlaps the storage intermediate electrode 244 with the gate insulating layer 226 interposed between the storage lower electrode 242 made of an LTPS thin film extended from the active layer 214 and doped with n + impurities. Is formed. The second storage capacitor Cst2 is formed by the storage upper electrode 246 connected to the pixel electrode parts 250 and 260 overlapping the storage intermediate electrode 244 with the interlayer insulating layer 212 interposed therebetween. Here, the storage voltage is supplied through the storage line connected to the storage intermediate electrode 244.

6A to 6G are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to a second embodiment of the present invention.

Referring to FIG. 6A, a buffer layer 216 is formed on a lower substrate 201, and an active layer 214, a storage lower electrode 242, and a second lower connection electrode 264 are formed thereon.

The buffer layer 216 is formed by depositing an inorganic insulating material such as SiO ₂ on the lower substrate 201.

The active layer 214, the storage lower electrode, and the second lower connection electrode 264 deposit amorphous silicon on the buffer layer 216 and then crystallize the amorphous silicon with a laser to become poly-silicon. The poly-silicon is formed by patterning the photolithography process and the etching process. The storage lower electrode 242 and the second lower connection electrode 264 may be conductive by doping n + impurities.

Referring to FIG. 6B, the gate insulating layer 226 is formed on the buffer layer 216 on which the active layer 214, the storage lower electrode 242, and the second lower connection electrode 214 are formed, and the gate insulating layer 226 is formed. A first conductive pattern group including a gate line 202, a gate electrode 206, a storage intermediate electrode 244, and a storage line is formed thereon.

The gate insulating layer 226 is formed by depositing an inorganic insulating material such as SiO ₂ on the buffer layer 216 on which the active layer 214, the storage lower electrode 242, and the second connection lower electrode 264 are formed.

The gate electrode 206, the gate line 202, and the storage intermediate electrode 244 are formed by forming a gate metal layer on the gate insulating film 226, and then patterning the gate metal layer by a photolithography process and an etching process.

The n + impurity is implanted into the active layer 214 using the gate electrode 206 as a mask, so that the source region 214S and the drain region 214D of the active layer 214 that are not overlapped with the gate electrode 206 are formed. Is formed. The source and drain regions 214S and 214D of the active layer 214 face each other with the channel region 214C overlapping the gate electrode 206 interposed therebetween. Here, the drain region 214D of the active layer 214 extends to form a first lower connection electrode 254 connected to the storage lower electrode 242.

Referring to FIG. 6C, an interlayer insulating film 212 is formed on the gate insulating film 226 on which the first conductive pattern group is formed, and source and drain contact holes 224S penetrating the interlayer insulating film 212 and the gate insulating film 226. , 224D).

The interlayer insulating layer 226 is formed by depositing an inorganic insulating material such as SiO ₂ on the gate insulating layer 112 on which the first conductive pattern group is formed.

Subsequently, the source and drain contact holes 224S exposing the source and drain regions 214S and 214D of the active layer 214 through the interlayer insulating film 212 and the gate insulating film 226 by photolithography and etching processes, respectively. 224D).

Referring to FIG. 6D, the data line 204, the source electrode 208, the drain electrode 210, the first and second upper connection electrodes 256 and 266, and the storage upper electrode 246 are disposed on the interlayer insulating layer 212. A second conductive pattern group including is formed.

The second conductive pattern group including the data line 204, the drain electrode 210, the source electrode 208, the first and second upper connection electrodes 256 and 266, and the storage upper electrode 246 may include the interlayer insulating layer 212. After the source / drain metal layer is formed on the pattern, the source / drain metal layer is formed by photolithography process and etching process.

The source electrode 204 and the drain electrode 210 are connected to each of the source region 214S and the drain region 214D of the active layer 214 through the source and drain contact holes 224S and 224D, respectively.

Referring to FIG. 6E, a passivation layer 218 is formed on the interlayer insulating layer 226 on which the second conductive pattern group is formed, and a pixel contact hole 220 penetrating the passivation layer 218 is formed.

The passivation layer 218 is formed by depositing an entire surface of an organic insulating material such as an inorganic insulating material or photo acryl on the interlayer insulating film 212 having the second conductive pattern group formed thereon.

Subsequently, the pixel contact hole 220 penetrating the passivation layer 218 and / or the interlayer insulating layer 212 is formed by a photolithography process and an etching process. The pixel contact hole 220 penetrates the passivation layer 218 to expose the drain electrode 210 of the thin film transistor TFT.

Referring to FIG. 6F, a third conductive pattern group including pixel electrode parts 250 and 260 is formed on the passivation layer 218.

The third conductive pattern group including the pixel electrode parts 250 and 260 is formed by depositing a transparent conductive film such as ITO on the protective film 218 and then patterning the transparent conductive film by a photolithography process and a dry etching process.

As described above, in the method of manufacturing the thin film transistor substrate and the liquid crystal display panel having the same, the drain electrode of the thin film transistor is formed so that the connection electrode formed in a direction parallel to the data line is adjacent to the end of one pixel region. Accordingly, no singular point is formed due to the connection electrode, so that a stable texture is displayed in the pixel area, thereby improving display quality of the liquid crystal display panel.

Although the detailed description of the present invention described above has been described with reference to a preferred embodiment of the present invention, those skilled in the art or those skilled in the art, those skilled in the art, described in the claims below It will be understood that various modifications and changes can be made in the present invention without departing from the spirit and scope of the invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A color filter substrate; A thin film transistor substrate formed to face the color filter substrate; A liquid crystal formed between the color filter substrate and the thin film transistor substrate, The thin film transistor substrate A thin film transistor having source and drain electrodes formed thereon; A pixel electrode part connected to the thin film transistor and formed of first and second pixel electrodes; A storage electrode formed with the first and second pixel electrodes interposed therebetween; A first connection electrode extending from the drain electrode to the storage electrode; And a second connection electrode extending from the storage electrode and extending to the second pixel electrode. The method of claim 1, The first connection electrode overlaps the first pixel electrode and the organic passivation layer, and the second connection electrode is formed to overlap the second pixel electrode and the organic passivation layer. Display panel. The method of claim 2, The first and second connection electrodes are formed of the same material as the drain electrode. A color filter substrate; A thin film transistor substrate formed to face the color filter substrate; A liquid crystal formed between the color filter substrate and the thin film transistor substrate, The thin film transistor substrate A thin film transistor having source and drain electrodes formed thereon; Source and drain regions of an active layer connected to the source and drain electrodes; A pixel electrode part connected to the thin film transistor and formed of first and second pixel electrodes; A plurality of storage capacitors for preventing a change in pixel voltage charged in the pixel electrode unit; And first and second connection electrodes formed by extending the drain electrode and the drain region. The method of claim 4, wherein The first and second connection electrodes are formed of the same material as the drain electrode, and doped with the same material or n + impurities as the drain region to form a conductive active layer. Forming a first conductive pattern group including a gate electrode, a gate line, and a storage lower electrode on the substrate; Stacking a gate insulating film on a substrate on which the first conductive pattern group is formed; Forming a source and a drain electrode on the gate insulating film; Extending the first connection electrode to form a storage upper electrode; Extending from the storage upper electrode to form a second connection electrode; Stacking an organic passivation layer having a contact hole on a substrate on which the source and drain electrodes, the first and second connection electrodes, and the storage upper electrode are formed; And forming first and second pixel electrodes formed on the organic passivation layer. The method of claim 6, The first connection electrode overlaps the first pixel electrode and the organic passivation layer, and the second connection electrode is formed to overlap the second pixel electrode and the organic passivation layer. Method for manufacturing a transistor substrate. The method of claim 6, The first and second connection electrodes are formed at the same time as the drain electrode, the method of manufacturing a thin film transistor substrate, characterized in that formed of the same material. An active layer of source and drain regions, and the drain region extending to form a lower storage electrode by doping impurities; Source and drain electrodes connected to the source and drain regions, and the drain electrode extending to form a storage upper electrode; Forming a first connection electrode by connecting the drain region to the lower storage electrode and connecting the drain electrode to the upper storage electrode; And extending the storage upper electrode, and extending the storage lower electrode to form a second connection electrode. The method of claim 9, And the first and second connection electrodes are formed of the same material as the drain electrode, and doped with the same material or n + impurities as the drain region to form an active layer having conductivity.

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