KR20080029021A - Method of forming a trench - Google Patents

Abstract

A method for forming a trench is provided to bury easily an insulating layer in an inside of a trench by preventing generation of a stepped part between a second trench and a third trench. A substrate(100) is prepared. The substrate includes a cell region, a peripheral region, and a boundary region formed between the cell region and the peripheral region. At least one of first trenches is formed adjacent to the boundary region by performing a first patterning process for the substrate of the peripheral region. At least one of second trenches(144) is formed adjacent to the boundary region in the cell region by performing a second patterning process for the substrate of the cell region and the peripheral region. A plurality of third trenches deeper than the first trenched are formed in the peripheral region.

Description

Method of forming a trench

1 to 8 are schematic cross-sectional views illustrating a method of forming a trench according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 oxide film

104: conductive film 106: hard mask film

108: first photoresist pattern 116: first gate pattern

118: first opening 120: second photoresist pattern

128: second gate pattern 130: second opening

132: first trench 140: third gate pattern

142 thermal oxide film 144 second trench

146: third trench 148: field insulating film pattern

The present invention relates to a method of forming a trench. More specifically, the present invention relates to a method of forming a trench having a self aligned structure in a nonvolatile memory device.

Nonvolatile memory devices have the advantage of being able to preserve digital data semi-permanently even in the absence of power, and both write and erase electrically. Therefore, it is widely used for data storage of portable electronic products. Moreover, in recent years, the application field has been expanded to digital, MP3 players, mobile phone memory and the like.

The unit cell of the nonvolatile memory device may include a vertical stacked gate structure having a floating gate. Specifically, the gate of the nonvolatile memory cell has a structure in which a floating gate, a dielectric film, and a control gate are stacked on a tunnel oxide film.

In this case, as the design rule of the memory cell becomes smaller and smaller, there is a limit to performing a predetermined photo process on the floating gate. Accordingly, the limitation of the photolithography process may be overcome by forming a self-aligned polysilicon-shallow trench isolation (hereinafter referred to as SAP-STI) having a structure aligned with the field insulating layer pattern.

In general, in the method of forming a floating gate having an SAP-STI structure, first, a tunnel oxide film, a polysilicon film for floating gate, a silicon nitride film, and a photoresist pattern are sequentially formed. Using the photoresist pattern as an etching mask, the silicon nitride film, the polysilicon film, the tunnel oxide film, and the exposed semiconductor substrate are sequentially etched to form a trench.

This series of processes is formed together in the cell region and the peripheral region of the semiconductor substrate. The trench formed in the cell region (hereinafter referred to as a cell trench) and the trench formed in the peripheral region (hereinafter referred to as a peripheral trench) are formed to have different depths. That is, the peripheral trench is formed deeper than the cell trench.

As such, the depths of the cell trenches and the peripheral trenches are different from each other, and the trenches at the boundary between the cell region and the peripheral region have a step on the bottom. In other words, a portion of the trench formed at the boundary portion has a depth of the cell trench, and the other portion has a peripheral trench depth.

As described above, when the trench bottom has a step, it is not easy to fill the trench inside with the field insulating layer due to the step. As described above, when the trench is not completely filled by the field insulating film, and the upper water layer is formed on the field insulating film, the upper water layer may flow into a portion where the field insulating film is not buried. It can cause the bonding of the semiconductor device.

An object of the present invention for solving the above problems is to provide a method for forming a trench in which the generation of step difference in the bottom is suppressed at the boundary between the cell region and the peripheral region.

According to an aspect of the present invention for achieving the above object, in the method of forming a trench, a substrate including a cell region and a peripheral region, and a boundary region located between the cell region and the peripheral region is provided. The substrate of the peripheral region is first patterned to form first trenches at least one adjacent to the boundary region. Second patterning the substrates of the cell region and the peripheral region to form second trenches in the cell region adjacent to the boundary region and simultaneously forming a second trench deeper than the first trenches in the peripheral region from the first trenches; Form 3 trenches.

According to an embodiment of the present invention, the primary patterning may be performed by masking the cell region and the boundary region on the substrate, forming a photoresist pattern exposing the peripheral region, and etching the exposed substrate. Can be. The secondary patterning may form a photoresist pattern on the substrate to mask the boundary region, expose a first trench of the peripheral region and a substrate of the cell region, and etch the first trench and the exposed substrate. This can be done by. The trench forming method may further include sequentially forming an oxide film, a conductive film, and a mask film on the substrate, masking the peripheral and boundary regions, and forming a photoresist pattern partially exposing the mask film of the cell region. The method may further include forming a first gate pattern in the cell region by using the photoresist pattern as an etching mask. In this case, the primary patterning may include forming a second photoresist pattern on the substrate to mask the cell region and the boundary region, and to expose the mask layer of the peripheral region, and to form the mask layer and the conductive layer of the exposed peripheral region. The oxide film and the substrate may be sequentially etched to form a first trench and a second gate pattern, and at the same time, a third gate pattern may be formed on the boundary region. In this case, the second patterning may expose the first trenches and the cell regions of the peripheral region using the first gate pattern, the second gate pattern, and the third gate patterns of the peripheral region, the cell region, and the boundary region as etch masks. The prepared substrate can be etched.

According to the present invention as described above, the trenches formed in the peripheral region and the cell region have respective desired depths. Therefore, by suppressing the trench bottom step in the boundary region in advance, it is possible to prevent device defects that are subsequently generated.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited to the following embodiments, and those skilled in the art will appreciate the technical spirit of the present invention. The present invention may be embodied in various other forms without departing from the scope of the present invention. In the accompanying drawings, the dimensions of the substrate, film, region, pad or patterns are shown to be larger than the actual for clarity of the invention. In the present invention, when each film, region, pad or pattern is referred to as being formed "on", "upper" or "top surface" of a substrate, each film, region or pad, each film, region, Meaning that the pad or patterns are formed directly on the substrate, each film, region, pad or patterns, or another film, another region, another pad or other patterns may be additionally formed on the substrate. In addition, where each film, region, pad or pattern is referred to as "first," "second," and / or "third," it is not intended to limit these members but merely to define the respective film, region, pad or patterns To distinguish. Thus, "first", "second" and / or "third" may be used selectively or interchangeably for each film, region, pad or pattern, respectively.

Hereinafter, a method of forming a trench according to a preferred embodiment of the present invention will be described in detail.

1 to 8 are schematic cross-sectional views illustrating a method of forming a trench according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor substrate 100 including a cell region and a peripheral region and a boundary region positioned between the cell region and the peripheral region is prepared.

The boundary region serves as a guard band region as a boundary region between the cell region and the peripheral region.

The oxide film 102, the conductive film 104, and the hard mask film 106 are sequentially formed on the semiconductor substrate 100. In this case, the oxide film 102, the conductive film 104, and the hard mask film 106 are simultaneously formed in the cell region, the peripheral region, and the boundary region.

In more detail, first, an oxide film 102 is formed on the semiconductor substrate 100. The oxide layer 102 may then use a tunnel oxide layer of a nonvolatile memory device. The oxide layer 102 is thinly formed on the semiconductor substrate 100 by performing a thermal oxidation or chemical vapor deposition process on the semiconductor substrate 100.

A conductive film 104 is formed on the oxide film 102. The conductive layer 104 may then be used as a floating gate of the nonvolatile memory device. The conductive layer 104 may include polysilicon or a metal doped with impurities. In this case, when the conductive layer 104 includes polysilicon doped with an impurity, it may be formed by depositing pure polysilicon and then doping the impurity into the polysilicon layer.

A hard mask film 106 is formed on the conductive film 104. The hard mask layer 106 may include silicon nitride and may be formed using a chemical vapor deposition process, or the like.

Referring to FIG. 2, a first photoresist pattern 108 is formed to mask the peripheral region and the boundary region and partially expose the hard mask layer 106 of the cell region.

A portion exposed by the first photoresist pattern 108 is a portion where a second trench (cell trench) is to be formed, and a portion masked by the first photoresist pattern 108 is a memory cell to be formed later. Part.

Although not shown, before forming the first photoresist pattern 108, an amorphous carbon layer (ACL) and an anti-reflection layer (Anti-Reflection Layer) on the hard mask layer 106; ARL) can be further formed sequentially. The amorphous carbon film and the organic antireflective film are provided to prevent the sidewall profile of the first photoresist pattern 108 from being deteriorated by diffuse reflection in a subsequent photographic process. In particular, the organic anti-reflection film may be a silicon oxynitride layer (SiON), and may be removed while the first photoresist pattern 108 is removed.

Referring to FIG. 3, the hard mask layer 106, the conductive layer 104, and the oxide layer 102 of the cell region are sequentially etched using the first photoresist pattern 108 as an etching mask. The first gate pattern 116 on which the oxide film pattern 110, the conductive film pattern 112, and the hard mask film pattern 114 are sequentially formed is formed on the semiconductor substrate 100 in the cell region by the etching process. In addition, a first opening 118 is formed between the first gate pattern 116 to expose the semiconductor substrate 100 while the first gate pattern 116 is formed.

In this case, the etching process may be an anisotropic etching, for example, plasma dry etching.

Subsequently, after the first gate pattern 116 and the first opening 118 are formed, the first photoresist pattern 108 may be removed by an ashing or strip process.

Referring to FIG. 4, a second photoresist pattern 120 is formed to mask the cell region and the boundary region and partially expose the hard mask layer 106 of the peripheral region.

A portion of the portion exposed by the second photoresist pattern 120 is then formed with a third trench, and a portion of the portion exposed by the second photoresist pattern 120 is then formed with a logic cell.

Although not shown, an amorphous carbon film and an organic anti-reflection film may be sequentially formed on the hard mask film 106 before the second photoresist pattern 120 is formed. The amorphous carbon film and the organic antireflective film are provided to prevent the sidewall profile of the second photoresist pattern 120 from being deteriorated by diffuse reflection in a subsequent photographic process. In particular, the organic anti-reflection film may be a silicon oxynitride layer (SiON), and may be removed while the second photoresist pattern 120 is removed.

Referring to FIG. 5, the hard mask layer 106, the conductive layer 104, and the oxide layer 102 exposed to the peripheral region are etched using the second photoresist pattern 120 as an etching mask to form an oxide layer pattern ( 122, a second gate pattern 128 in which the conductive film pattern 124 and the hard mask film pattern 126 are sequentially stacked is formed. While the second gate pattern 128 is formed, a second opening 130 exposing the semiconductor substrate 100 is formed between the second gate pattern 128.

Subsequently, the exposed semiconductor substrate 100 is continuously etched to form the first trench 132. The etching process is anisotropic etching, for example, plasma dry etching.

After forming the second gate pattern 128 and the first trench 132, the second photoresist pattern 120 is removed by an ashing or strip process.

Meanwhile, during the etching process, the oxide layer pattern 134, the conductive layer pattern 136, and the hard mask layer pattern 138 are sequentially stacked on the boundary region that is a boundary region between the cell region and the peripheral region. The third gate pattern 140 is naturally formed. More specifically, first, referring to FIG. 3, one side of the third gate pattern 140 of the boundary region is etched while the first gate pattern 116 is formed in the cell region. In addition, while the third gate pattern 140 is formed in the peripheral region with reference to FIG. 4, the other side of the third gate pattern 140 of the boundary region is etched to form the third gate pattern 140 on the boundary region. Is formed.

Referring to FIG. 6, the resultant formed in FIG. 5 is treated by heat treatment.

In more detail, the first gate pattern 116, the second gate pattern 128, and the third gate pattern 140 formed in the peripheral region, the cell region, and the boundary region are patterned by plasma dry etching to form the gate. The patterns, the exposed substrate 100 and the first trenches 132 in the peripheral region are in a plasma damaged state. In order to cure this, the resultant is treated with In-Situ Steam Generation (ISSG).

Part of sidewalls of the first gate pattern 116, the second gate pattern 128, and the third gate pattern 140, the inside of the first trench 132, and the exposed semiconductor substrate during the ISSG process. A thin thermal oxide film 142 of about 150 Hz is formed on the 100.

Referring to FIG. 7, hard mask layer patterns 114, 126, and 138 of the first gate pattern 116, the second gate pattern 128, and the third gate pattern 140 may be used as an etching mask, respectively. The first trench 132 of the peripheral area is etched to expose the exposed semiconductor substrate 100 of the cell area.

A second trench 144 is formed in the cell region by the etching process, and third trenches 146 deeper than the first trench 132 are formed in the peripheral region from the first trenches 132. . That is, second trenches 144 are formed in the cell region, and third trenches 146 are formed in the peripheral region. In particular, the second trench 144 and the third trench 146 are formed in contact with the boundary region.

As such, first forming the first trenches 132 in the peripheral area, and then performing an etching process on the cell area and the peripheral area together, thereby forming the second trench 144 in the peripheral area and the third trench in the cell area. 146 may be formed. Therefore, no step is generated in the bottom of the second trench 144 and the third trench 146.

8, on the first gate pattern 116, the second gate pattern 128, and the third gate pattern 140 to completely fill the second trench 144 and the third trench 146. An insulating film (not shown) is formed in the film. The insulating film includes silicon oxide, and examples of the silicon oxide include an undoped silicate glass (USG) or a high density plasma (HDP) oxide film.

At this time, since there is no step in the bottom of the second trench 144 and the third trench 146, the insulating film is more easily buried, and thereafter, the problem that the upper material layer formed on the insulating film penetrates into the insulating film is not known. You can prevent it.

Subsequently, an insulating layer pattern 148 is formed by polishing an upper portion of the insulating layer to expose upper surfaces of the hard mask patterns of the first gate pattern 116, the second gate pattern 128, and the third gate pattern 140. . The polishing process may include an etch back process or a chemical mechanical polishing process.

As a result, a floating gate of a nonvolatile memory device having a structure in which a tunnel oxide film and a conductive film pattern are stacked between the insulating film pattern 148 and the insulating film pattern 148 is formed on the semiconductor substrate 100.

As described above, according to a preferred embodiment of the present invention, the first trench is formed in the first peripheral region by primary patterning, and the second trench is formed in the cell region by the second patterning and the third trench deeper than the first trench in the peripheral region. By forming together, it is possible to prevent the step difference between the bottom of the second trench and the third trench to be finally formed.

Therefore, since there is no step in the bottom of the trench, it is easier to embed the insulating film in the trench afterwards, and it is possible to prevent the upper material layer from immersing into the insulating film while the upper material layer is deposited on the insulating film.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (6)

Providing a substrate comprising a cell region and a peripheral region and a boundary region located between the cell region and the peripheral region; First patterning the substrate in the peripheral region to form first trenches at least one adjacent to the boundary region; And Second patterning the substrates of the cell region and the peripheral region to form second trenches in the cell region adjacent to the boundary region and simultaneously forming a second trench deeper than the first trenches in the peripheral region from the first trenches; Forming trenches; The method of claim 1, wherein the primary patterning, Forming a photoresist pattern on the substrate to mask the cell region and the boundary region and expose the peripheral region; And And etching the exposed substrate. The method of claim 1, wherein the secondary patterning, Masking the boundary region on the substrate and forming a photoresist pattern exposing the first trench of the peripheral region and the substrate of the cell region; And Etching the first trench and the exposed substrate. The method of claim 1, further comprising: sequentially forming an oxide film, a conductive film, and a mask film on the substrate; Masking the peripheral region and the boundary region and forming a photoresist pattern partially exposing the mask film of the cell region; And And forming a first gate pattern in the cell region by using the photoresist pattern as an etch mask. The method of claim 4, wherein the primary patterning is Forming a second photoresist pattern on the substrate to mask the cell region and the boundary region and expose a mask layer of the peripheral region; Sequentially etching the mask layer, the conductive layer, the oxide layer, and the substrate of the exposed peripheral region to form a first trench and a second gate pattern, and simultaneously forming a third gate pattern on the boundary region. Trench formation method. The method of claim 4, wherein the secondary patterning, Etching the first trench of the peripheral area and the exposed substrate of the cell area by using the first gate pattern, the second gate pattern, and the third gate pattern of the peripheral area, the cell area, and the boundary area as an etching mask. Trench formation method comprising a.

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