KR20080029574A - Method for fabricating recessed contact plug in semiconductor device by in situ etch - Google Patents

Abstract

A method for manufacturing a recessed contact plug in a semiconductor device is provided to easily adjust a depth of contact hole by using an in-situ etching process to form the contact hole. Plural gate patterns are formed on a semiconductor substrate(21). A gate spacer(25) is formed on a sidewall of the gate pattern. The semiconductor substrate between the gate patterns is recess-etched, such that a contact hole(27) is formed. A conductive layer(28) is deposited in the contact hole. The conductive layer is selectively removed to form a contact plug. The conductive layer is deposited by using an in-situ process right after the contact hole is formed.

Description

Method of forming recessed contact plug of semiconductor device by in-situ etching method {METHOD FOR FABRICATING RECESSED CONTACT PLUG IN SEMICONDUCTOR DEVICE BY IN SITU ETCH}

1A and 1B illustrate a method of forming a recess contact according to the prior art.

1C illustrates a contact surface of a recess contact according to the prior art.

2A to 2D are cross-sectional views illustrating a method of forming a contact plug in a semiconductor device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 gate oxide film

23: gate electrode 24: gate hard mask

25: gate spacer 26: source / drain

27: contact hole 28A: plug

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact for a semiconductor device.

As semiconductor devices become smaller and more integrated, the contact area decreases due to the decrease in contact size and the operating current decreases, resulting in device degradation such as poor tWR and deterioration of refresh characteristics. . Accordingly, many attempts have been made to lower the contact resistance of the device and to improve the operating current.

As a method for reducing contact resistance, there is a method of replacing a material having a low resistivity with a plug as much as possible, and an interface control method for reducing interface resistance occurring at an interface between a junction and a plug.

First, as a general method for lowering the resistivity of the plug material, a method of increasing the dopant concentration of the junction of the silicon substrate or a dopant concentration of the dopant in the polysilicon used as the plug is used.

However, the method of increasing the concentration as described above has a limitation in the method of increasing the concentration because the problem of deterioration of internal pressure due to dopant diffusion and deterioration of the refresh characteristics of the device.

As a second method of lowering the resistivity of the plug material, a metal material having a lower resistance than that of the silicon may be used instead of the conventional doped silicon.

Secondly, a fine oxide film is formed on the interface between polysilicon and silicon substrate due to the oxygen concentration present when loading the furnace under atmospheric pressure during polysilicon deposition to be used as a plug, which greatly affects the increase in contact resistance. It is known to give.

In order to overcome these problems, epitaxial silicon is formed in a single type CVD system, and the existing semiconductor device manufacturing process is applied as it is, but it can be deposited at low temperature and is sufficiently existing even at low concentration of doping. Applications such as selective epitaxy growth (SEG) and solid phase epitaxy (SPE) are expected to overcome the problems of polysilicon.

Currently, it is expected that the contact resistance can be greatly reduced by the interface control by SEG and SPE in sub-100 nm or less semiconductor devices. However, as the integration of the devices continues to be higher, the lower contact resistance must be maintained. Epitaxial silicon is also expected to show a limit.

Since epitaxial silicon also has a limit in terms of the resistivity of the material itself, it exhibits a specific resistance value of about 1E-3 mΩ-cm at the level of about 1E20 atoms / cm ³ in epitaxial silicon, and it is difficult to lower it below this level.

Therefore, it is necessary to develop a method having a contact resistance lower than that of the application of epitaxial silicon in the next-generation semiconductor device of sub 100 nm or less.

The various methods of reducing contact resistance as described above are focused on the selection of the plug material and the control of the interface, and it is very likely that it is difficult to satisfy the contact resistance in the next-generation semiconductor devices due to the above-mentioned limitations.

Therefore, the ultimate method for solving the increase in contact resistance caused by the decrease of the contact area requires a method of maintaining the actual contact area even when the high integration and the chip size are reduced. As shown in FIG. 1A, there is a method of forming a recess contact structure by etching more than a contact surface.

1A and 1B illustrate a method of forming a recess contact according to the related art.

Referring to FIG. 1A, a gate pattern stacked in the order of the gate oxide film 12, the gate electrode 13, and the gate hard mask 14 is formed on the semiconductor substrate 11, and then a gate spacer is formed on sidewalls of the gate pattern. (15) is formed.

Subsequently, the junction ion implantation for forming the source / drain 16 is performed, and the semiconductor substrate 11 between the gate patterns is recessed to a predetermined depth to form the contact hole 17.

As shown in FIG. 1B, after the conductive layer is deposited to fill the contact hole 17, the plug 18 is formed by etching and chemical mechanical polishing (CMP). Such a plug 18 has a recessed contact structure.

Referring to FIG. 1C, which shows a three-dimensional contact surface of the plug 18 in FIG. 1B, the recessed contact structure has a contact area of (A + 2B + 2C), whereas the contact area of the conventional structure is A, and the resistance is an area. Inversely proportional to the resistance decreases by the ratio 1 / A: 1 / (A + 2B + 2C).

However, this prior art, despite the increase in the contact area due to the recess, has been used in the subsequent processing between the contact and the junction due to the adsorption of the polymer and the generation of substrate defects by the ex-situ dry etching using plasma. Due to this, there is a problem in that an interface that is difficult to remove occurs, a loss of sidewalls of the gate spacers in the recess etching process, and a recess etching profile which is not suitable for subsequent plug deposition performed by epitaxial deposition is formed.

The present invention has been proposed to solve the above problems of the prior art, and it is possible to control the depth of the recess while preventing defects and loss of the gate spacer at the junction, and easy to control the interface between the plug and junction It is an object of the present invention to provide a method for forming a contact of a device.

A method of forming a contact of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a plurality of gate patterns on a semiconductor substrate; Forming a gate spacer on sidewalls of the gate pattern; Forming a contact hole by recess-etching the semiconductor substrate between the gate patterns in the state of being charged in the conductive layer deposition mechanism; Depositing a conductive layer in the contact hole; And selectively removing the conductive layer to form a contact plug, and after the forming of the contact hole, depositing the conductive layer continuously in-situ. The recess etching to form the contact hole is characterized by using a halogen-based gas.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

The present invention described below, without the use of the exo-situ dry etching using the plasma of the recess etch, By etching in-situ using the gas of halogen series such as HCl, C _l2 in the subsequent plug material vapor-deposit device, all the bonded area It does not cause any damage, and it is possible to control the depth of the recess while preventing the loss of the sidewall nitride film, and perfect interfacial control by depositing the plug immediately without exposure to the atmosphere after etching in the same chamber before deposition. By providing a recess etch profile suitable for a plug deposition process, a contact formation method can be provided that can reduce contact resistance in a high-density device by improving a reduction in contact size due to improved integration.

2A through 2D are cross-sectional views illustrating a method of forming a contact plug in a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 2A, a gate pattern is formed on the semiconductor substrate 21. In this case, the gate pattern is formed by sequentially forming the gate oxide film 22, the gate electrode 23, and the gate hard mask 24, and then performing gate patterning. Here, the gate oxide film 22 is SiO ₂ , and the gate electrode 23 is formed by using polysilicon alone or by depositing tungsten silicide or tungsten on polysilicon. The gate hard mask 24 is formed of a silicon nitride film (Si ₃ N ₄ ).

Subsequently, gate spacers 25 in contact with both side walls of the gate pattern are formed. In this case, the gate spacer 25 is formed through deposition of silicon nitride (Si ₃ N ₄ ) and etching back, and the surface of the semiconductor substrate 21 below the outside of the gate spacer 25 is partially formed by the etching back. Can be recessed.

Subsequently, junction ion implantation for the source / drain 26 is performed. In this case, the junction ion implantation is optimized by reflecting subsequent recess depth and final device characteristics. For example, the depth of the source / drain 26 by junction ion implantation is controlled deeper than the subsequent contact holes.

As shown in FIG. 2B, pretreatment is performed. At this time, the pretreatment removes impurities such as native oxide and the like at the interface where the plug is to be formed by excitation wet cleaning, dry cleaning or in situ surface treatment. For example, wet cleaning uses BOE (Buffered Oxide Etchant).

After the pre-treatment, the semiconductor substrate 31 is loaded into the deposition equipment of the conductive layer to be used as a plug, and then in-situ recess etch is performed in-situ to form contact holes 27. do. For example, in the conductive layer deposition apparatus, the contact hole 27 is formed by recessing the exposed surface of the semiconductor substrate 21 by a predetermined depth using a halogen-based gas in situ. Here, the halogen-based gas uses HCl or Cl ₂ . As such, when the recess is etched using a halogen-based gas, the recessed contact hole 27 can be formed while preventing the gate spacer 25 from being damaged. In addition, in the deposition process of the conductive layer to be used as a subsequent plug. A suitable etch profile can be obtained.

As described above, after the contact hole 27 is formed through the recess etching, a conductive layer to be used as a plug is continuously deposited without exposure to the atmosphere.

That is, as illustrated in FIG. 2C, the conductive layer 28 to be plugged into the contact hole 27 is deposited in situ. The conductive layer 28 may be formed of poly-silicon, epitaxial silicon, epitaxial silicon germanium, epitaxial silicon germanium carbon, epitaxial silicon silicon, and selective epitaxial silicon. SEG-Si), selective epitaxial silicon germanium (SEG-SiGe) or selective epitaxial silicon germanium carbon (SEG-SiGeC), or tungsten (W), titanium (Ti), cobalt (Co) or metal At least one metal material selected from silicides (Metal silicide).

2B and 2C, the recess etching for forming the contact hole 27 and the deposition of the conductive layer 28 for the plug proceed in situ. Plug deposition equipment is selected from among Low Pressure Chemical Vapor Deposition (LPCVD), Very Low Pressure CVD (VLPCVD), Plasma Enhanced CVD (PECVD), Ultra High Vacuum CVD (UHVCVD), Rapid Thermal CVD (RTCVD), or Atmosphere Pressure CVD (APCVD). Use any one selected.

As shown in FIG. 2D, etch back and chemical mechanical polishing (CMP) are subsequently performed on the conductive layer 28 to separate adjacent plugs 28A from each other.

According to the embodiment described above, the present invention has the following advantages.

First, in a method of etching by oxide dry etching or silicon dry etching using an existing plasma, a mixed etching gas is used to maintain a selectivity with other films stacked in the substrate, for example, an oxide film and a nitride film. At this time, the generation of the polymer is inevitable, which is finally adsorbed on the recessed surface and requires several processes for removal in a subsequent process, but the modified polymer once adsorbed is difficult to remove. In addition, the use of plasma also inevitably leads to defects in the recessed final surface, which causes an interface between the plug and the junction during subsequent plug deposition, and makes it difficult to control the plug deposition process, particularly in the selective deposition process of epitaxial silicon and silicon germanium. Facet, stacking faults may occur. In the present invention, in the same method as the plug deposition mechanism (Mechanism) in the plug deposition equipment by reacting the etching gas instead of the deposition gas does not cause any formation of polymers and defects on the final etching surface does not cause an interface problem to increase the contact resistance And makes it possible to stabilize the subsequent plug deposition process.

Second, in the case of the conventional dry etching, the selectivity with other films stacked on the substrate is controlled, but the thickness of the gate spacer using the nitride film is also reduced and the sidewall loss is minimized and it is necessary to adjust the density uniformly with the improvement of the density. . The in situ recess etching method according to the present invention does not cause loss of the formed gate spacer.

Third, in the conventional method of forming a recess contact by dry etching, even if the pretreatment before plug deposition is performed, the pretreatment and the deposition are performed separately, thus making it difficult to control the interface. In the present invention, since the recess is formed in the plug deposition apparatus after the standard wet treatment, and the plug deposition is performed in situ, it is possible to maintain a clean interface as compared with the conventional method.

Fourth, since the recess etching mechanism and the plug deposition mechanism are the same, an etching profile that is easy to deposit the plug can be made. This area is particularly effective in improving the quality of the deposited epitaxial thin films in the selective epitaxial silicon and silicon germanium deposition processes.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention described above forms contact holes through recess etching in situ in the deposition equipment of the conductive layer to be used as the plug, thereby preventing defects and loss of gate spacers at the interface between the plug and the depth of the contact hole. This has an easy effect.

In addition, the present invention can control the interface without impurities by continuously depositing a conductive layer to be used as a plug after contact hole formation.

In addition, by providing an etching profile suitable for the deposition process of the conductive layer to be used as a plug it has the effect of reducing the contact resistance in the high-density device by improving the reduction of the contact size due to the integration.

Claims (9)

Forming a plurality of gate patterns on the semiconductor substrate; Forming a gate spacer on sidewalls of the gate pattern; Forming a contact hole by recess-etching the semiconductor substrate between the gate patterns in the state of being charged in the conductive layer deposition mechanism; Depositing a conductive layer in the contact hole; And Selectively removing the conductive layer to form a contact plug Contact plug formation method of a semiconductor device comprising a. The method of claim 1, And depositing the conductive layer continuously in-situ after the forming of the contact hole. The method of claim 2, Recess etching to form the contact hole, Contact plug formation method of a semiconductor device using a halogen-based gas. The method of claim 3, The halogen-based gas is a contact plug forming method of a semiconductor device using HCl or Cl ₂ . The method of claim 1, The conductive layer, Poly-silicon, epitaxial silicon, epitaxial silicon germanium (Epitaxial SiGe), epitaxial silicon germanium (Epitaxial SiGeC), selective epitaxial silicon (SEG-Si), selective epitaxial Selected from silicon germanium (SEG-SiGe) or selective epitaxial silicon germanium carbon (SEG-SiGeC), or tungsten (W), titanium (Ti), cobalt (Co) or metal silicide (metal silicide) A method for forming a contact plug of a semiconductor device which is at least one metal material. The method of claim 5, The method of depositing the conductive layer may include low pressure chemical vapor deposition (LPCVD), very low pressure CVD (VLPCVD), plasma enhanced CVD (PECVD), ultra high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), or APCVD (Atmosphere). A method of forming a contact plug in a semiconductor device using any one selected from Pressure CVD. The method according to any one of claims 1 to 6, Before forming the contact hole, Performing junction ion implantation into the semiconductor substrate between the gate patterns; And Pretreatment to remove the interfacial material of the junction ion implanted surface Contact plug forming method of a semiconductor device further comprising. The method of claim 7, wherein The pretreatment is A method of forming a contact plug for a semiconductor device which proceeds by excitation wet cleaning, dry cleaning or in-situ surface treatment. The method of claim 7, wherein And a depth of the junction ion implantation deeper than that of the contact hole.

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