KR20080026236A - Thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

A thin film transistor display panel and a method for manufacturing the same are provided to form contact holes for penetrating gate and interlayer insulating layers by performing once an etching process using the same mask and etch liquid. A thin film transistor display panel includes gate and data lines(121,171), an interlayer dielectric layer(160), source and drain electrodes(193,195), an organic semiconductor(154), and a gate insulating layer(140). The gate lines include a gate electrode. The data lines are formed to cross with the gate lines. The interlayer dielectric layer insulates between the gate and data lines. The source electrodes are connected to the data lines. The drain electrodes are formed opposite to the source electrodes. The organic semiconductor is contacted with the source and drain electrodes. The gate insulating layer, which is formed between the gate electrode and organic semiconductor, has the same etch ratio as the interlayer dielectric layer.

Description

Thin film transistor array panel and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II.

3, 5, 7, 9 and 11 are layout views sequentially illustrating a method of manufacturing the thin film transistor array panel of FIGS. 1 and 2 according to an embodiment of the present invention.

4 is a cross-sectional view of the thin film transistor array panel of FIG. 3 taken along the line IV-IV.

FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI.

FIG. 8 is a cross-sectional view of the thin film transistor array panel of FIG. 7 taken along the line VIII-VIII.

FIG. 10 is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along the line X-X.

FIG. 12 is a cross-sectional view of the thin film transistor array panel of FIG. 11 taken along the line XII-XII.

<Description of Drawing>

110: insulating substrate 121: gate line

124: gate electrode 129: end of gate line

131: storage electrode line 140: gate insulating film

160: interlayer insulating film 154: organic semiconductor

171: data line 179: end of data line

81, 82: contact auxiliary members 141, 142, 143: contact holes

180: protective member

191: pixel electrode 193: source electrode

195: drain electrode Q: organic thin film transistor

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

In general, a flat panel display device such as a liquid crystal display (LCD), an organic light emitting diode display (OLED display), an electrophoretic display, or the like, includes a plurality of pairs of field generating electrodes and And an electro-optical active layer interposed therebetween. The liquid crystal display device includes a liquid crystal layer as the electro-optical active layer, and the organic light emitting display device includes an organic light emitting layer as the electro-optical active layer.

One of the pair of field generating electrodes is typically connected to a switching element to receive an electrical signal, and the electro-optical active layer converts the electrical signal into an optical signal to display an image.

In the flat panel display device, a thin film transistor (TFT), which is a three-terminal element, is used as a switching element. A data line to be transmitted is provided in the flat panel display.

Among these thin film transistors, studies on organic thin film transistors (OTFTs) including organic semiconductors instead of inorganic semiconductors such as silicon (Si) have been actively conducted.

The organic thin film transistor is attracting attention as a core element of a flexible display device because the organic thin film transistor may be formed in a fiber or film form due to the nature of the organic material.

  The organic thin film transistor array panel in which the organic thin film transistors are arranged in a matrix form has a different structure compared to the conventional thin film transistor, and thus, the number of masks required to manufacture the organic thin film transistor array panel increases.

Accordingly, the technical problem to be achieved by the present invention is to reduce the number of masks required to manufacture the organic thin film transistor.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes a gate line including a gate electrode, a data line intersecting the gate line, an interlayer insulating layer insulating the gate line and the data line, a source electrode connected to the data line, and the A drain electrode facing the source electrode, an organic semiconductor in contact with the source electrode and the drain electrode, and a gate insulating layer positioned between the gate electrode and the organic semiconductor and having the same etching ratio as the interlayer insulating layer.

The interlayer insulating layer and the gate insulating layer may include the same material.

The interlayer insulating film and the gate insulating film may include silicon nitride.

A protective member covering the organic semiconductor may be further included, and the protective member may include a soluble organic material.

A method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention includes forming a data line, forming an interlayer insulating film on the data line, forming a gate line on the interlayer insulating film, and forming a gate insulating film on the gate line. Forming a pixel electrode including a source electrode connected to the data line and a drain electrode facing the data insulating layer, forming an organic semiconductor in contact with the source electrode and the drain electrode; Forming a protective member on the organic semiconductor.

The forming of the protective member may be performed by an inkjet printing method.

The forming of the organic semiconductor may be performed by deposition using a shadow mask.

The forming of the interlayer insulating film and the forming of the gate insulating film may be deposited under the same conditions.

The method may further include forming contact holes penetrating the interlayer insulating film and the gate insulating film after the forming of the gate insulating film, wherein the contact holes may be formed using the same mask.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right over" but also when there is another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

 1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along a line II-II.

A plurality of data lines 171 and a plurality of storage electrode lines 131 are formed on an insulating substrate 110 made of transparent glass, silicon, or plastic. It is.

The data line 171 transmits a data signal and mainly extends in the vertical direction. Each data line 171 includes a plurality of projections 173 protruding sideways and a wide end portion 179 for connection with another layer or an external driving circuit. A data driving circuit (not shown) for generating a data signal is mounted on a flexible printed circuit film (not shown) attached to the substrate 110, directly mounted on the substrate 110, or integrated in the substrate 110. Can be. When the data driving circuit is integrated on the substrate 110, the data line 171 may be extended to be directly connected to the data driving circuit.

The storage electrode line 131 receives a predetermined voltage and extends substantially in parallel with the data line 171. Each storage electrode line 131 is positioned between the two data lines 171 and is close to the right side of the two data lines 171. However, the shape and arrangement of the storage electrode line 131 may be modified in various ways.

The data line 171 and the storage electrode line 131 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, gold-based metal such as gold (Ag) or gold alloy, or copper ( Copper-based metals such as Cu) and copper alloys, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, and low resistance conductors such as chromium (Cr), tantalum (Ta), and titanium (Ti). However, they may have a multilayer structure including two conductive films (not shown) with different physical properties.

An interlayer insulating layer 160 is formed on the data line 171 and the storage electrode line 131. The interlayer insulating layer 160 may be made of an insulating material such as silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ). The thickness of the interlayer insulating layer 160 may be about 2,000 μm to 4 μm.

A plurality of gate lines 121 are formed on the interlayer insulating layer 160.

The gate line 121 transmits a gate signal and mainly extends in a horizontal direction to cross the data line 171 and the storage electrode line 131. Each gate line 121 includes a plurality of gate electrodes 124 protruding upwards and a wide end portion 129 for connection with another layer or an external driving circuit. A gate driving circuit (not shown) that generates a gate signal is mounted on a flexible printed circuit film (not shown) attached over the substrate 110, directly mounted on the substrate 110, or integrated into the substrate 110. Can be. When the gate driving circuit is integrated on the substrate 110, the gate line 121 may extend to be directly connected to the gate driving circuit.

The gate line 121 may be made of a low resistance conductor like the data line 171 and the storage electrode line 131.

The side surface of the gate line 121 is also inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30 ° to about 80 °.

The gate insulating layer 140 is formed on the gate line 121. The gate insulating layer 140 may be made of an insulating material such as silicon nitride or silicon oxide, and is preferably made of the same material as the interlayer insulating layer 160. In this case, the gate insulating layer 140 and the interlayer insulating layer 160 are deposited under the same conditions using the same material, and have the same film quality and etching ratio.

A plurality of contact holes 141 are formed in the gate insulating layer 140, and a plurality of contact holes 142 and 143 are formed in the gate insulating layer 140 and the interlayer insulating layer 160.

A plurality of source electrodes 193, a plurality of pixel electrodes 191, and a plurality of contact assistants 81 and 82 are formed on the gate insulating layer 140. They can be made of ITO or IZO and their thickness can be from about 300 kPa to about 2000 kPa.

ITO or IZO is a conductive material that does not have a large work function difference from the organic semiconductor. The source electrode 193 and the drain electrode 195, which are in direct contact with the organic semiconductor 154, are made of ITO or IZO to form an organic material. The Schottky barrier can be lowered between the semiconductor and the electrode to facilitate carrier injection and movement.

The source electrode 193 is connected to the data line 171 through the contact hole 143 and extends over the gate electrode 124.

The pixel electrode 191 includes a portion (hereinafter, referred to as a “drain electrode”) 195 facing the source electrode 193 around the gate electrode 124.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 through the contact holes 141 and 142, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portion 129 of the gate line 121 and the end portion 179 of the data line 171 and the external device.

A plurality of island type organic semiconductor islands 154 are formed on the source electrode 193 and the drain electrode 195.

The organic semiconductor 154 may include a derivative including a substituent of tetratracene or pentacene. The organic semiconductor 154 may also include oligothiophenes comprising 4 to 8 thiophenes linked at the 2, 5 positions of the thiophene ring.

The organic semiconductor 154 may be polythienylenevinylene, poly-3-hexylthiophene, polythiophene, phthalocyanine, metallized phthalocyanine or metallized phthalocyanine thereof. Halogenated derivatives. The organic semiconductor 154 may also include perylenetetracarboxylic dianhydride (PTCDA), naphthalenetetracarboxylic dianhydride (NTCDA) or imide derivatives thereof. The organic semiconductor 154 may include a derivative including perylene or coronene and substituents thereof.

The thickness of the organic semiconductor may be about 300 kPa to 5,000 kPa.

The protection member 180 covering the organic semiconductor 154 is formed on the organic semiconductor 154. The protection member 180 is for protecting the organic semiconductor 154 from external heat and chemical liquids, and includes a material that does not affect the organic semiconductor 154, such as polyvinyl alcohol (PVA) or fluorine. It may be made of a polymer compound such as a polymer.

One gate electrode 124, one source electrode 193, and one drain electrode 195 form one thin film transistor (TFT) Q together with the organic semiconductor 154. A channel (Q) is formed in the organic semiconductor 154 between the source electrode 193 and the drain electrode 195.

The pixel electrode 191 generates an electric field together with a common electrode (not shown) of another display panel (not shown) which receives a data voltage from the thin film transistor Q and receives a common voltage. This determines the direction of the liquid crystal molecules of the liquid crystal layer (not shown) between the two electrodes. The pixel electrode 191 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off.

The pixel electrode 191 overlaps the storage electrode line 131 to form a storage capacitor, which enhances the voltage holding capability of the liquid crystal capacitor.

Next, a method of manufacturing the thin film transistor shown in FIGS. 1 and 2 will be described in detail with reference to FIGS. 3 to 12.

3, 5, 7, 9 and 11 are layout views sequentially illustrating a method of manufacturing the thin film transistor array panel of FIGS. 1 and 2 according to an embodiment of the present invention, and FIG. 4 is a thin film of FIG. 3. 6 is a cross-sectional view of the transistor panel cut along the line IV-IV, and FIG. 6 is a cross-sectional view of the thin film transistor array panel of FIG. 5 taken along the line VI-VI, and FIG. 8 is a VIII-VIII of the thin film transistor array panel of FIG. 10 is a cross-sectional view of the thin film transistor array panel of FIG. 9 taken along the line XX, and FIG. 12 is a cross-sectional view of the thin film transistor array panel of FIG. 11 taken along the line XII-XII. .

First, a conductive layer is stacked on the substrate 110 by a method such as sputtering, and photo-etched, thereby including data including a protrusion 173 and an end portion 179 as shown in FIGS. 3 and 4. The line 171 and the storage electrode line 131 are formed.

Next, as shown in FIGS. 5 and 6, silicon nitride is chemical vapor deposited (CVD) to form an interlayer insulating layer 160.

Subsequently, the conductive layer is stacked on the interlayer insulating layer 160 and photo-etched to form the gate line 121 including the gate electrode 124 and the end portion 129.

Next, as shown in FIGS. 7 and 8, silicon nitride is chemically vapor deposited to form the gate insulating layer 140. At this time, the gate insulating layer 140 and the interlayer insulating layer 160 are formed by setting the same deposition conditions, for example, deposition gas, deposition pressure, and temperature. Accordingly, the gate insulating layer 140 and the interlayer insulating layer 160 may be formed of substantially the same film quality.

Subsequently, the gate insulating layer 140 and the interlayer insulating layer 160 are photo-etched to expose the end portions 129 of the gate lines 121, the protrusions 173 and the end portions 179 of the data lines 171, respectively. Contact holes 141, 143, and 142 are formed. As described above, since the gate insulating layer 140 and the interlayer insulating layer 160 are made of the same material and film quality, the etching ratio is the same. Therefore, contact holes 142 and 143 may be formed through the gate insulating layer 140 and the interlayer insulating layer 160 by one etching using the same mask and etching solution.

Next, as shown in FIGS. 9 and 10, after sputtering ITO or the like and photographing etching, the pixel electrode 191 including the drain electrode 195, the source electrode 193, and the contact auxiliary members 81 and 82 are formed. To form.

Next, as shown in FIGS. 11 and 12, an organic semiconductor 154 is formed over the source electrode 193 and the drain electrode 195. The organic semiconductor 154 may be formed by a deposition method using a shadow mask (not shown).

Next, as shown in FIGS. 1 and 2, the protection member 180 is formed on the organic semiconductor 154 by an inkjet printing method. In this case, the inkjet printing method is formed by spraying a solution for a protective member onto each pixel without a separate partition.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of the invention.

The number of masks required to manufacture the organic thin film transistor array panel can be reduced.

Claims (9)

A gate line including a gate electrode, A data line intersecting the gate line, An interlayer insulating film insulating the gate line and the data line; A source electrode connected to the data line and a drain electrode facing the source electrode; An organic semiconductor in contact with the source electrode and the drain electrode, and A gate insulating layer disposed between the gate electrode and the organic semiconductor and having the same etching ratio as that of the interlayer insulating layer Thin film transistor array panel comprising a. In claim 1, The thin film transistor array panel of which the interlayer insulating layer and the gate insulating layer include the same material. In claim 2, The thin film transistor array panel of which the interlayer insulating layer and the gate insulating layer include silicon nitride. In claim 1, Further comprising a protective member for covering the organic semiconductor, The protective member includes a soluble organic material. Forming a data line, Forming an interlayer insulating film on the data line; Forming a gate line on the interlayer insulating film, Forming a gate insulating film on the gate line; Forming a pixel electrode on the gate insulating layer, the pixel electrode including a source electrode connected to the data line and a drain electrode facing the data electrode; Forming an organic semiconductor in contact with the source electrode and the drain electrode, and Forming a protective member on the organic semiconductor Method of manufacturing a thin film transistor array panel comprising a. In claim 5, The forming of the protective member may be performed by an inkjet printing method. In claim 6, The forming of the organic semiconductor may be performed by deposition using a shadow mask. In claim 5, The forming of the interlayer insulating film and the forming of the gate insulating film may include depositing the same material under the same conditions. In claim 8, After forming the gate insulating film Forming a contact hole penetrating the interlayer insulating film and the gate insulating film; The contact hole is formed of the same mask and the same etching liquid manufacturing method of a thin film transistor array panel.

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