KR20080024896A - Method of gain estimation for vco and frequency synthesizer using the method - Google Patents

Abstract

A method for measuring a gain of a VCO(Voltage Controlled Oscillator) and a frequency synthesizer are provided to decrease power consumption of the frequency synthesizer by stopping the operation of a measuring loop and a calibration unit at a normal mode. A frequency synthesizer includes an oscillator(240), a main loop(210), and a measuring loop(220). The oscillator generates an oscillation signal having a frequency corresponding to a magnitude of a control signal. The main loop is activated at a normal mode, and receives the oscillation signal. The main loop compares the oscillation signal with a first reference signal, generates the control signal according to the compared result, and provides the control signal to the oscillator. The measuring loop is activated at a measuring mode, and receives the oscillation signal. The measuring loop sequentially changes the frequency of the oscillation signal by a predetermined amount and provides the control signal to the oscillator according to the frequency of the oscillation signal.

Description

Method of measuring gain of voltage controlled oscillator and frequency synthesizer using same

1 is a block diagram of a phase locked loop that is a representative example of a frequency synthesizer.

2 is a block diagram illustrating a frequency synthesizer according to an embodiment of the present invention.

3 illustrates a method of approximating the magnitude of a control voltage to measure the gain of an oscillator.

4 is a circuit diagram illustrating a pull-down current source in a charge pump including a frequency synthesizer that can be calibrated according to an embodiment of the present invention.

5 is a block diagram illustrating a configuration of sharing a high rate feedback divider in a phase locked loop according to an embodiment of the present invention.

6 is a flowchart illustrating a method of measuring oscillator gain in a frequency synthesizer and calibrating a characteristic of the frequency synthesizer according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

210: main loop

220: measurement loop

230: correction unit

240: oscillator

The present invention relates to a frequency synthesizer, and more particularly to a voltage controlled oscillator in a frequency synthesizer.

Many modern electronic devices often require high frequency signals. For example, almost all digital systems require high frequency clock signals, and many analog systems require radio frequency (RF) signals, local oscillation signals, and the like. These high frequency signals not only need to be stably supplied, but also need to be supplied with various frequencies in some cases. Such a circuit for supplying high frequency signals is called a frequency synthesizer or a clock generator, and a phase locked loop is a representative example.

In general, frequency synthesizers, such as phase locked loops, generate high frequency signals using oscillators controlled by voltage or current. In order for a frequency synthesizer to stably generate a wide range of signals of various frequencies, the oscillator must have such characteristics.

Representative oscillators that have been used conventionally are ring oscillators and LC (LC) oscillators. The ring oscillator is an annular coupling of a plurality of delay cells having the same delay characteristics and is an oscillator extracting an oscillation signal from the output of any one of the delay cells. The ring oscillator may adjust the frequency of the oscillation signal by using a property in which a delay characteristic of the delay cell changes according to a power supply voltage or a supply current supplied to the delay cell. The LC oscillator includes an inductor L and a capacitor C, and generates an oscillation signal by using the resonance characteristics of the inductor and the capacitor.

In general, a ring oscillator has a wide frequency range (tuning range) of oscillation signals that can be generated, but poor phase noise characteristics. In contrast, the LC oscillator has a narrow tuning range but good phase noise characteristics. However, the narrow tuning range of the LC oscillator can be overcome by using a capacitor array configured to digitally adjust the capacitance.

In a digital system, the phase of the clock signal is important, so the LC oscillator with better phase noise characteristics of the oscillation signal is more suitable. By the way, the capacitance of the capacitor array changes considerably sensitive to process changes, and because the capacitors in the capacitor array also have errors, they may not match each other. Thus, the frequency characteristics of the capacitor array may differ from the desired characteristics. Different frequency characteristics can result in different gains of the oscillator, different loop characteristics of the frequency synthesizer, and may result in an oscillation signal of the desired frequency. This is an unavoidable problem in the process. In general, after the circuit is manufactured, the loop characteristics can be measured and the characteristics of the elements in the circuit can be calibrated to obtain an oscillation signal of a desired frequency.

1 is a block diagram of a phase locked loop that is a representative example of a frequency synthesizer. Referring to FIG. 1, a typical phase locked loop 10 includes a phase / frequency detector (PFD) 11, a charge pump 12, a loop filter 13, a voltage controlled oscillator 14 and a minute. A frequency divider 15. The phase / frequency detector 11 detects whether the phase of the divided signal VCO_N is fast or slow by comparing the transition period of the divided signal VCO_N in which the oscillation signal VCO_OUT is divided with the reference signal REF. The detection result is output as up / down signals UP and DN. The charge pump 12 includes a pull-up current source 121 and a pull-down current source 122, and adjusts a control voltage V _CON based on the up / down signals UP and DN. The loop filter 13 suppresses the influence of switching noise and the like of the charge pump 12 and maintains the magnitude of the control voltage V _CON . The voltage controlled oscillator 14 generates an oscillation signal VCO_OUT having a frequency that varies according to the control voltage V _CON . The voltage controlled oscillator 14 may be replaced with a current controlled oscillator, except that the current controlled oscillator converts the control voltage V _CON into a control current. The divider 15 divides the frequency of the oscillation signal VCO_OUT at a predetermined division ratio 1 / N. When the frequency of the oscillation signal VCO_OUT is low, the divider 15 is not necessarily required.

The characteristics of the phase locked loop 10 may be represented by a loop bandwidth and a damping factor. The loop bandwidth and the damping rate may be expressed by Equation 1 below.

[Equation 1]

Where K _VCO is the gain of the voltage controlled oscillator, I _CP is the current supplied by the charge pump, N is the division ratio of the divider, C _P is the size of the capacitor in the loop filter, and R _P is the size of the resistance in the loop filter. Each of these variables is represented.

In reality, in the case of using an LC oscillator, the gain of the oscillator realized through the semiconductor process often does not have a designed characteristic, and it should be considered that the gain will not be constant from the beginning. In addition, the higher the frequency of the oscillation signal, the larger the frequency division ratio of the frequency divider and the larger the gain of the oscillator. In this case, the influence of the gain change on the characteristics of the phase locked loop increases.

Therefore, in order for the phase locked loop to generate an oscillation signal having a desired characteristic, it is very important to accurately know the change in gain of the internal oscillator.

It is an object of the present invention to provide a frequency synthesizer having means for measuring the gain of an oscillator contained therein.

Another object of the present invention is to provide a method for measuring the gain of an oscillator included in a frequency synthesizer.

It is still another object of the present invention to provide a method for measuring the gain of an oscillator included in a frequency synthesizer to generate an oscillation signal of a desired frequency.

The frequency synthesizer according to an embodiment of the present invention includes an oscillator, a main loop and a measurement loop. The oscillator generates an oscillation signal having a frequency corresponding to the magnitude of the control signal. The main loop operates in a normal mode, receives the oscillation signal, compares it with a first reference signal, generates the control signal according to the comparison result, and provides the oscillation signal to the oscillator. The measurement loop operates in a measurement mode, receives the oscillation signal and changes the frequency of the oscillation signal in order by a predetermined magnitude, and transmits the control signal to the oscillator according to a change result of the frequency of the oscillation signal. to provide.

According to an embodiment, the main loop may include a charge pump in which the magnitude of the charge pump current is corrected according to the calibration signal in the calibration mode, and generates the corrected charge pump current according to the comparison result in the normal mode. The frequency synthesizer measures the magnitude of the control signal to be changed in the measurement mode, and generates and provides the calibration signal to the main loop based on the gain of the oscillator calculated from the measurement result in the calibration mode. It may further include a calibration unit.

In this case, the calibration unit may include an analog-to-digital converter for measuring the magnitude of the control signal to be changed into a digital measurement value, and a digital processor for generating the m-bit digital code of the calibration signal based on the digital measurement value. In this case, the charge pump has m current units each outputting a current represented by a power of 2 with respect to the reference current, and m current units capable of activating the m current units according to the calibration signal, respectively. And switches to sum the currents from the activated current units and output the sum pump current.

According to an embodiment, the main loop may be configured to divide the oscillation signal with a first division ratio and compare it with the first reference signal, wherein the measurement loop divides the oscillation signal with a second division ratio and The frequency division of the oscillation signal may be changed by changing the second division ratio by one. The main loop may be configured to sequentially divide the oscillation signal into a high division ratio and a first low division ratio, and the measurement loop may be configured to divide an oscillation signal divided into a high division ratio in the main loop at a second low division ratio. In this case, a value obtained by multiplying the high division ratio by the first low division ratio is the same as the first division ratio, and a value obtained by multiplying the high division ratio by the second low division ratio is the same as the second division ratio.

According to another aspect of the present invention, there is provided a method of measuring a gain of an oscillator in a frequency synthesizer. Generating; Measuring the magnitude of the control signal while repeatedly changing the frequency of the oscillation signal by a predetermined magnitude; And obtaining a gain of the oscillator from the ratio of the change amount of the frequency of the oscillation signal and the change amount of the magnitude of the control signal measured.

According to an embodiment, measuring the magnitude of the control signal may include: dividing the oscillation signal with a predetermined division ratio; And changing the frequency of the oscillation signal by changing the predetermined division ratio by one.

According to another aspect of the present invention, there is provided a method of driving a frequency synthesizer, the method comprising: generating an oscillation signal having a frequency varying according to a magnitude of a control signal applied; Measuring the magnitude of the control signal by changing the control signal while sequentially changing the frequency of the oscillation signal by a predetermined magnitude, and calibrating a frequency synthesizer based on the measurement result; And generating the oscillation signal with the calibrated frequency synthesizer.

According to an embodiment, the frequency synthesizer may include a charge pump having a calibrated current source, wherein calibrating the frequency synthesizer may change the amplitude of the control signal while repeatedly changing the frequency of the oscillation signal by a predetermined magnitude. Measuring; Obtaining a gain of the oscillator from the ratio of the change amount of the frequency of the oscillation signal and the change amount of the magnitude of the control signal measured; Generating a calibration signal by comparing the gain of the oscillator to an ideal gain; And calibrating the current source based on the calibration signal such that the charge pump generates a calibrated current. In this case, the control signal is measured as a digital value, the calibration signal may be a digital code of m bits.

According to an embodiment, measuring the magnitude of the control signal may include: dividing the oscillation signal with a predetermined division ratio; And changing the frequency of the oscillation signal by changing the predetermined division ratio by one.

With respect to the embodiments of the present invention disclosed in the text, specific structural to functional descriptions are merely illustrated for the purpose of describing embodiments of the present invention, embodiments of the present invention may be implemented in various forms and It should not be construed as limited to the embodiments described in.

As the inventive concept allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. In describing the drawings, similar reference numerals are used for the components.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

When a component is referred to as being "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that other components may be present in between. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between," or "neighboring to," and "directly neighboring to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "having" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions of the same elements are omitted.

2 is a block diagram illustrating a frequency synthesizer according to an embodiment of the present invention. Referring to FIG. 2, the phase locked loop 200 includes a main loop 210, a measurement loop 220, a calibrator 230, and a voltage controlled oscillator 240 as a representative example of the frequency synthesizer.

The phase locked loop 200 has an operation mode of measurement mode, calibration mode and normal mode. In the measurement mode, the measurement loop 220, the calibrator 230, and the voltage controlled oscillator 240 operate. In the calibration mode, only the calibrator 230 operates, and in the normal mode, the main loop 210 and the voltage are operated. The control oscillator 240 is operated.

The main loop 210 includes a first reference divider 211, a first phase / frequency detector 212, a first charge pump 213, a first loop filter 214, and a first feedback divider 215. It includes. The main loop 210 does not operate while the phase locked loop 200 operates in the measurement mode and the calibration mode. The first reference divider 211 divides an input signal IN input from the outside at a predetermined first reference division ratio M ₁ and outputs the first reference signal REF1 having a first reference frequency. do. The first phase / frequency detector 212 compares the transition period of the first divided signal VCO_N1 in which the oscillation signal VCON_OUT is divided with the first reference signal REF1 to compare the phase of the first divided signal VCO_N1. It detects whether it is fast or slow and outputs the detection result as the first up / down signals UP1 and DN1. The first charge pump 213 includes a pull-up current source 213a and a pull-down current source 213b and is controlled based on the first up / down signals UP1 and DN1. Adjust the voltage (V _CON ). The pull-up current source 213a and the pull-down current source 213b operate complementarily according to the first up / down signals UP1 and DN1 to generate charge pump currents I _CP having the same magnitude. The first loop filter 214 suppresses the influence of switching noise generated and propagated in the circuit and maintains the control voltage V _CON .

At this time, the pull-up current source 213a and the pull-down current source 213b of the first charge pump 213 do not operate in the measurement mode and the calibration mode, except that each of the charge pump currents I _CP supplied by each of them in the calibration mode. The setpoint has a configuration in which the setpoint is calibrated according to the calibration signal CAL.

The voltage controlled oscillator 240 generates an oscillation signal VCO_OUT having a frequency that varies according to the control voltage V _CON . In some embodiments, the voltage controlled oscillator may be replaced with a current controlled oscillator, which functions in the same manner except that the control voltage is converted into a control current.

Referring to Equation 1 for a while, the variables of Equation 1 may be arbitrarily adjusted by the designer without difficulty even after the circuit is completed, excluding the K _VCO which is the gain of the voltage controlled oscillator 240. Therefore, even if the gain K _VCO of the voltage controlled oscillator 240 does not have a desired characteristic, the desired characteristic can be obtained as a whole by adjusting other variables.

However, when the loop bandwidth and the damping rate of Equation 1 are well discussed, the capacitance CP of the first loop filter 214 is in the denominator at the loop bandwidth ω _{n and} in the numerator at the damping ratio ξ. Therefore, adjusting the capacitance CP cannot correct the error of the gain of the voltage controlled oscillator 240. On the other hand, since the charge pump current (ICP) is present in the molecules of both the loop bandwidth ω _n and the damping ratio ξ, adjusting this can correct the error of the gain of the voltage controlled oscillator. The measuring loop 220, and calibration unit 230 by correcting the detected gain error, and the charge pump current (I _CP) of the voltage controlled oscillator 240, the phase-locked loop 200 is the desired loop bandwidth ω _n may have a damping ratio ξ.

The measurement loop 220 includes a second reference divider 221, a second phase / frequency detector 222, a second charge pump 223, a second loop filter 224, and a second feedback divider 225. It includes. The measurement loop 220 operates only while the phase locked loop 2200 operates in the measurement mode. The second reference divider 221 divides the input signal IN at a predetermined second reference division ratio M ₂ , and divides the divided input signal with a second reference frequency REF2. Will output The second phase / frequency detector 222 compares the transition period of the second divided signal VCO_N2 in which the oscillation signal VCO_OUT is divided with the second reference signal REF2 to compare the phase of the second oscillation signal VCO_N2. It detects whether it is fast or slow and outputs the detection result as the second up / down signals UP2 and DN2. The second charge pump 223 adjusts the control voltage V _CON based on the second up / down signals UP2 and DN2. The second loop filter 223 suppresses the influence of switching noise generated and propagated in the circuit and maintains the control voltage V _CON .

While the phase locked loop 200 operates in the measurement mode, the calibrator 230 measures the gain of the voltage controlled oscillator 240. When the phase locked loop 200 operates in the calibration mode, the calibrator 230 generates a calibration signal CAL based on the measured control voltage V _CON , and generates the calibration signal CAL. 213 to provide for calibration of the charge pump current I _CP . According to an embodiment, the voltage controlled oscillator may be replaced with a current controlled oscillator, which receives a control current generated by voltage-to-current conversion of the control voltage. Therefore, even in this case, the calibration unit 230 may measure the gain of the voltage controlled oscillator 240 in the same manner.

In this case, since the gain of the voltage controlled oscillator 240 is a ratio between the input control voltage V _CON and the frequency of the oscillation signal VCO_OUT, it means a voltage-frequency characteristic of the voltage controlled oscillator 240. According to an embodiment, in order to obtain a voltage-frequency characteristic, the magnitude of the control voltage V _CON in the measurement loop 220 is changed over time, and the calibration unit 230 accordingly changes the frequency of the oscillation signal VCO_OUT. You can also measure how. On the other hand, in the phase locked loop 200 of FIG. 2, the measurement loop 220 changes the frequency of the oscillation signal VCO_OUT with time, and accordingly, the correction unit 230 adjusts the magnitude of the control voltage V _CON . By measuring how is changed, the voltage-frequency characteristic is obtained.

At this time, the gain curve of the voltage controlled oscillator 240 may be obtained by measuring the change of the control voltage V _{CON in} real time while continuously changing the frequency of the oscillation signal VCO_OUT, but in order to obtain a realistic gain value It is not reasonable to implement a circuit that measures the change in voltage in real time.

3 illustrates a method of approximating the magnitude of the control voltage to measure the gain of the voltage controlled oscillator.

The second phase / frequency detector 222 of FIG. 2 compares the frequency of the second reference signal REF2 with the frequency of the second divided signal VCO_N2, and as a result, the frequency of the second divided signal VCO_N2. The phase is synchronized with the frequency and phase of the second reference signal REF2. If the second feedback division ratio N ₂ is an integer and its magnitude is changed by 1, the frequency of the oscillation signal VCO_OUT is changed by the frequency of the second reference signal REF2 than the previous value.

Referring to FIG. 3, the second feedback division ratio at the first time point is N ₂ , and accordingly, the frequency of the oscillation signal is f ₁ . At this time, the magnitude of the control voltage measured by the calibration unit is V ₁ . When the second feedback division ratio becomes N ₂ +1 at the second time point, the frequency of the oscillation signal is f ₂ and has a value of f ₁ + fREF. At this time, the magnitude of the control voltage measured by the calibration unit is V ₂ . Since the gain of the voltage controlled oscillator is a value of frequency / voltage, this value is not largely error even if it is obtained as the value of the frequency change / voltage change. The gain of the voltage controlled oscillator can be obtained as shown in Equation 2 below.

[Formula 2]

DELTA V represents the difference between the measured values of the control voltages.

By continuously measuring the magnitude of the control voltage while continuously changing the second feedback division ratio, the gain characteristics of the voltage controlled oscillator can be measured from these measurements.

Referring back to FIG. 2, the calibration unit 230 includes an analog-to-digital converter (ADC) 231 and a digital processor (DSP) 232. The ADC converts the analog measurement of the control voltage (V _CON ) into n bits of digital measurement data and provides it to the digital processor 232. The ADC does not require high precision and high speed.

The resolution of the ADC 231 may be expressed as Equation 3 below.

[Equation 3]

The numerator of Equation 3 is the maximum value that the control voltage V _CON can have, that is, a value within a range obtained by subtracting the operating voltage V _OV applied to the current sources in the second charge pump 223 from the power supply voltage V _DD . Indicates. The denominator ΔV represents the minimum change in the control voltage V _CON to be measured.

For example, when the power supply voltage is 5V and the voltage across the current sources in the second charge pump 223 is 0.7V, even a low speed ADC with a resolution of 7 to 8 bits may cause the voltage controlled oscillator 240 to be sufficiently accurate. A gain curve can be obtained.

The digital processor 232 receives the n-bit digital measurement data and generates an m-bit calibration signal CAL.

According to an exemplary embodiment, independent ADC and DSP may be used without implementing the calibrator 230 together with the phase locked loop 200.

The performance of the phase locked loop 200 depends on how constant the loop bandwidth ω _n shown in Equation 1 and the damping ratio ξ are maintained. If the gain of the voltage controlled oscillator 240 is measured to be greater than the ideal value, the magnitude of the charge pump current I _CP is reduced, thereby reducing the loop bandwidth ω _n of the phase locked loop 200 when operating in the normal mode. The damping ratio ξ can be made to the desired value. Conversely, if the gain of the voltage controlled oscillator 240 is measured smaller than the ideal value, the loop bandwidth ω _n and the damping ratio ξ can be made desired by increasing the magnitude of the charge pump current I _CP . The digital processor 232 thus generates the calibration signal CAL such that the first charge pump 213 generates a charge pump current I _CP of an appropriate magnitude.

4 is a circuit diagram illustrating a pull-down current source in a charge pump including a frequency synthesizer that can be calibrated according to an embodiment of the present invention.

3 and 4, the pull-down current source 40 in the charge pump includes a current source 41 for generating a reference current I ₀ , a mirror transistor 42 connected in series with the current source 41, and the mirror transistor. M NMOS transistors 43, 44, 45 having an area ratio of two powers of 42 to form a current mirror structure, and the NMOS transistors 43 according to each bit of the calibration signal CAL. M, switches 46, 47, and 48 are used to control the drain currents.

The drains of the m NMOS transistors 43, 44, and 45 are all connected, and the drain currents are summed and output as the charge pump current I _CP . When the switches 46, 47, and 48 are turned on / off by the calibration signal CAL and the corresponding NMOS transistor is turned on / off, the charge pump current I _CP is reduced or increased by that amount.

After the measurement of the gain of the voltage controlled oscillator 240 in the measurement mode is finished, the switches 46, 47, and 48 in the calibration mode are set to an on / off state determined according to the calibration signal CAL. In the normal mode, the first charge pump 213 may output a charge pump current I _CP having a corrected magnitude. According to an embodiment, the switches 46, 47, and 48 may be implemented such that their on / off state is fixed according to the calibration signal CAL once input, and is turned on whenever the calibration signal CAL is applied. The on / off state may be implemented to be updated.

Referring back to FIG. 2, the phase locked loop 200 includes two feedback dividers 215 and 225, and may occupy a large chip area because each division ratio N ₁ and N ₂ is also large. . The chip area can be reduced by using a method of sharing a high rate feedback divider as follows.

5 is a block diagram illustrating a configuration of sharing a high rate feedback divider in a phase locked loop according to an embodiment of the present invention.

Referring to FIG. 5, there is shown one high rate feedback divider 51, a first low rate feedback divider 52 for the main loop, and a second low rate feedback divider 53 for the measurement loop. 2, the oscillation signal VCO_OUT divided through the high rate feedback divider 51 and the first low rate feedback divider 52 is divided through the first feedback divider 215 of FIG. 2. Is equal to the oscillated signal VCO_OUT (ie, N _H ㅧ N _L1 = N ₁ ). Similarly, the oscillation signal VCO_OUT divided through the high rate feedback divider 51 and the second low rate feedback divider 53 is divided by the second feedback divider 225 of FIG. 2. VCO_OUT) (ie, N _H ㅧ N _L2 = N ₂ ).

The measurement loop 220 and the calibration unit 230 may be implemented without taking up a larger area than the main loop 210, and do not operate in a normal mode, and thus there is no additional power consumption.

6 is a flowchart illustrating a method of measuring oscillator gain in a frequency synthesizer and calibrating a characteristic of the frequency synthesizer according to an embodiment of the present invention. Referring to FIG. 6, the frequency synthesizer has three operation modes, a measurement mode, a calibration mode, and a normal mode, and the frequency synthesizer will be described using a circuit having the structure of FIG. 2 as an example.

While in the measurement mode, the gain curve of the oscillator is measured in the measurement loop (S61, S62). In this case, the gain is a ratio of the frequency of the control signal input to the oscillator and the oscillation signal output from the oscillator according to the control signal. The amplitude of the control signal is measured while changing the frequency of the oscillation signal (S61). The gain characteristic of the oscillator is obtained from the magnitude of the measured control signal (S62).

In the calibration mode, a calibration signal is generated according to how the measured value of the gain curve differs from the designed value in the calibration unit (S63), and pull-down and pull-up current sources in the first charge pump of the main loop are generated according to the calibration signal. It is corrected (S64). After the calibration, the measurement loop and the calibration unit no longer operate (S65). In the normal mode, an oscillation signal is generated in the main loop using the calibrated first charge pump (S66).

Although the above-described integer ratio frequency synthesizer has been described as an example, the present invention can be applied to a fractional-N frequency synthesizer. The present invention can be applied to a circuit having a structure in which a voltage controlled oscillator or a current controlled oscillator generates an oscillation signal according to a control signal controlled by a charge pump.

The frequency synthesizer according to an embodiment of the present invention may measure the gain of an oscillator included therein. The measurement loop and the calibration unit included in the frequency synthesizer may be implemented without taking up more area than the main loop, and since the measurement loop and the calibration unit do not operate in the normal mode, no additional power is consumed.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (11)

An oscillator for generating an oscillation signal having a frequency corresponding to the magnitude of the control signal; A main loop operated in a normal mode, receiving the oscillation signal and comparing the oscillation signal with a first reference signal, and generating and providing the control signal to the oscillator according to the comparison result; And A measurement loop which is operated in a measurement mode, receives a feedback signal of the oscillation signal and sequentially changes the frequency of the oscillation signal by a predetermined magnitude, and provides the oscillator with the control signal which is changed according to a change result of the frequency of the oscillation signal; Frequency synthesizer comprising a. The method of claim 1, wherein the main loop A charge pump for correcting the magnitude of the charge pump current in the calibration mode according to the calibration signal, and generating the calibrated charge pump current according to the comparison result in the normal mode, The frequency synthesizer And a calibrating unit configured to measure the magnitude of the control signal to be changed in the measurement mode, and generate and provide the calibration signal to the main loop based on the gain of the oscillator calculated from the measurement result in the calibration mode. A frequency synthesizer characterized by the above. The method of claim 2, wherein the correction unit An analog-to-digital converter that measures the magnitude of the changed control signal and converts the magnitude into a digital measurement value; And a digital processor for generating the calibration signal into an m-bit digital code based on the digital measurement; The charge pump is M current units each outputting a current represented by a power of 2 with respect to the reference current; And m switches each capable of activating the m current units according to the calibration signal, and summing the currents from the activated current units to output the charge pump current. 2. The apparatus of claim 1, wherein the main loop is configured to divide the oscillation signal with a first division ratio to compare with the first reference signal, And the measurement loop is configured to divide the oscillation signal with a second division ratio and change the frequency of the oscillation signal by changing the second division ratio by one. The method of claim 4, wherein the main loop is configured to sequentially divide the oscillation signal into a high division ratio and a first low division ratio, and the measurement loop divides the oscillation signal divided into a high division ratio in the main loop at a second low division ratio. And a value obtained by multiplying the high division ratio by the first low division ratio is the same as the first division ratio, and a value obtained by multiplying the high division ratio by the second low division ratio is the same as the second division ratio. . In a frequency synthesizer comprising an oscillator, applying a control signal to the oscillator to generate an oscillator signal having a frequency that varies according to the magnitude of the control signal from the oscillator; Measuring the magnitude of the control signal while repeatedly changing the frequency of the oscillation signal by a predetermined magnitude; And And obtaining a gain of the oscillator from a ratio of the change amount of the frequency of the oscillation signal and the change amount of the magnitude of the control signal measured. The method of claim 6, wherein measuring the magnitude of the control signal Dividing the oscillation signal with a predetermined division ratio; And changing the frequency of the oscillation signal by changing the predetermined division ratio by one. Generating an oscillation signal having a frequency that varies according to the magnitude of the applied control signal; Measuring the magnitude of the control signal by changing the control signal while sequentially changing the frequency of the oscillation signal by a predetermined magnitude, and calibrating a frequency synthesizer based on the measurement result; And Generating the oscillation signal with the calibrated frequency synthesizer. The method of claim 8, The frequency synthesizer comprises a charge pump having a calibrated current source, Calibrating the frequency synthesizer Measuring the magnitude of the control signal while repeatedly changing the frequency of the oscillation signal by a predetermined magnitude; Obtaining a gain of the oscillator from the ratio of the change amount of the frequency of the oscillation signal and the change amount of the magnitude of the control signal measured; Generating a calibration signal by comparing the gain of the oscillator to an ideal gain; And And calibrating the current source based on the calibration signal such that the charge pump produces a calibrated current. 10. The method of claim 9, wherein the control signal is measured as a digital value and the calibration signal is an m-bit digital code. The method of claim 9, Measuring the magnitude of the control signal Dividing the oscillation signal with a predetermined division ratio; And changing the frequency of the oscillation signal by changing the predetermined division ratio by one.

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