KR20080015554A - Method of manufacturing a non-volatile memory device - Google Patents

Abstract

A method of manufacturing a non-volatile memory device is provided to easily control a threshold voltage of a transistor by forming recesses on a surface of a substrate between gate structures and then forming source/drain regions. Gate structures(120,122) comprising a tunnel oxide layer pattern(112), a floating gate(114), a dielectric layer pattern(116) and a control gate(118) is formed on a semiconductor substrate(100). Portions of the substrate adjacent to the gate structures are etched to form recesses having an inclined side. The surfaces of the recesses are implanted with impurity by using the gate structures as an ion implantation mask to form source/drain regions(128). An interlayer dielectric pattern(130) having contact holes exposing the source/drain regions is formed to bury the gate structures. Contacts(132) are formed to bury the contact holes.

Description

Method of manufacturing a non-volatile memory device

1 to 5 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention.

6 is a cross-sectional view illustrating a preliminary source / drain region of a nonvolatile memory device according to another exemplary embodiment of the present invention.

7 is a cross-sectional view illustrating a preliminary source / drain region of a nonvolatile memory device according to still another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100 semiconductor substrate 102 tunnel oxide film

104: first conductive film 106: dielectric film

108: second conductive film 112: tunnel oxide film pattern

114: floating gate 116: dielectric film pattern

118: control gate 120: first gate structure

122: second gate structure 124: gate structures

126: recess 128: source / drain region

130: interlayer insulating film pattern 132: contact

I-I ': first region II-II': second region

The present invention relates to a method of manufacturing a nonvolatile memory device, and more particularly, to a method of manufacturing a nonvolatile memory device suitable for reducing the size of a cell.

Semiconductor memory devices, such as dynamic random access memory (DRAM) and static random access memory (SRAM), are volatile and fast data input / output that loses data over time, and data is input once. This can be largely classified as a non-volatile (read-only memory) product that is non-volatile to maintain its state but has a slow input / output of data.

In the case of the nonvolatile memory device, there is an increasing demand for an electrically erasable and programmable ROM (EEPROM) or flash memory capable of electrically inputting / outputting data. The flash memory device has a structure for electrically controlling input and output of data by using F-N tunneling or channel hot electron injection. The flash memory device may be classified into a NOR type and a NAND type.

Since the NOR flash memory device forms contact holes on the source region and the drain region of each cell transistor, it is not easy to integrate. In contrast, the NAND type flash memory device has a string structure in which a plurality of cell transistors are connected in series to facilitate integration.

The memory cells of the NAND flash memory device are divided into a stack type and a split type according to the shape of the gate electrode. A general stacked type flash memory cell includes a tunnel oxide film of a thin film formed on a semiconductor substrate. And a floating gate and a control gate stacked on the insulating layer, and a source / drain region formed on the exposed substrate.

As a method of manufacturing the flash memory, for example, according to US Patent No. 6,465,293, a tunnel oxide film and a first polysilicon layer are sequentially formed on a semiconductor substrate on which a device isolation film is formed. The floating layer is formed by planarizing the first polysilicon layer until the tunnel oxide layer is exposed. The tunnel oxide layer and the oxide layer pattern of the exposed portion are etched by a predetermined thickness to form a dielectric layer on the entire upper surface. A second polysilicon layer, a tungsten silicide layer, and a hard mask are sequentially formed on the dielectric layer, and then patterned to form a control gate. Impurity ions are implanted into the exposed substrates on both sides of the floating gate to form a junction region.

The state of the flash memory device is determined by a threshold voltage. That is, by changing the amount of charge stored in the floating gate of the cell transistor to change the threshold voltage of the cell transistor to determine the erase or program state. In this case, the erase state is a state in which the threshold voltage is low and is displayed as "0", and the program state is in a state where the threshold voltage is high and is represented by "1".

In recent years, the cell size of the flash memory has become smaller, and as a result, the gate length is shortened, and the short channel effect is increased. In addition, as the threshold voltage (Vth) and the sub-threshold slope are increased, the concentration of impurity ions injected into the channel region is further increased to maintain the threshold voltage.

However, according to US Pat. No. 6,465,293, when impurities are injected at a high concentration into the channel region formed between the tunnel oxide film and the interface of the substrate, the impurities can also spread to the junction region, thereby increasing capacitance in the channel region. You can. That is, when boron, fluorine boron (BF ₂ ), or the like is used as the impurity ions to be injected into the channel region, boron, etc., can be widely spread to increase the concentration in the junction region, thereby making it difficult to control the threshold voltage of the transistor. Therefore, malfunction of the flash memory device occurs frequently.

Accordingly, the threshold voltage of the transistor may be adjusted by performing selective ion implantation on a portion where the transistor is formed. However, the ion implantation process is becoming more difficult as it is highly integrated.

Therefore, there is a need for a method of facilitating adjustment of the threshold voltage of a transistor to improve electrical reliability of a nonvolatile memory device.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a nonvolatile memory device in which a high concentration of impurities do not meet each other in a junction region between a source / drain region and a channel region to facilitate threshold voltage regulation of a transistor. can do.

A method of manufacturing a nonvolatile memory device according to a preferred embodiment of the present invention for achieving the above object to form a gate structure including a tunnel oxide film pattern, a floating gate, a dielectric film pattern and a control gate on a semiconductor substrate. Surface portions of the substrate adjacent to the gate structures are etched to form recesses having sloped sides. The gate structures are used as ion implantation masks, and impurities are implanted into surface portions of the recesses to form source / drain regions. An interlayer insulating layer pattern having contact holes exposing the source / drain regions and filling the gate structures is formed. Forming contacts to bury the contact holes. As a result, a nonvolatile memory device having a source / drain region including recesses is manufactured.

In this case, the gate structures include first gate structures having a first width and second gate structures having a second width wider than the first width formed at a portion around the first gate structures.

As an example, the recesses may be formed in substrate surface portions between the first gate structures and between the first gate structures and the second gate structures.

As another example, the recesses may be formed in substrate surface portions between the first gate structures.

Accordingly, the present invention may form a transistor having a source / drain region in which recesses are formed, so that impurities of high concentration may not meet in the junction region, and the threshold voltage of the transistor may be easily adjusted. Therefore, it is possible to implement a nonvolatile memory device having an improved electrical reliability, particularly a NAND type flash memory device.

Hereinafter, a method of manufacturing a nonvolatile memory device of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments and may be implemented in other forms. The embodiments introduced herein are provided to make the disclosure more complete and to fully convey the spirit and features of the invention to those skilled in the art. In the drawings, the thickness of each device or film (layer) and regions has been exaggerated for clarity of the invention, and each device may have a variety of additional devices not described herein. When (layer) is mentioned as being located on another film (layer) or substrate, an additional film (layer) may be formed directly on or between the other film (layer) or substrate.

1 to 5 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention. 6 is a cross-sectional view illustrating a preliminary source / drain region of a nonvolatile memory device according to another exemplary embodiment of the present invention. 7 is a cross-sectional view illustrating a preliminary source / drain region of a nonvolatile memory device according to still another embodiment of the present invention.

Referring to FIG. 1, a semiconductor substrate 100 having an isolation region (not shown) such as a trench isolation layer is provided. In this case, the semiconductor substrate 100 may include a first region I-I '(FIG. 2) in which a plurality of cell transistors connected in series with a subsequent bit line will be formed, and a string select transistor connected left and right with the cell transistor. And a substrate 100 divided into a second region II-II '(FIG. 2) where a ground select transistor is to be formed. In this case, first gate structures having a first width may be formed in the first region I-I ', and have a second width wider than the first width in the second region II-II'. Second gate structures may be formed.

Subsequently, a tunnel oxide film 102 is formed on the semiconductor substrate 100. The tunnel oxide film 102 is formed by performing a thermal oxidation method or a radical oxidation method as a silicon oxide film. At this time, the tunnel oxide film 102 is preferably formed to have a thickness of about 10 to 500Å.

Subsequently, a first conductive layer 104 to be used as a floating gate is formed on the tunnel oxide layer 102. The first conductive layer 104 is mainly formed using a material such as polysilicon, titanium nitride, tantalum nitride, tungsten nitride, rudenium, or the like. It is preferable to use the above materials alone, but in some cases, two or more of them may be used in combination.

In particular, when the first conductive film 104 is formed of polysilicon, the first conductive film 104 is mainly formed by performing a first process of stacking and a second process of doping impurities. Here, the first step is preferably formed by thermal decomposition of a silane (SiH ₄ ) gas using a furnace. In the second process, the dopants may be doped by diffusion and ion implantation after the first process, or the dopants may be doped in-situ during the first process. In addition, when the first conductive film 104 is formed of a metal nitride film such as titanium nitride, tantalum nitride, or tungsten nitride, it is preferable to perform a chemical vapor deposition process.

Subsequently, a dielectric film 106 is formed on the surface of the first conductive film 104. Here, the dielectric film 106 is to form a dielectric film pattern of the flash memory device and should have a high capacitance. Accordingly, the dielectric layer 106 may be formed by containing hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), or zirconium-hafnium-oxide, which are high-k dielectrics. This is because the coupling ratio of the flash memory device is improved when the dielectric film has a high capacitance.

Subsequently, a second conductive layer 108 to be used as a control gate is formed on the surface of the dielectric layer 106. Like the first conductive film 104, the second conductive film 108 is formed of a material such as polysilicon, titanium nitride, tantalum nitride, tungsten nitride, rudenium, tungsten, or the like. It is preferable to use the above materials alone, but in some cases, two or more of them may be used in combination.

Referring to FIG. 2, the second conductive film 108, the dielectric film 106, the first conductive film 104, and the tunnel oxide film 102 are sequentially patterned. Accordingly, the second conductive layer 108 is formed of the control gate 118, the dielectric layer 106 is formed of the dielectric layer pattern 116, and the first conductive layer 104 is the floating gate 114. The tunnel oxide layer 202 is formed of a tunnel oxide layer pattern 212.

Accordingly, gate structures 124 of the nonvolatile memory device including the tunnel oxide layer pattern 112, the floating gate 114, the dielectric layer pattern 116, and the control gate 118 are formed on the semiconductor substrate 100. In particular, first gate structures 120 having a first width 119 are formed in the first region I-I 'of the semiconductor substrate 100, and in the second region II-II'. Second gate structures 122 having a second width 121 wider than the first width 119 are formed.

Subsequently, an outside of the semiconductor substrate 100 and the gate structures 124 exposed by reoxidizing the semiconductor substrate 100 on which the first gate structures 120 and the second gate structures 122 are formed. An oxide film (not shown) may be formed on the surface. In this case, the reoxidation process may be performed to cure damage caused by high energy ion bombardment during an etching process performed to form the gate structures 124.

Referring to FIG. 3, surface portions of the semiconductor substrate 100 adjacent to the gate structures 124 are etched to form recesses 126 having sloped sides. At this time, the reason for forming the recesses 126 may be due to dispersing impurities in a lower surface of the semiconductor substrate 100 below the bottom surface of the tunnel oxide layer pattern 112 when ion implantation forms a source / drain region. This is to prevent impurities implanted into the channel region from being diffused in a high concentration into the source / drain regions. Accordingly, capacitance in the channel region of the substrate 100 may be reduced, and boosting characteristics may be improved, and thus the threshold voltage Vth of the transistor may be easily adjusted.

As an example, the recesses 126 having the inclined side surfaces may be inclined with respect to the upper surface of the semiconductor substrate 100 between the first gate structures 120 and the second gate structures 122. The substrate 100 may be formed by dry etching.

As another example, as shown in FIG. 6, the recesses 127 may have a substrate between the first gate structures 120 and between the first gate structures 120 and the second gate structures 122. (100) may be formed on the surface portions. That is, the recesses 127 are disposed between the first region I-I 'and the first region I-I' of the semiconductor substrate 100 and the second region II-II 'of the peripheral portion. The exposed substrate 100 is formed by etching. Specifically, in the NAND flash memory device, a substrate 100 exposed between the first gate structures 120 forming the cell transistor, and a string select transistor and a ground select transistor connected to both sides of the cell transistor. The substrate 100 exposed between the two gate structures 122 may be etched.

As another example, as shown in FIG. 7, the recesses 129 may be formed in surface portions of the substrate 100 between the first gate structures 120. That is, the recesses 129 may etch the substrate 100 exposed between the first gate structures 120 that are the first region I-I 'forming the cell transistor in the NAND flash memory device. Can be formed. In this case, etching is not performed in the second region (II-II ') where the source line or the bit line meets at the peripheral portion, the ground select transistor and the word line meet each other, or the string selection transistor and the word line meet each other. The same select transistor characteristics as in the prior art can be maintained.

Referring to FIG. 4, the gate structures 124 are used as an ion implantation mask, and impurities are implanted into surface portions of the recesses 126. In this case, the impurity implantation may be performed perpendicularly to the substrate 100 that meets the inclined side surfaces and bottom surfaces of the recesses 126 having the inclined surface. Subsequently, a heat treatment process is performed to activate the implanted impurities. As a result, the implanted impurities are further diffused under the recesses 126 to form source / drain regions 128 on the substrate 100.

Referring to FIG. 5, an interlayer insulating layer pattern having contact holes (not shown) exposing source / drain regions 128 between the gate structures 124 and filling the gate structures 124. 130). Subsequently, the contact holes are buried to form the contacts 132.

Specifically, first, an interlayer insulating layer is formed to bury the gate structures 124. The interlayer insulating layer may be made of silicon oxide. For example, the interlayer insulating layer may be made of high density plasma (HDP) oxide or BPSG (Boro Phosphor Silicate Glass). Subsequently, a predetermined portion of the interlayer insulating layer is etched to form contact holes exposing source / drain regions 128 adjacent to the gate structures 124. In addition, the interlayer insulating film is converted into the interlayer insulating film pattern 130. In this case, the interlayer insulating layer pattern 130 has a flat upper surface.

Subsequently, the contact holes are buried in a conductive material to form contacts 132 in electrical contact with the source / drain regions 128. The contacts 132 are then applied to the bit line or source line.

According to the method, it is possible to implant recesses between gate structures on the semiconductor substrate to implant impurity ions into a lower surface than the tunnel oxide layer pattern, so that the junction between the substrate portion where the channel is formed and the source / drain region is formed. High concentrations of impurities may not meet in the region. As a result, the channel capacitance in the channel region is reduced and the boosting characteristic is improved, so that the threshold voltage Vth of the transistor can be easily adjusted.

In addition, in the present embodiment, a description is given of a floating gate type flash memory device, but a charge trap type flash memory device using a charge trap layer in place of the floating gate also has the inclined side surface. A source / drain region including the sets may be formed to easily adjust the threshold voltage of the transistor.

As described above, according to the method of manufacturing the nonvolatile memory device according to the preferred embodiment of the present invention, a transistor having source / drain regions in which recesses having sloped sides are formed may be formed, thereby forming a substrate on which a channel is formed. Since high concentrations of impurities may not meet each other in the junction region between the portion and the source / drain region, the voltage in the channel region may be increased. As a result, the voltage difference between the control gate and the channel is reduced, so that the threshold voltage of the transistor can be easily adjusted, so that only the string associated with the program to be executed can be operated. Thus, improved electrical reliability can be obtained, and in particular, the implementation of the NAND type flash memory device can be improved.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (4)

Forming gate structures including a tunnel oxide pattern, a floating gate, a dielectric layer pattern, and a control gate on the semiconductor substrate; Etching surface portions of the substrate adjacent the gate structures to form recesses having sloped sides; Forming source / drain regions by using the gate structures as an ion implantation mask and implanting impurities into the surface portions of the recesses; Forming an interlayer insulating film pattern having contact holes exposing the source / drain regions and filling the gate structures; And And forming contacts to bury the contact holes. The gate structure of claim 1, wherein the gate structures include first gate structures having a first width and second gate structures having a second width wider than the first width formed at a portion around the first gate structures. A method of manufacturing a nonvolatile memory device, characterized in that. 3. The method of claim 2, wherein the recesses are formed in substrate surface portions between the first gate structures and between the first gate structures and the second gate structures. 4. . 3. The method of claim 2, wherein the recesses are formed in substrate surface portions between the first gate structures.

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