KR20080010946A - Display device and control method thereof - Google Patents

Abstract

A display device and a control method thereof are provided to eliminate horizontal line patterns by outputting a load signal and an inversed control signal to a data driver. Plural pixels(130) are defined by data lines(120) and gate lines(110). A data driver(220) applies a data voltage to the pixels during a data interval, and applies a blank voltage of desired level to the pixels during a blank period. A blank load/inversed control signal generator(230) applies a load signal and an inversed control signal to the data driver during the blank interval. The pixels, which are contiguously arranged in a direction of data line, are applied with a voltage of different polarity, and the pixels arranged on one gate line are applied with a voltage having the same polarity.

Description

DISPLAY DEVICE AND CONTROL METHOD THEREOF}

1 is a schematic diagram of a display device according to an embodiment of the present invention;

2 is a control block diagram of a blank load / inversion control signal generator according to an embodiment of the present invention;

3 is a signal waveform diagram of a display device according to an embodiment of the present invention.

4 is a control flowchart illustrating a control method of a display apparatus according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

100: liquid crystal panel 110: gate line

120: data line 130: pixel

210: gate driver 220: data driver

230: blank load / inversion control signal generator

231: blank section detection unit 233: load signal generation unit

235: inversion control signal generation unit 240: signal control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display apparatus and a control method thereof, and more particularly, to a display apparatus and a control method driven by a precharging method.

In general, a liquid crystal display applies an electric field to a liquid crystal material having an anisotropy dielectric constant injected between two substrates, and adjusts the intensity of the electric field to control the amount of light transmitted through the substrate to obtain a desired image signal. It is a display device. In such a liquid crystal display device, a TFT-LCD using a thin film transistor for switching is mainly used.

Since the charge time of the pixel is drastically reduced as the resolution of the liquid crystal display device increases, a precharge method is used to compensate for the reduced charge time. The precharging method is a method of increasing the amount of data charging of a pixel by charging the pixel in advance with data of a neighboring pixel having the same polarity when driving a polarity inversion. On the other hand, the conventional vertical sync start signal is output only once in one frame, but the general precharging method adds a precharge vertical sync start signal to charge in advance to a predetermined voltage having the same polarity before charging the n-th pixel to the data voltage. To compensate for the charging time. In more detail, a method of generating a precharging vertical synchronization start signal at a designated time point using a counter during a frame blank period is used.

In the precharging method, when a blank voltage of a predetermined level is applied instead of precharging the n th data voltage to charge the n th pixel, the load signal and the inversion control signal generated based on the gate clock signal No output This maintains a continuous charging state of the same polarity in the pixel, and thus, when a data voltage is applied, a problem arises in that a horizontal line pattern is formed on the liquid crystal panel due to the difference in charge amount between polarities during the polarity inversion driving.

Accordingly, an object of the present invention is to provide a display apparatus and a control method thereof in which image quality is improved by preventing horizontal stripes.

According to the present invention, there is provided a display apparatus having a data section and a blank section for one frame, comprising: a plurality of pixels defined by data lines and gate lines;

A data driver for applying a data voltage to the pixel during the data period and a blank voltage of a predetermined level to the pixel during the blank period; And a blank load / inversion control signal generator for applying a load signal and an inversion control signal to the data driver during the blank period.

In the display device according to the present embodiment, voltages having different polarities are applied to the pixels arranged adjacent to each other in the data line direction, and voltages having the same polarity are applied to the pixels arranged at one gate line. It is driven by line inversion.

A gate driver including a first gate line and a second gate line, the gate driver applying a gate pulse to the first gate line and the second gate line; A first for driving the second gate line before the first gate line to which a voltage having the same polarity as that applied to the pixel arranged in the first gate line and adjacent to the first gate line currently being driven is applied; And a signal controller for outputting a vertical synchronous start signal and a second vertical synchronous start signal for driving the first gate line to the gate driver, wherein the signal controller includes the first vertical line during the blank period for precharging. It is preferable to output the synchronization start signal to the gate driver.

That is, when the first gate line is the N-th gate line, the second gate line may be the N-2th gate line.

The signal controller may output a gate clock signal controlling the output timing of a gate pulse to the gate driver, and two gate clock signals may be output to the gate driver during the blank period.

The blank load / inversion control signal generation unit includes a blank period detection unit detecting a start of the blank period, a load generation signal based on a blank start signal output from the blank period detection unit, and a count input from the outside. It is preferable to include a signal generator and an inversion control signal generator for generating an inversion control signal based on the blank start signal and the count.

The blank period detection unit outputs the blank start signal indicating the generation of the load signal and the inversion control signal to the load signal generation unit and the inversion control signal generation unit when the row period of the gate clock signal has elapsed. It is preferable.

On the other hand, the object of the display apparatus having a plurality of pixels consisting of a gate line and a data line according to the present invention, and having a data section to which a data voltage is applied to the pixel and a blank section to which the data voltage is not applied during one frame A control method, comprising: generating a blank voltage of a predetermined level; Outputting a first vertical synchronization start signal and a gate clock signal during the blank period; Transferring the blank voltage to the pixel while applying a gate pulse to the pixel according to the gate clock signal; Counting a row period of the gate clock signal; If the count value is out of a predetermined range, it may also be achieved by a control method of the display apparatus including outputting a load signal and an inversion control signal.

The outputting of the load signal and the inversion control signal may further include outputting a blank start signal when a count value is out of a predetermined range, wherein the load signal and the inversion control signal are based on an output of the blank start signal. It is preferably generated by.

Two gate clock signals may be output during the blank period. The number of gate lines activated in the blank period is not limited to two, and may be set differently according to the environment of the display apparatus and the user's preference.

The method may further include outputting a second vertical synchronization start signal and a gate clock signal during the data period in order to normally apply a data voltage.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

In various embodiments, like reference numerals refer to like elements, and like reference numerals refer to like elements in the first embodiment and may be omitted in other embodiments.

1 is a schematic diagram of a display apparatus according to an embodiment of the present invention. The display device according to the present invention is described as an example of a liquid crystal display device, and a display device capable of being driven by a precharging method is not limited to the liquid crystal display device.

As illustrated, the liquid crystal display according to the present exemplary embodiment includes a liquid crystal panel 100 in which an image is displayed, a gate line 110 formed on the liquid crystal panel 100, a data line 120, and a gate line 110. And a gate driver 210 connected to the data driver 220, a data driver 220 connected to the data line 120, a blank load / inversion control signal generator 230, and a signal controller 240 controlling the gate driver 210.

The liquid crystal panel 100 may include the data lines D ₁ to D _n 120 and the gate line 110 and the data line 120 that cross and insulate the gate lines G ₁ to G _n 110 and the gate lines 110. A plurality of pixels 130 defined by and arranged in a matrix form are formed. A thin film transistor (not shown) is formed at the intersection of the gate line 110 and the data line 120, and the thin film transistor applies various voltages to the pixel 130. The gate line 110 applies a gate pulse provided from the gate driver 210 to the pixel 130, and the data line 120 transmits a data voltage output from the data driver 120 to the pixel 130.

The signal controller 240 may control an RGB data signal DATA corresponding to the RGB gray level signal and an input control signal for controlling the display thereof, for example, a main clock from an external graphic controller. , CLK), and a data enable signal (DE) are provided. The signal controller 240 generates a gate control signal, a data control signal, and a voltage selection control signal VSC based on the control input signal, and generates an RGB data signal DATA from the outside of the liquid crystal panel 100. After appropriately converting according to the operating conditions, the gate control signal is sent to the gate driver 210 and the data control signal and the processed data signal DATA are sent to the data driver 220.

The signal controller 240 receives the RGB data signal DATA and the data enable signal DE to select a next gate line 110, that is, a gate clock signal CPV for controlling an output timing of the gate pulse. ) And the first gate line 110, the vertical synchronization start signal (STV) indicating the start of one frame and the gate on enable signal defining the width of the gate on pulse. , OE, etc. are output to the gate driver 210.

In particular, the vertical synchronous start signal output from the signal controller 240 according to the present invention is substantially equal to the current gate line 110, for example, the N-th gate line, together with the vertical synchronous start signal for driving the gate line 110. The vertical synchronization start signal for the precharging voltage applied to the gate line 110, for example, the N-second gate line 110, which is the same as the polarity of the 110 and is arranged adjacent to the N-th gate line 110, is further included. Include. Here, the polarity of the gate line 110 refers to the polarity of the data voltage applied to the pixel 130 arranged on one gate line 110. In the display device according to the present exemplary embodiment, all polarities of the data voltages applied to one gate line 110 are the same, and each of the gate lines 110 is driven by line inversion in which the polarities of the data voltages are inverted. Hereinafter, the first vertical synchronizer is arranged to be closest to the currently driven gate line 110 and to perform a vertical sync start signal for the charge of the previous gate line 110 having the same polarity as the current gate line 110 being driven. As a start signal, a vertical synchronous start signal for driving the current gate line 110 is referred to as a second vertical synchronous start signal. The signal controller 240 according to the present embodiment outputs a first vertical synchronization start signal in a blank section for precharging, and two gate clocks for activating the first gate line 110 and the second gate line 110. Output the signal CPV.

In addition, the data control signal output to the data driver 220 includes a horizontal synchronous signal (STH) for transmitting RGB data and a load (LOAD or TP) that starts output of the data driver 220 after completion of the RGB data transmission. ) Signal, an inversion control signal REV for inverting the polarity of the data voltage, a data clock signal HCLK, and the like.

In addition, the signal controller 240 outputs the clock signal CLK and the gate clock signal CPV informing the timing of the signal output to the blank load / inversion control signal generator 230.

The gate driver 210 may also be referred to as a scan driver. The gate driver 210 may be connected to the gate line 110 and may include a gate including a gate on voltage Von and a gate off voltage Voff from a gate voltage generator (not shown). The pulse is applied to the gate line 110.

The data driver 220 may also be referred to as a source driver. The data driver 220 applies a data voltage to the pixel 130 during the data period, and applies a blank voltage of a predetermined level to the pixel 130 during the blank period between the data periods. The blank period generally refers to a period between frames in which an image is displayed and is recognized as a period for preparing a data voltage of a next frame. The blank period according to the present exemplary embodiment is defined as a period in which the blank voltage is applied to the liquid crystal panel 100 instead of the data voltage. As described above, two gate clock signals CPV are applied to the blank period so that a blank of a predetermined level is provided. Voltage is applied to the first and second gate lines 110.

The data driver 220 receiving the gray voltage from the gray voltage generator (not shown) selects the gray voltage under the control of the signal controller 240 to apply the data voltage to the data line 120 and applies the data voltage. In the blank period, the predetermined number of pixel columns is precharged by applying a predetermined blank voltage to the data line 120.

The blank load / inversion control signal generator 230 generates a load signal TP and an inversion control signal REV in the blank section based on the control signal received from the signal controller 240, and outputs the load signal TP and the inversion control signal REV to the data driver 220. do. 2 is a schematic diagram of a blank load / inversion control signal generation unit according to an embodiment, and as shown, the blank load / inversion control signal generation unit 230 includes a blank section detection unit 231 and a load signal generation unit 233. ) And an inversion control signal generator 235.

The blank period detection unit 231 transmits the blank start signal based on the clock signal CLK and the gate clock signal CPV received from the signal controller 240 to the load signal generator 233 and the inversion control signal generator 235. ) As described above, the two gate lines 110 are turned on during the blank period, and the gate clock signal CPV is generated twice. In this case, the two gate clock signals may be output continuously or at predetermined intervals. The blank section detecting unit 231 recognizes the blank section when the row section of the gate clock signal has elapsed, that is, when the row section of the gate clock signal becomes more than a predetermined count.

In the related art, when precharging using a blank voltage of a predetermined level instead of a data voltage during a blank period, an inversion control signal REV generated according to the load signal TP and the load signal TP is not generated in the blank period. Did. Therefore, the charge remaining in the pixel 130 due to the blank voltage applied to the blank period affects the subsequent data voltage. That is, as the deviation between the positive data voltage and the negative data voltage becomes greater, the distinction of the data voltage according to the polarity between the lines during the line inversion driving becomes clear, so that a horizontal line is formed in the liquid crystal panel 100.

According to an embodiment of the present invention, the load signal TP and the inversion control signal REV are also applied to a blank section in which a blank voltage of a predetermined level is applied to remove the horizontal lines, thereby removing charges remaining in the pixel 130 due to the blank voltage. Can be. That is, since the blank voltage is recognized as being applied as a waveform having a polarity rather than a predetermined DC level, the influence of the charge can be removed when the data voltage is applied while precharging the pixel 130.

When the blank start signal is output from the blank section detection unit 231, the load signal generator 233 and the inversion control signal generator 235 output the load signal TP and the inversion control signal REV at regular intervals. . The interval or number of outputs for outputting the load signal TP and the inversion control signal REV may be arbitrarily set. The brightness and the duration of the blank section that occur in the horizontal line generated in the liquid crystal panel 100 will be set in consideration.

3 is a signal waveform diagram of a display device according to an embodiment of the present invention.

(1) shows DE, and a valid data voltage is stored in the data driver 220 and waits for output to the data line 120. The data voltage to be applied to the first gate line 110 is referred to as d1, and the data voltage to be applied to the second gate line 110 is referred to as d2. A blank voltage of a predetermined level is formed in the blank section I before d1 is formed. The blank voltage and the data voltage are output from the data driver 220 to the data line 120 by the load signal TP shown in (8). During the blank period I, the first vertical synchronization start signal ① is output (2), and the first gate clock signal a for turning on the first gate line G1 is output as shown in (3). When the first gate line G1 is turned on as in (4), a blank voltage is applied to the first gate line 110 by the first load signal TP1 of (8).

After the blank voltage is applied to the first gate line G1 and the next gate clock signal CPV is not output even after a predetermined time has elapsed, the second load signal TP2 and ( The inversion control signal REV shown in 9) is output.

(7) shows a conventional load signal TP, and the blank applied to the first load signal TP1 and the second gate line G2 for outputting the blank voltage applied to the first gate line G1. No load signal TP is generated between the third load signal TP3 for outputting the voltage and no inversion control signal REV is generated.

Unlike the related art, the second load signal TP2 is formed between the first load signal TP1 and the third load signal TP3 to prevent excessive accumulation of the blank voltage.

When the second gate line G2 is turned on by the second gate clock signal b, a blank voltage is applied to the second gate line G2 by the third load signal TP3.

When the blank period I ends and the data period II starts, the first gate line G1 is turned on again by the second vertical synchronization start signal ② and the third gate clock signal c. The third gate line G3 is turned on by the 1 vertical synchronous start signal ①. At this time, the negative polarity d1 is applied to the first and third gate lines G1 and G3 by the fourth load signal TP4 and the inversion control signal REV. D1 applied to the first gate line G1 is a data voltage for substantially driving, and d1 applied to the third gate line G3 is used as a voltage for precharging.

In summary, the first vertical synchronizing start signal ① generated before the second vertical synchronizing start signal ② for driving the first gate line G1 that is currently driven is most applied to the gate line G1 that is currently driven. The previous gate line, i.e., the third gate line G3, adjacent to each other and having the same polarity is precharged. The above process is repeated while being sequentially turned on two gate lines 110.

The above-described output waveform is only an example for explaining the present invention, and the number of gate clock signals CVP output in the blank period I is not limited to two. As long as the polarity is the same, the second or third gate line 110 may be used instead of the previous first gate line 110.

4 is a control flowchart illustrating a control method of a display apparatus according to an exemplary embodiment of the present invention.

First, in the blank period I, the first vertical synchronization start signal ① and the gate clock signal CPV are output (S10).

When a gate pulse is applied to the first gate line G1 by the gate clock signal CPV, a blank voltage of a predetermined level is applied to the pixel 130 (S20).

The blank period detection unit 231 counts a low period of the gate clock signal CPV (S30), and determines whether the count value deviates from a predetermined reference value (S40).

As a result of the determination, when the counter value exceeds the reference value, it is determined that the low section of the gate clock signal CPV has continued for a predetermined time or more. Since the low time interval of the gate clock signal CPV has elapsed since the gate clock signal no longer occurs, the blank period detection unit 231 inverts the blank start signal from the load signal generator 233. The control signal generator 235 outputs the control signal to the control signal generator 235 (S50).

On the other hand, when the counter value is less than the reference value, the blank section detection unit 231 does not output any signal.

The blank start signal is output, and the load signal generator 233 and the inversion control signal generator 235 generate a load signal TP and an inversion control signal REV, respectively, and output the load signal TP and the inversion control signal REV to the data driver 220 (S60). ).

When the blank voltage of a predetermined level becomes a waveform having the polarity by the load signal TP and the inversion control signal REV, residual charges accumulated in the pixel 130 are exhausted to remove the horizontal stripes.

When the blank period I ends and the data period II starts, the gate pulse and the data voltage are applied to the pixel 130 according to the first vertical synchronization start signal ② for substantially driving the gate line 110. .

Although some embodiments of the invention have been shown and described, it will be apparent to those skilled in the art that modifications may be made to the embodiment without departing from the spirit or spirit of the invention. . It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.

As described above, according to the present invention, there is provided a display apparatus and a method of controlling the same, in which image quality is improved by preventing horizontal stripes.

Claims (10)

In a display device having a data section and a blank section for one frame, A plurality of pixels defined by data lines and gate lines; A data driver for applying a data voltage to the pixel during the data period and a blank voltage of a predetermined level to the pixel during the blank period; And a blank load / inversion control signal generator configured to apply a load signal and an inversion control signal to the data driver during the blank period. The method of claim 1, Voltages having different polarities are applied to the pixels arranged adjacent to each other in the data line direction. And a voltage of the same polarity is applied to the pixels arranged on one gate line. The method of claim 2, The gate line includes a first gate line and a second gate line. A gate driver for applying a gate pulse to the gate line; A first for driving the second gate line before the first gate line to which a voltage having the same polarity as that applied to the pixel arranged in the first gate line and adjacent to the first gate line currently being driven is applied; And a signal controller for outputting a vertical synchronous start signal and a second vertical synchronous start signal for driving the first gate line to the gate driver. And the signal controller outputs the first vertical synchronization start signal to the gate driver during the blank period. The method of claim 2, The signal controller outputs a gate clock signal for controlling the output timing of the gate pulse to the gate driver, And at least two gate clock signals are output to the gate driver during the blank period. The method of claim 4, wherein The blank load / inversion control signal generator, A blank section detecting unit detecting a start of the blank section; A load signal generator configured to generate a load signal based on a blank start signal output from the blank period detector and a count input from the outside; And an inversion control signal generation unit configured to generate an inversion control signal based on the blank start signal and the count. The method of claim 5, And the blank period detection unit outputs the blank start signal to the load signal generator and the inversion control signal generator when the row period of the gate clock signal passes a predetermined time. A control method of a display apparatus having a plurality of pixels comprising a gate line and a data line, and having a data section in which a data voltage is applied to the pixel and a blank section in which no data voltage is applied to the pixel for one frame. Generating a blank voltage of a predetermined level; Outputting a first vertical synchronization start signal and a gate clock signal during the blank period; Transferring the blank voltage to the pixel while applying a gate pulse to the pixel according to the gate clock signal; Counting a row period of the gate clock signal; And outputting a load signal and an inversion control signal when the count value exceeds a predetermined reference value. The method of claim 7, wherein The outputting of the load signal and the inversion control signal may further include outputting a blank start signal when a count value is out of a predetermined range. And the load signal and the inversion control signal are generated based on the output of the blank start signal. The method of claim 7, wherein And at least two gate clock signals are output during the blank period. The method of claim 9, And outputting a second vertical synchronization start signal and a gate clock signal during the data period.

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