KR20080008543A - Cmos image sensor and method for fabricating the same - Google Patents

Abstract

A CMOS image sensor and a method for manufacturing the same are provided to enhance the quality of the product by increasing the transmission efficiency of charges. A CMOS(Complementary Metal Oxide Semiconductor) image sensor includes an active region, a photo diode and a floating diffusion region(FD), a gate(35) of a transfer transistor(30), and at least one dopant doping region(7). The active region is defined by an element isolation region(20). The photo diode and floating diffusion region are disposed in parallel with the active region. The gate of the transfer transistor is formed to cross over the active region between the photo diode and floating diffusion region. The density of dopant doping regions formed in the active region is varied based on distance with the floating diffusion area.

Description

CMOS image sensor and method for fabricating the same {CMOS image sensor and method for fabricating the same}

1 is a circuit diagram illustrating a unit pixel of a CMOS image sensor according to an exemplary embodiment.

2 is a layout diagram illustrating unit pixels of a CMOS image sensor according to an exemplary embodiment.

3 is a cross-sectional view taken along line III-III ′ of FIG. 2.

4 to 6 are cross-sectional views of the CMOS image sensor according to embodiments of the present invention.

7 to 10 are cross-sectional views of intermediate structures in which the manufacturing methods of CMOS image sensors according to the exemplary embodiments of the present invention are arranged step by step in the order of processing.

<Explanation of symbols for the main parts of the drawings>

10: photodiode 20: floating diffusion region

30: transfer transistor 40: reset transistor

50: drive transistor 60: select transistor

The present invention relates to an image sensor and a method of manufacturing the same, and more particularly to a CMOS image sensor and a method of manufacturing the same.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is classified into a charge coupled device (CCD) and a CMOS image sensor (CIS).

Among them, the CMOS image sensor forms transistors corresponding to the quantity of unit pixels on the semiconductor substrate by using CMOS technology using a control circuit, a signal processing circuit, and the like as peripheral circuits, thereby outputting each unit pixel by the transistors. It is a device that employs a switching method that detects sequentially. The CMOS image sensor uses CMOS manufacturing technology, resulting in a simple manufacturing process with low power consumption and few photo process steps. In addition, the CMOS image sensor can integrate a control circuit, a signal processing circuit, and an analog / digital conversion circuit onto the CMOS image sensor chip, thereby facilitating miniaturization of the product. Therefore, CMOS image sensors are now widely used in various application areas such as digital still cameras, digital video cameras, and the like. However, such CMOS image sensor has a problem of performance degradation caused by dark current, and it is required to develop CMOS image sensor which can reduce dark current and does not reduce charge transfer efficiency.

The technical problem to be achieved by the present invention is to provide a CMOS image sensor that can reduce the dark current, but does not lower the charge transfer efficiency.

Another technical problem to be achieved by the present invention is to provide a method for manufacturing a CMOS image sensor that can reduce the dark current but does not reduce the charge transfer efficiency.

According to an embodiment of the present disclosure, a CMOS image sensor may include an active region defined by an isolation region, a photodiode and a floating diffusion region disposed side by side in the active region, and the photodiode A gate of a transfer transistor across the active region between the floating diffusion regions, and at least one impurity doped region, which is located in the active region below the gate and whose concentration gradually changes from the photodiode side toward the floating diffusion region side. It includes a channel region having a.

The impurity doped region may have a doping profile in which the concentration gradually decreases from the photodiode side toward the floating diffusion region, and the impurity of the impurity doped region may be P-type.

The impurity doped region may further include a first conductivity type impurity doped region having a doping profile that gradually increases in concentration from the floating diffusion region side to the photodiode side and the first conductivity below the first conductivity type impurity doped region. And a second conductivity type impurity doped region having a doping profile complementary to the doping profile of the type impurity doped region, wherein the first conductivity type is P type and the second conductivity type is N type.

According to another aspect of the present invention, there is provided a method of manufacturing a CMOS image sensor, the method comprising: defining an active region by an isolation region, and ionizing a pattern of a photoresist film exposing a channel region of the active region Implanting at least one impurity at a predetermined oblique angle as an injection mask, and forming a gate of a transfer transistor across the channel region, a photodiode and a floating diffusion region disposed side by side in the active region.

The implanting of the impurity at a predetermined inclination angle may include injecting a first conductivity type impurity at a first inclination angle such that the channel region on the floating diffusion region side is shaded by the pattern of the photoresist layer. .

The implanting of the impurity at a predetermined inclination angle may further include injecting a second conductivity type impurity at a second inclination angle such that the channel region on the photodiode region side is shaded by the photoresist pattern. .

In this case, the first conductivity type impurities and the second conductivity type impurities may be type and P type impurities.

In addition, the second conductivity type impurity injected into the channel region may be implanted with a relatively higher energy than the first conductivity type impurity.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the embodiments make the disclosure of the present invention complete, and the scope of the invention to those skilled in the art. It is provided for the purpose of full disclosure, and the invention is only defined by the scope of the claims. Thus, in some embodiments, well known process steps, well known device structures and well known techniques are not described in detail in order to avoid obscuring the present invention. Further, the first conductivity type and the second conductivity type may be P type and N type, respectively, and the first conductivity type and the second conductivity type may be N type and P type, respectively. In addition, each embodiment described and illustrated herein also includes its complementary embodiment. Like reference numerals refer to like elements throughout.

CMOS image sensor according to embodiments of the present invention will be well understood by referring to FIGS.

1 is a circuit diagram illustrating a unit pixel of an image sensor according to an exemplary embodiment.

As illustrated in FIG. 1, the unit pixel 100 of the CMOS image sensor includes a photodiode PD and four transistors 30, 40, 50, and 60. The four transistors 30, 40, 50, and 60 are photodiodes PD that receive light to generate photocharges, and transfer transistors 30 that transport the photocharges collected from the photodiodes PD to the floating diffusion region FD. And a reset transistor 40 which sets the potential of the floating diffusion region FD to a desired value and discharges the charge to reset the floating diffusion region FD, and serves as a source follower buffer amplifier. It consists of a drive transistor 50 and a select transistor 60 to enable addressing in the switching role. In addition to the unit pixel 100, a load transistor 70 for reading an output signal is formed. Tx denotes a gate voltage of the transfer transistor 30, Rx denotes a gate voltage of the reset transistor 40, Dx denotes a gate voltage of the drive transistor 50, and Sx denotes a gate voltage of the select transistor 60. In addition, GND represents ground.

The operation of the unit pixel 100 of the CMOS image sensor configured as described above is performed as follows.

First, the reset transistor 40, the transfer transistor 30, and the select transistor 60 are turned on to reset the unit pixel 100. At this time, the photodiode PD begins to deplete, and charge accumulation occurs in the photodiode PD, and charge is accumulated in the floating diffusion region FD in proportion to the supply voltage V _DD .

Thereafter, the transfer transistor 30 is turned off and the select transistor 60 is turned on, and then the reset transistor 40 is turned off. In such an operation state, the first output voltage V ₁ is read from the unit pixel output terminal OUT, stored in a buffer (not shown), and then the transfer transistor 30 is turned on to change a photo according to the light intensity. The charges of the diode PD are moved to the floating diffusion region FD, and then the second output voltage V ₂ is read from the output terminal OUT again, and analog data of two voltage differences V ₁ -V ₂ is obtained. By changing the to digital data, the operation period for the unit pixel 100 is completed.

This CMOS image sensor will be described in more detail with reference to FIGS. 2 and 3. 2 is a layout diagram illustrating unit pixels of a CMOS image sensor according to an exemplary embodiment, and FIG. 3 is a cross-sectional view taken along line III-III ′ of FIG. 2.

As shown in FIG. 2, in the unit pixel 100 of the CMOS image sensor of the present invention, the active region 10 is a region defined by a thick solid line, and the device isolation region 20 is outside the active region. Area. The gate 35 of the transfer transistor 30, the gate 45 of the reset transistor 40, the gate 55 of the drive transistor 50 and the gate 65 of the select transistor 60 are each an active region 10. It is arranged in the form across the top of the.

As shown in FIG. 3, a first concentration of a low conductivity type, eg, a P ⁻ type epitaxial layer, is formed on a high concentration of a first conductivity type, eg, a P ⁺⁺ type semiconductor substrate (P ^++- sub, 1). (P ^-- epi, 2) is located. As the semiconductor substrate 1, for example, a single crystal silicon substrate can be used.

In the epitaxial layer 2 of the semiconductor substrate 1, an element isolation region 20 defining an active region (10 in FIG. 2) is positioned. Although the device isolation region 20 is illustrated as being formed by a shallow trench isolation (STI) process, the device isolation region 20 may be formed by a local oxidation of silicon (LOCOS) process.

The epi layer 2 of the active region (10 in FIG. 2) has a low concentration of a second conductivity type for the photodiode PD, for example an N ⁻ type diffusion region 3 and a medium concentration of the first conductivity type, for example. For example, the P ⁰ diffusion region 4 is located. At this time, the P ⁰ type diffusion region 4 is positioned on the N ⁻ type diffusion region 3.

In addition, the floating diffusion region FD is positioned in the epi layer 2 in parallel with the N ⁻ / P ⁰ diffusion regions 3 and 4 with the gate 35 of the transfer transistor 30 interposed therebetween. The floating diffusion region FD has a low concentration of a second conductivity type, for example, an N ⁻ type diffusion region 5a and a high concentration of a second conductivity type, for example, an N ⁺ type diffusion for forming a lightly doped drain (LDD). Region 5b.

On the other hand, a photodiode (PD) is N ^- it is possible to have type diffusion region (3) only ^- / P ⁰ type diffusion regions are shown as having 3, 4, a, in practice N.

A gate insulating film 15 and a gate 35 for the transfer transistor 30 are positioned in the epi layer 2 between the photodiode PD and the floating diffusion region FD, and spacers 36 are disposed on both sidewalls of the gate 35. Are located respectively. In addition, a channel region 6 is positioned in the epi layer 2 under the gate 35, which is in contact with the photodiode PD to provide a movement path of the photocharges. That is, when a voltage is applied to the transfer transistor 30, a channel region 6 in which photocharges can move is formed, and photoelectric charges are transferred to the floating diffusion region FD through the channel region 6 on the surface of the semiconductor substrate 1. Transported.

Near the surface of the semiconductor substrate 1 where the channel region 6 is located, there are factors that generate dark currents, including various defects and dangling bonds, thereby deteriorating the dark current characteristics of the CMOS image sensor. You can. Therefore, in order to prevent deterioration of the dark current characteristic, an impurity doped region 7 may be provided in the channel region 6. Impurities in the impurity doped region 7 may be, for example, P-type or N-type impurities, preferably P-type impurities.

In the impurity doped region 7, the impurity concentration may gradually change from the photodiode PD side to the floating diffusion region FD side. In more detail, the doping region 7 in the impurity doping region 7 in the channel region 6 has an inclined doping profile in which the dose amount of the impurity is larger on the photodiode PD side and the dosing amount of the impurity is smaller toward the floating diffusion region FD. profile). This can reduce the dark current as the concentration of the first conductivity type impurity, for example P-type impurity, of the impurity doped region 7 in the channel region 6 increases, but on the contrary, the charge accumulated in the photodiode PD region. Since the charge transfer efficiency of transferring the to the floating diffusion region FD may be reduced, the impurity doping region 7 has a doping profile as described above, thereby reducing charge transfer efficiency while reducing dark current generation. You can prevent it. Solid arrows in the figure indicate the direction of increasing the concentration of impurities in the impurity doped region 7.

Subsequently, a CMOS image sensor according to another embodiment of the present invention will be described with reference to FIG. 4. 4 is a cross-sectional view of a CMOS image sensor according to another exemplary embodiment of the present invention. As illustrated in FIG. 4, a CMOS image sensor according to another exemplary embodiment of the present invention may have a first conductivity type diffusion of a photodiode (PD). Except for region 4 ', it is substantially the same as CMOS image sensor according to one embodiment of the present invention. Therefore, a CMOS image sensor according to another embodiment of the present invention will be described based on differences from the CMOS image sensor according to an exemplary embodiment of the present invention.

The first conductivity type, for example P ⁰ diffusion region 4 ′, of intermediate concentration of the photodiode PD of the CMOS image sensor according to another embodiment of the present invention is spaced at random intervals from the transfer gate 35. It is formed in the epi layer 2 spaced apart. This is to prevent the junction from diffusing into the channel region 6 under the gate 35 when the P ⁰ type diffusion region is finally completed by a subsequent heat treatment process. When the junction of the P ⁰ type diffusion region enters below the gate 35, a barrier potential is formed below the edge of the gate 35 on the photodiode PD side to lower the charge transfer efficiency. In this case, the low light characteristic and the operating speed of the CMOS image sensor may be reduced. Accordingly, the first conductivity type diffusion region 4 ′ of the photodiode PD of the CMOS image sensor according to another embodiment of the present invention is spaced apart from the gate 35 to reduce the dark current but not reduce the charge transfer efficiency. Can be.

Subsequently, a CMOS image sensor according to another embodiment of the present invention will be described with reference to FIG. 5. 5 is a cross-sectional view of a CMOS image sensor according to another embodiment of the present invention. As shown in FIG. 5, the CMOS image sensor according to another exemplary embodiment of the present invention is the present invention except for the impurity doped region 7 ′ provided in the channel region 6 under the transfer gate 35. It is substantially the same as the CMOS image sensor according to an embodiment of. Therefore, the following description will focus on differences from the CMOS image sensor according to an exemplary embodiment.

The channel region 6 of the CMOS image sensor according to another embodiment of the present invention includes an impurity doped region 7 ′ whose concentration is gradually changed from the photodiode PD side to the floating diffusion region FD side. . For example, the impurity doped region 7 is a floating diffusion region as opposed to the first conductivity type impurity doped region 7a having a doping profile whose concentration gradually decreases from the photodiode PD side to the floating diffusion region FD side. It may have a second conductivity type impurity doped region 7b having a doping profile whose concentration gradually decreases from the (FD) side toward the photodiode PD side. The second conductivity type impurity doped region 7b has a doping profile complementary to that of the first conductivity type impurity doped region 7a. In this case, the first conductivity type may be P type, and the second conductivity type may be N type.

The impurity doped region 7 ′ as described above is of the first conductivity type, eg, P-type impurity doped region 7a and the second conductivity type, eg, N-type impurity doped region 7b having complementary doping profiles. ), It is advantageous for the P-type impurity doped region 7a to have a desired doping profile, so that the charge transfer efficiency can be reduced while reducing the dark current. Solid and dashed arrows in the figure indicate directions of increasing concentrations of impurities in the first and second impurity doped regions 7a and 7b, respectively.

Subsequently, a CMOS image sensor according to still another embodiment of the present invention will be described with reference to FIG. 6. 6 is a cross-sectional view of a CMOS image sensor according to another embodiment of the present invention. As shown in FIG. 6, the CMOS image sensor according to another exemplary embodiment of the present invention may include an impurity doped region 7 ′ provided in the channel region 6 and a first conductivity type diffusion region of the photodiode PD. Except for 4 ', the CMOS image sensor is substantially the same as the CMOS image sensor according to the exemplary embodiment. Therefore, a CMOS image sensor according to another embodiment of the present invention will be described based on differences between the CMOS image sensor according to another embodiment of the present invention and the CMOS image sensor according to another embodiment of the present invention. .

The first conductivity type, for example P ⁰ diffusion region 4 ′, of intermediate concentration of the photodiode PD of the CMOS image sensor according to a further embodiment of the invention is provided at any distance from the transfer gate 35. Spaced apart and located in the epi layer (2). This is to prevent the junction from diffusing into the channel region 6 under the gate 35 when the P ⁰ type diffusion region is finally completed by a subsequent heat treatment process.

In addition, in the channel region 6 under the transfer gate 35 of the CMOS image sensor according to another embodiment of the present invention, the concentration is gradually changed from the photodiode PD side to the floating diffusion region FD side. Impurity doped region 7 '. For example, the impurity doped region 7 is a floating diffusion region as opposed to the first conductivity type impurity doped region 7a having a doping profile whose concentration gradually decreases from the photodiode PD side to the floating diffusion region FD side. It may have a second conductivity type impurity doped region 7b having a doping profile whose concentration gradually decreases from the (FD) side toward the photodiode PD side. The second conductivity type impurity doped region 7b has a doping profile complementary to that of the first conductivity type impurity doped region 7a. In this case, the first conductivity type may be P type, and the second conductivity type may be N type.

According to another embodiment of the present invention, the CMOS image sensor may include a first having a doping profile complementary to the first conductivity type diffusion region 4 ′ positioned at an arbitrary distance from the transfer gate 35 as described above. By including the channel region 6 having the impurity doped region 7 'including the conductive impurity doped region 7a and the second impurity doped region 7b, the charge transfer efficiency is not reduced while reducing the dark current. can do. Solid arrows and dotted arrows in the figure indicate directions of increasing concentrations of impurities in the first and second impurity doped regions, respectively.

Subsequently, a method of manufacturing the CMOS image sensor according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3, 7, and 8. 7 and 8 are cross-sectional views of intermediate structures in which the CMOS image sensor manufacturing method according to an embodiment of the present invention is arranged step by step according to a process sequence.

First, as shown in FIG. 7, the semiconductor substrate 1 is prepared. As the semiconductor substrate 1, a high concentration of a first conductivity type, for example, a P ⁺⁺ type single crystal silicon substrate can be used. On one surface of the semiconductor substrate 1, for example, a surface for forming an element, a first conductive type, for example, a P ⁻ type epitaxial layer 2, which is grown by an epitaxial process, is formed. This is to increase the ability of the low voltage photodiode PD to collect photocharges and further improve the photosensitivity by forming large and deep depletion regions in the photodiode.

Next, the transfer transistor (30 in FIG. 2), the reset transistor (40 in FIG. 2), the drive, as well as the active region (10 in FIG. 2) and the floating diffusion region (FD in FIG. 3) of the photodiode (PD in FIG. 3). An isolation region 20 is formed in the epi layer 2 of the semiconductor substrate 1 to define an active region (10 in FIG. 2) for the transistor (50 in FIG. 2) and the select transistor (60 in FIG. 2). do. The device isolation region 2 may be formed by, for example, an STI process. Of course, the device isolation region may be formed by a LOCOS process or the like.

Subsequently, the gate insulating layer 150 is formed on the epitaxial layer 2 of the entire active region (10 of FIG. 2) including the active region (10 of FIG. 2) of the photodiode (FD of FIG. 3). In this case, the gate insulating film 150 is a gate insulating film for the transfer transistor (30 in FIG. 2), the reset transistor (40 in FIG. 2), the drive transistor (50 in FIG. 2) and the select transistor (60 in FIG. 2). For example, it may be formed into a thermal oxide film grown by a thermal oxidation process.

Next, a pattern of the photosensitive film 200 is formed on the gate insulating film 150. At this time, the pattern of the photosensitive film 200 exposes the channel region 6 of the transfer transistor (30 in FIG. 2). Using the pattern of the photosensitive film 200 as an ion implantation mask, the impurity doped region 70 is ion-implanted into the channel region 6 by a first conductivity type, for example, P-type impurity, at a predetermined inclination angle θ ₁ . Form. By injecting the impurity into the channel region 6 at a predetermined inclination angle θ ₁ , a portion of the channel region 6 is covered by the pattern of the photoresist layer 200, thereby causing a shading region to which impurities do not reach. . The shading region may be formed on the floating diffusion region (FD in FIG. 3).

Subsequently, when the semiconductor substrate 1 is heat-treated in the state where impurities are injected as shown in FIG. 8, the impurities diffuse to the side, that is, the floating diffusion region (FD in FIG. 3). Therefore, in the channel region 6, an impurity doped region 7 having an inclined doping profile having a relatively high concentration on the photodiode (PD in FIG. 3) side and a low concentration on the floating diffusion region (FD in FIG. 3) side is formed. do. Solid arrows in the figure indicate the direction of increasing the concentration of impurities in the impurity doped region 7.

Next, as shown in FIG. 3, the pattern of the photosensitive film of FIG. 8 is removed, and a conductive layer (not shown), for example, a high concentration polycrystal, for the transfer gate 35 is formed on the gate insulating film 150 of FIG. 8. Deposit a silicon layer. In this case, the conductive layer may include the transfer transistor (30 in FIG. 2), the reset transistor (40 in FIG. 2), the drive transistor (50 in FIG. 2), and the gates (35, 45 in FIG. 3) of the select transistor (60 in FIG. 3). 55, 65). Although not shown, the conductive layer may be formed of a high concentration polycrystalline silicon layer and a silicide layer thereon.

Subsequently, a photolithography process leaves a conductive layer and a gate insulating layer for the gate and removes the remaining conductive layer and the gate insulating layer to form a gate with the gate insulating layer 15 of the transfer transistor 35, and the photodiode PD And expose the surface of the active region (10 in FIG. 2) for the floating diffusion region FD. In addition, although not shown in the drawings, patterns of gate and gate insulating films for the reset transistor (40 in FIG. 2), the drive transistor (50 in FIG. 2) and the select transistor (60 in FIG. 2) are formed, and the reset transistor (FIG. 2) is used. 40), the surface of the active region (10 of FIG. 2) for the drive transistor (50 of FIG. 2) and the select transistor (60 of FIG. 2) is exposed.

Next, a pattern (not shown) of the photosensitive film is formed on the semiconductor substrate 1. At this time, the pattern of the photoresist layer exposes the epi layer 2 of the active pattern (10 of FIG. 2) for the floating diffusion region FD, and the epi layer of the active region (10 of FIG. 2) for the photodiode PD. Mask (2). Further, although not shown, the pattern of the photoresist film exposes the active regions (10 in FIG. 2) for the reset transistor (40 in FIG. 2), the drive transistor (50 in FIG. 2) and the select transistor (60 in FIG. 2). .

Subsequently, floating diffusion is performed by ion implanting low-concentration, second conductivity-type impurities, such as N-type impurities, into the epi layer of the active region for the floating diffusion region FD using the photoresist pattern as an ion implantation mask. An N ⁻ type diffusion region 5a is formed for the region. In addition, although not shown, N for LDD in the epi layer of the active region (10 in FIG. 2) for the reset transistor (40 in FIG. 2), the drive transistor (50 in FIG. 2) and the select transistor (60 in FIG. 2). ^- to form a type diffusion region.

Next, the pattern of the photosensitive film is removed, and a pattern (not shown) of the photosensitive film is formed on the semiconductor substrate 1. At this time, the pattern of the photoresist film exposes the epi layer 2 of the active region (10 in FIG. 2) for the photodiode PD and masks the N ⁻ type diffusion region 5a. Also, although not shown, the active regions (10 in FIG. 2) for the reset transistor (40 in FIG. 2), the drive transistor (50 in FIG. 2) and the select transistor (60 in FIG. 2) are masked.

Subsequently, a low concentration of the first conductivity type, for example, an N-type impurity, is applied to the epi layer 2 of the active region (10 in FIG. 2) for the photodiode PD using the pattern of the photosensitive film as an ion implantation mask. Ion implantation forms the N ⁻ type diffusion region 3 for the photodiode PD.

Next, a P ⁰ diffusion region 4 is formed on the N ⁻ type diffusion region 3 by ion implantation of a second conductivity type, for example, P type impurity, of low concentration at low energy. On the other hand, it is apparent that the photodiode PD having only the N ⁻ type diffusion region 3 can be formed by omitting the process of forming the P ⁰ diffusion region 4.

Subsequently, the pattern of the photoresist film is removed and the N ^- diffusion region 3, P ⁰ , using a chemical vapor deposition process, for example, a low pressure chemical vapor deposition process or the like. An insulating film (not shown), for example, an oxide film or a nitride film, is deposited for the spacers 36 on all regions of the semiconductor substrate 1 including the diffusion region 4 and the gate 35. Thereafter, the insulating layer is etched by a dry etching method or a wet etching method to form the spacers 36 on the sidewalls of the gate 35. Although not shown, spacers are formed on both sidewalls of the gates for the reset transistor (40 in FIG. 2), the drive transistor (50 in FIG. 2) and the select transistor (60 in FIG. 2), and the reset transistor (40 in FIG. 2). ), Active regions for the drive transistor (50 in FIG. 2) and the select transistor (60 in FIG. 2).

Next, a pattern (not shown) of the photosensitive film is formed on the semiconductor substrate 1. At this time, the pattern of the photosensitive film exposes the N ⁻ type diffusion region 5a and masks the P ⁰ type diffusion region 4 and the gate 35. Also, although not shown, the N ⁻ type diffusion region for the reset transistor (40 in FIG. 2), the drive transistor (50 in FIG. 2) and the select transistor (60 in FIG. 2) are exposed.

Subsequently, using a pattern of the photoresist as an ion implantation mask, a high concentration of a second conductivity type, for example N-type impurities, is ion-collected at high energy to form an N ⁺ type diffusion region 5b for the floating diffusion region FD. . In addition, although not shown, an N ⁺ type diffusion region is formed for the source / drain regions of the reset transistor (40 in FIG. 2), the drive transistor (50 in FIG. 2), and the select transistor (60 in FIG. 2).

Next, the pattern of the photoresist film is removed, and the N ^- type diffusion region 3, the P ⁰ type diffusion region 4, the N ^- type diffusion region 5a, N are subjected to a heat treatment process, for example, a rapid heat treatment process. ^The implanted impurities in the ⁺ type diffusion region 5b are diffused to diffuse the N ⁻ type diffusion region 3, the P ⁰ type diffusion region 4, the N ⁻ type diffusion region 5a and the N ⁺ type diffusion region 5b. Form a junction substantially. Although not shown, the junctions of the N ⁻ type diffusion region and the N ⁺ type diffusion region of the reset transistor (40 in FIG. 2), the drive transistor (50 in FIG. 2) and the select transistor (60 in FIG. 5) are substantially formed. do. Therefore, the manufacturing process for forming the unit pixel of the CMOS image sensor according to an embodiment of the present invention is completed. Solid arrows in the figure indicate the direction of increasing the concentration of impurities in the impurity doped region 7.

In the above, the case where the first conductivity type diffusion region 4 for the photodiode PD is formed before the spacer 36 of the transfer gate 35 is formed has been described by way of example, but the spacer ( After forming 36, a first conductivity type diffusion region (4 ′ in FIG. 4) may be formed for the photodiode PD.

Subsequently, a method of manufacturing the CMOS image sensor according to another exemplary embodiment of the present invention will be described with reference to FIGS. 5, 7, 9, and 10. 9 and 10 are cross-sectional views of intermediate structures in which a method of manufacturing a CMOS image sensor according to another embodiment of the present invention is arranged step by step according to a process sequence.

The manufacturing method of the CMOS image sensor according to another exemplary embodiment of the present invention is substantially the same as the manufacturing method of the CMOS image sensor according to the exemplary embodiment of the present invention except for the manufacturing method of the channel region of the transfer gate. Therefore, a method of manufacturing the CMOS image sensor according to another embodiment of the present invention will be described based on differences from the manufacturing method of the CMOS image sensor according to the exemplary embodiment of the present invention.

First, as in the method of manufacturing the CMOS image sensor according to the exemplary embodiment of the present invention, as shown in FIG. 7, the photoresist film 200 exposing the channel region 6 under the transfer gate (35 in FIG. 5) is exposed. A first conductive type impurity doped region (70a in FIG. 9) was formed by forming a pattern and ion implanting a first conductivity type, for example, P type impurity, into the channel region 6 at a predetermined inclination angle θ1 using the ion implantation mask. ). In this case, the inclination angle θ ₁ may vary according to the doping profile to be formed in the channel region. For example, the thickness of the pattern of the photosensitive film 200 is about 0.7 μm, and the width of the transfer transistor 35 is about. In the case of 1 μm, the inclination angle θ ₁ may be adjusted so that impurities are injected into the channel region on the photodiode PD side, that is, about 0.75 μm corresponding to 2/3 of the width of the entire channel region.

Next, as shown in FIG. 9, the second conductive type, for example, N type impurity, is predetermined in the channel region 6 by using the photosensitive film pattern 200 used as the ion implantation impurity as an ion implantation mask. The second conductivity type impurity doped region 70b is implanted by ion implantation at an inclination angle θ ₂ . The shading region is formed on the side of the photodiode (PD in FIG. 5), and the inclination angle θ ₂ is the channel region on the floating diffusion region FD side, that is, when the width of the transfer transistor 35 is about 1 μm. The inclination angle θ ₂ may be such that impurities are injected into a region corresponding to about 0.75 μm corresponding to two thirds of the width of the channel region. In this case, the impurity of the second conductivity type injected into the channel region 6 may be implanted with a higher energy than the impurity of the first conductivity type.

Subsequently, when the semiconductor substrate 1 is heat-treated in the state in which the first and second conductivity-type impurities are injected as shown in FIG. 10, the first conductivity-type impurities diffuse to the floating diffusion region (FD of FIG. 5). And the second conductivity type impurity diffuses into the photodiode (PD in FIG. 5). Therefore, in the channel region 6, the first conductivity type impurity doping has an inclined doping profile having a relatively high concentration at the photodiode (PD in FIG. 7) side and a relatively low concentration at the floating diffusion region (FD in FIG. 5) side. The region 7a is formed. Further, in the lower portion of the first impurity doped region 7a of the channel region 6, the inclined doping has a relatively low concentration on the photodiode (PD of FIG. 5) region and a relatively high concentration on the floating diffusion region 7b side. A second conductivity type impurity doped region 7b having a profile is formed. At this time, the doping profiles of the first conductivity type impurity doped region 7a and the second conductivity type impurity doped region 7b of the impurity doped region 7 'are complementary to each other. Solid and dashed arrows in the figure indicate directions of increasing concentrations of impurities in the first conductivity type impurity doped region 7a and the second conductivity type impurity doped region 7b, respectively.

The remaining process of forming a gate (35 in FIG. 5), forming a photodiode (PD in FIG. 5), and forming a floating diffusion region (FD in FIG. 5) is performed by a method of manufacturing a CMOS image sensor according to an embodiment of the present invention. Since they are substantially the same, redundant descriptions are omitted here.

In the above, the case where the first conductivity type diffusion region 4 for the photodiode PD is formed before the spacer 36 of the transfer gate (35 in FIG. 5) is described has been described by way of example, but the transfer gate 35 is described. After forming the spacer 36, the first conductivity type diffusion region (4 ′ in FIG. 6) for the photodiode PD may be formed. Although the case where the first conductivity type impurity region 7a is formed in the channel region 6 and the second conductivity type impurity region 7b has been described by way of example, the second conductivity type impurity is not limited to this order. It is a matter of course that the first conductivity type impurity region 7a can be formed after the region 7b is formed.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, the terms and expressions used herein are used for descriptive purposes only and do not have any limitation, and the use of such terms and expressions is illustrated. It is not intended to exclude equivalents of the described components or portions thereof, and various modifications are of course possible within the scope of the claimed invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

CMOS image sensor according to the embodiments of the present invention as described above can reduce the dark current, improve the charge transport efficiency can improve the product quality competitiveness.

Claims (10)

An active region defined by the device isolation region; A photodiode and a floating diffusion region disposed side by side in the active region; A gate of a transfer transistor across the active region between the photodiode and the floating diffusion region; And And a channel region positioned in the active region under the gate, the channel region including at least one impurity doped region whose concentration varies gradually from the photodiode side toward the floating diffusion region. The method of claim 1, The impurity doped region has a CMOS image sensor having a doping profile in which the concentration gradually decreases from the photodiode side toward the floating diffusion region side. The method of claim 2, And an impurity in the impurity doped region is a P-type CMOS image sensor. The method of claim 1, The impurity doped region may have a first conductivity type impurity doped region having a doping profile in which the concentration gradually decreases toward the floating diffusion region from the photodiode side and the first conductivity type under the first conductivity type impurity doped region. And a second conductivity type impurity doped region having a doping profile complementary to said doping profile of an impurity doped region. The method of claim 4, wherein The first conductivity type is P-type, the second conductivity type N-type CMOS image sensor. Defining an active region by the device isolation region; Implanting at least one impurity at a predetermined inclination angle using a pattern of the photoresist film exposing the channel region of the active region as an ion implantation mask; And Forming a gate of a transfer transistor across the channel region, a photodiode disposed side by side in the active region around the channel region and a floating diffusion region. The method of claim 6, Injecting the impurity at a predetermined inclination angle comprises injecting a first conductivity type impurity at a first inclination angle such that the channel region on the floating diffusion region side is shaded by a pattern of the photoresist layer. Method of manufacturing. The method of claim 7, wherein Injecting the impurity at a predetermined inclination angle further comprises implanting a second conductivity type impurity at a second inclination angle such that the channel region on the photodiode region side is shaded by the photoresist pattern. Method of preparation. The method according to claim 7 or 8, And the first conductivity type impurities and the second conductivity type impurities are N type and P type impurities. The method of claim 9, And the second conductivity type impurity implanted into the channel region is implanted with a relatively higher energy than the first conductivity type impurity.

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