KR20080001542A - Thin film transistor array substrate and manufacturing method thereof - Google Patents

Abstract

A TFT(thin film transistor) array substrate is provided to improve an aperture ratio and brightness by forming a common line in parallel with a data line and forming a storage capacitor between a gate metal and a common line. A gate metal is formed on a transparent substrate while a gate electrode is formed, and functions as a first electrode of a storage capacitor by being electrically connected to a pixel electrode through a contact hole. A gate insulation layer is formed on the gate metal, and functions as a dielectric layer of the storage capacitor. A common line(Vc2) is formed in parallel with a data line(D1,D2) of a DLS(data line sharing) driving type, and functions as a second electrode of the storage capacitor by being overlapped with the gate metal. The first electrode of the storage capacitor has a width greater or smaller than that of an overlapped common line. The common line is formed together with a source/drain electrode.

Description

Thin Film Transistor Array Substrate and Manufacturing Method Thereof}

1 is a view schematically illustrating a structure of a liquid crystal display panel of a data line sharing driving method according to the prior art.

FIG. 2 is an enlarged view of a portion of a pixel cell in the liquid crystal display panel shown in FIG. 1.

3 is a view schematically showing the structure of a thin film transistor array substrate according to an embodiment of the present invention.

FIG. 4 is an enlarged view of a portion of a pixel cell in the thin film transistor array substrate of FIG. 3.

FIG. 5 is a cross-sectional view taken along line A-A 'of the thin film transistor array substrate of FIG. 4.

6A and 6B illustrate an example of a portion B of the thin film transistor array substrate illustrated in FIG. 4.

<Description of the symbols for the main parts of the drawings>

G1o to Gno: Odd gate line G1e to Gne: Even gate line Vc1 to Vc (m / 2) +1: Common line D1 to D (m / 2): Data line

T11 to Tnm: switching element P11 to Pnm: pixel electrode

Cn2: first storage capacitor electrode Cn3: second storage capacitor electrode

The present invention relates to a liquid crystal display panel, and more particularly, to a thin film transistor array substrate for forming a storage capacitor in a data line sharing (DLS) driving method, and a manufacturing method thereof.

Recently, various devices such as a liquid crystal display device (LCD), a plasma display panel (PDP), and a vacuum fluorescent display (VFD) have been developed and used according to the demand for various flat panel display devices. Among such flat panel displays, LCDs having excellent image quality, light weight, thinness, and low power consumption have been widely used in various fields. In particular, LCDs are mostly used for monitors of notebook computers, and LCDs are also used for monitors of TV receivers and desktop computers.

1 is a view schematically illustrating a structure of a liquid crystal display panel of a data line sharing driving method according to the prior art.

As illustrated in FIG. 1, n odd gate lines G1o to Gno and n even gate lines G1e to Gne extending in a horizontal direction are formed in a liquid crystal display panel of a data line sharing driving method. In this case, for example, the i-th odd gate line Gio and the i-th even gate line Gie are arranged at intervals of almost pixel cells so that pixel cells are formed between each line. The i th even gate line Gie and the i + 1 th odd gate line G (i + 1) o are formed adjacent to each other.

Further, m / 2 data lines D1 to D (m / 2) are formed orthogonal to the odd and even gate lines G1o to Gno and G1e to Gne. At this time, for example, the j th data line Dj and the j + 1 th data line D (j + 1) are arranged at intervals of two pixel cells between the lines. If the data lines are m / 2, the pixel cells become m in the horizontal direction.

Meanwhile, pixel electrodes are formed between the odd and even gate lines and both of the data lines. Therefore, m pixel electrodes P11 to P1m are formed between the first odd and even gate lines G1o and G1e. Similarly, m pixel electrodes Pn1 to Pnm are formed between the n-th odd and even gate lines Gno and Gne, so that n × m pixel electrodes P11 to Pnm corresponding to n × m pixel cells as a whole are formed. Is formed.

Here, each of the pixel electrodes receives a data signal through an adjacent data line and a switching element (for example, a TFT). That is, a thin film transistor (TFT) for driving an arbitrary pixel electrode is connected to a data line adjacent to a source, a drain is connected to a pixel electrode, and a gate is connected to an odd or even gate line.

As shown in Fig. 1, in the liquid crystal display panel, the TFT connected to the pixel electrode formed on the left side of the data line is configured to operate according to the gate driving voltage from the odd gate line, and connected to the pixel electrode formed on the right side of the data line. TFT is configured to operate according to the gate driving voltage from the even gate line. Therefore, the gate of the TFT driving the pixel electrode formed on the left side of the data line is connected with the odd gate line, and the gate of the TFT driving the pixel electrode formed on the right side of the data line is connected with the even gate line.

Finally, a common line Vc1 for forming the pixel electrode and the storage capacitor is formed in the horizontal direction at the centers of the first odd and even gate lines G1o and G1e. In this manner, n common lines Vc1 to Vcn are formed between each odd and even gate line.

In the liquid crystal display panel of the conventional data line sharing driving method configured as described above, for example, when data is to be written to the pixel electrode of the first line, the first data signal is transmitted to the data lines D1 to D (m / 2). After scanning the first odd gate line (G1o) by applying to the second data signal is applied to the data lines (D1 ~ D (m / 2)) to scan the first even gate line (G1e). Therefore, the data signal is applied to the pixel electrodes P11, P13, ..., P1 (m-1) formed on the left side of the data line in the first scanning, and the pixel electrode P12 formed on the right side of the data line in the next scanning. , P14, ..., P1m) is applied to the data signal. In this manner, a scanning operation is performed from one line to n lines to apply a data signal to the pixel electrode.

FIG. 2 is an enlarged view of a portion 10 of a pixel cell in the liquid crystal display panel illustrated in FIG. 1. In FIG. 2, the pixel electrode Pn2 is called a first pixel electrode, and the pixel electrode Pn3 is called a second pixel electrode.

As illustrated in FIG. 2, a first electrode Cn2 of the first storage capacitor is formed in the common line Vcn at the center of the first pixel electrode Pn2 to form a storage capacitor. Similarly, the first electrode Cn3 of the second storage capacitor is formed in the common line Vcn at the center of the second pixel electrode Pn3 to form the storage capacitor. In this case, the pixel electrodes P11 to Pnm serve as the second electrode. Such storage capacitor electrodes are formed for all pixel electrodes P11 to Pnm. Such a storage capacitor formation method is called a storage on common method.

Therefore, according to such a conventional liquid crystal display panel, the aperture ratio is reduced by passing a common line parallel to the gate line through the central portion of all the pixel electrodes P11 to Pnm. In addition, according to the conventional liquid crystal display panel as described above, there is a problem that the luminance is decreased by decreasing the aperture ratio.

SUMMARY OF THE INVENTION An object of the present invention is to improve the aperture ratio and brightness, and to stably form a storage capacitor between a gate metal connected to a pixel electrode and a common line, and a method of manufacturing the same. To provide.

The thin film transistor array substrate of the present invention for achieving the above object is formed on the transparent substrate at the time of forming the gate electrode, the gate is electrically connected through the pixel electrode and the contact hole to serve as the first electrode of the storage capacitor metal; A gate insulating layer formed on the gate metal and serving as a dielectric layer of the storage capacitor; And a common line formed parallel to a data line of a data line sharing (DLS) driving method and overlapping the gate metal to serve as a second electrode of the storage capacitor.

Here, the width of the first electrode of the storage capacitor is wider than the width of the common line overlapping.

Here, the width of the first electrode of the storage capacitor is characterized in that narrower than the width of the common line overlapping.

The common line may be formed together when forming the source / drain electrodes.

On the other hand, the method of manufacturing a thin film transistor array substrate of the present invention, forming a first electrode of the storage capacitor formed together when forming the gate electrode on a transparent substrate; Forming a gate insulating film on the first electrode and the substrate of the storage capacitor; Forming a common line on the gate insulating layer to overlap the storage capacitor first electrode and serve as the storage capacitor second electrode; Forming a contact hole on the gate insulating film; And forming a pixel electrode on the contact hole, the pixel electrode being electrically connected to the first electrode of the capacitor.

The forming of the common line may be formed to be narrower than the width of the first electrode of the storage capacitor overlapping the width of the common line.

The forming of the common line may be formed to be wider than the width of the first electrode of the storage capacitor overlapping the width of the common line.

The common line may be formed together when forming the source / drain electrodes.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

3 is a view schematically showing the structure of a thin film transistor array substrate according to an embodiment of the present invention.

As shown in FIG. 3, the liquid crystal display panel of the data line sharing driving method according to an exemplary embodiment of the present invention has n odd gate lines G1o to Gno and n even gate lines G1e to Gne extending in a horizontal direction. ) Is formed. For example, the i-th odd gate line Gio and the i-th even gate line Gie are arranged at intervals of almost pixel cells so that pixel cells are formed between each line. In this case, the i-th even gate line Gie and the i + 1-th odd gate line G (i + 1) o are formed adjacent to each other.

Further, m / 2 data lines D1 to D (m / 2) are formed orthogonal to the odd and even gate lines G1o to Gno and G1e to Gne. At this time, for example, the j th data line Dj and the j + 1 th data line D (j + 1) are arranged at intervals of two pixel cells between the lines. If the data lines are m / 2, the pixel cells become m in the horizontal direction.

A pixel electrode is formed between the odd and even gate lines and both of the data lines. Therefore, m pixel electrodes P11 to P1m are formed between the first odd and even gate lines G1o and G1e. Similarly, m pixel electrodes Pn1 to Pnm are formed between the n-th odd and even gate lines Gno and Gne, and the n × m pixel electrodes P11 to Pnm corresponding to the n × m pixel cells as a whole. Is formed.

Each pixel electrode is connected to an adjacent data line through a switching element (for example, a TFT) to receive a data signal. That is, a TFT for driving an arbitrary pixel electrode is connected to a data line adjacent to a source, a drain is connected to a pixel electrode, and a gate is connected to an odd or even gate line.

As illustrated in FIG. 3, in the liquid crystal display panel according to the exemplary embodiment of the present invention, the pixel electrode formed on the left side of the data line is configured to operate according to gate driving voltages from odd gate lines G1o to Gno. The pixel electrode formed on the right side is configured to operate according to the gate driving voltages from even gate lines G1e to Gne.

Therefore, the gates of the TFTs driving the pixel electrodes formed on the left side of the data line are connected to odd gate lines G1o to Gno, and the gates of the TFTs driving the pixel electrodes formed on the right side of the data line are even gate lines G1e ~. Connected to Gne).

Lastly, common lines Vc1 to Vc (m / 2) +1 for forming a storage capacitor are formed to extend in a direction parallel to the data lines between two pixel electrodes between the data lines. Such common lines are formed by (m / 2) +1 pieces.

In the liquid crystal display panel of the data line sharing driving method of the present invention configured as described above, for example, when data is to be written to the pixel electrode of the first line, the first data signal is transmitted to the data lines D1 to D (m / 2). ) To scan the first odd gate line G1o and to apply the second data signal to the data lines D1 to D (m / 2) to scan the first even gate line G1e. In this manner, a scanning operation is performed from one line to n lines to apply a data signal to the pixel electrode.

FIG. 4 is an enlarged view of a portion 100 of a pixel cell in the thin film transistor array substrate of FIG. 3. In FIG. 4, the pixel electrode Pn2 is called a first pixel electrode, and the pixel electrode Pn3 is called a second pixel electrode.

As shown in FIG. 4, the gate metal connected to the first pixel electrode Pn2 is used as the first electrode Cn2 of the first storage capacitor, and the common line Vc2 is used as the second electrode of the first storage capacitor. 1 storage capacitor is formed. In addition, a second storage capacitor is formed using the gate metal connected to the second pixel electrode Pn3 as the first electrode Cn3 of the second storage capacitor and the common line Vc2 as the second electrode of the second storage capacitor. . The first storage capacitor electrode Cn2, which is the gate metal, is formed such that one side thereof is electrically connected to the first pixel electrode Pn2 and the other side thereof overlaps the common line Vc2. Similarly, the second electrode Cn3 of the second storage capacitor, which is the gate metal, is formed such that one side thereof is electrically connected to the second pixel electrode Pn3 and the other side thereof overlaps the common line Vc2.

Accordingly, the capacitance of the first storage capacitor formed between the first electrode Cn2 of the first storage capacitor and the common line Vc2 is between the first electrode Cn2 and the common line Vc2 of the first storage capacitor. Determined by overlap. In addition, the capacitance of the second storage capacitor formed between the first electrode Cn3 of the second storage capacitor and the common line Vc2 is between the first electrode Cn3 and the common line Vc2 of the second storage capacitor. Determined by overlap.

FIG. 5 is a cross-sectional view of an A-A 'portion of the thin film transistor array substrate shown in FIG. 4.

Referring to FIG. 5, a thin film transistor array substrate according to an embodiment of the present invention is formed together at the time of forming a gate electrode on a transparent substrate, and electrically connected to a pixel electrode through a contact hole to serve as a first electrode of a storage capacitor. A gate metal; A gate insulating layer formed on the gate metal and serving as a dielectric layer of the storage capacitor; And a common line formed parallel to a data line of a data line sharing (DLS) driving method and overlapping the gate metal to serve as a second electrode of the storage capacitor.

When the gate line of the TFT is formed on the transparent substrate, the first electrode Cn2 of the first storage capacitor is simultaneously formed. In addition, a first insulating layer is formed on the first electrode Cn2 of the first storage capacitor. In addition, a common line Vc2 is formed at a position corresponding to the first electrode Cn2 of the first storage capacitor on the first insulating layer to serve as a second electrode of the first storage capacitor.

Subsequently, a passivation film is formed on the common line Vc2 and the insulating film. Subsequently, a contact hole C is formed in the insulating film and the passivation film on the first electrode Cn2 of the first storage capacitor, and then a first pixel electrode is formed on the passivation film and the contact hole C. FIG. As a result, the first pixel electrode Pn2 and the first electrode Cn2 of the first storage capacitor are electrically connected to each other.

When the thin film transistor array substrate is completed in this manner, the thin film transistor array substrate may correspond to the first electrodes Cn2 and Cn3 of the first and second storage capacitor electrodes between the first pixel electrode Pn2 and the second pixel electrode Pn3. The black matrix BM1 having a predetermined width is formed on the color filter substrate at the position. Finally, the liquid crystal panel is completed by injecting and bonding the liquid crystal between the thin film transistor array substrate and the color filter substrate.

6A and 6B illustrate an example of a portion B of the thin film transistor array substrate illustrated in FIG. 4.

As shown in FIG. 6A, the first electrode Cn3 of the second storage capacitor is formed, for example, in the shape of a letter “b” (rotated 90 degrees clockwise). When the width of the common line Vc2 is W1, the width of the first electrode Cn3 of the second storage capacitor is W2. In this case, the width W2 of the first electrode Cn3 of the second storage capacitor is wider than the width W1 of the common line Vc2. Therefore, according to the embodiment, it is possible to secure a margin of the overlapping position of the first electrode Cn3 of the second storage capacitor and the common line Vc2, thereby obtaining stable storage capacitor capacity.

6B, the width of the common line Vc2 is W1, and the width of the first electrode Cn3 of the second storage capacitor is W3. In this case, the width W1 of the common line Vc2 is wider than the width W3 of the first electrode Cn3 of the second storage capacitor. According to this embodiment, it is possible to secure a margin of the overlap position between the common line Vc2 and the first electrode Cn3 of the second storage capacitor, thereby obtaining stable storage capacitor capacity. In particular, the left and right widths of the common line Vc2 and the first electrode Cn3 of the second storage capacitor may be set to secure a margin for preventing misalignment.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all aspects, and the scope of the present invention is indicated by the following claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

According to the present invention, the aperture ratio and the luminance can be improved by forming a common line parallel to the data line and forming a storage capacitor between the gate metal and the common line.

Claims (8)

A gate metal formed together with the gate electrode when the gate electrode is formed on the transparent substrate and electrically connected to the pixel electrode through a contact hole to serve as a first electrode of the storage capacitor; A gate insulating layer formed on the gate metal and serving as a dielectric layer of the storage capacitor; And A common line formed in parallel with a data line of a data line sharing (DLS) driving method and overlapping the gate metal to serve as a second electrode of the storage capacitor. Thin film transistor array substrate comprising a. The method of claim 1, The width of the first electrode of the storage capacitor is wider than the width of the overlapping common line substrate transistor array substrate. The method of claim 1, The width of the first electrode of the storage capacitor is narrower than the width of the overlapping common line transistor array substrate. The method of claim 1, The common line is a thin film transistor array substrate, characterized in that formed together when forming the source / drain electrode. Forming a first electrode of a storage capacitor formed together upon forming a gate electrode on the transparent substrate; Forming a gate insulating film on the first electrode and the substrate of the storage capacitor; Forming a common line on the gate insulating layer to overlap the storage capacitor first electrode and serve as the storage capacitor second electrode; Forming a contact hole on the gate insulating film; And Forming a pixel electrode on the contact hole, the pixel electrode being electrically connected to the first electrode of the capacitor Method of manufacturing a thin film transistor array substrate comprising a. The method of claim 5, The forming of the common line may include forming the common line smaller than the width of the first electrode of the storage capacitor overlapping the width of the common line. The method of claim 5, The forming of the common line may include forming the common line wider than the width of the first electrode of the storage capacitor overlapping the width of the common line. The method of claim 5, The common line is a method of manufacturing a thin film transistor array substrate, characterized in that formed together when forming the source / drain electrode.

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