KR20080000205A - Gate driving circuit and display apparatus having the same - Google Patents

Abstract

A gate driving circuit and a display device having the same are provided to reduce ripples in a control electrode of a pull-up unit by enlarging the capacitance of a charge capacitor ten times more than the parasite capacitance of a pull-up transistor. A gate driving circuit includes shift registers cascaded plural stages. An m-stage(SRCm) includes pull-up and pull-down parts(210,220), and a charger(212). The pull-up part includes a first transistor, which receives a first clock signal through a drain electrode thereof and outputs the first clock signal as a gate signal in response to the signal of a first node controlled by a first input signal inputted to a gate electrode. The pull-down part includes a second transistor for discharging the gate signal in response to a second input signal, which is inputted to gate electrode. The charger includes a charge capacitor between gate and source electrodes of the first transistor. The capacitance of the charge capacitor is ten times more than the parasite capacitance between drain and gate electrodes of a pull-up transistor.

Description

GATE DRIVING CIRCUIT AND DISPLAY APPARATUS HAVING THE SAME}

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of a first embodiment of the gate driving circuit shown in FIG. 1.

3 is a detailed circuit diagram of the stage shown in FIG.

4 is a signal waveform diagram of the stage shown in FIG.

<Description of the symbols for the main parts of the drawings>

IN1: first input terminal IN2: second input terminal

CK1: first clock terminal CK2: second clock terminal

V: voltage terminal RE: voltage terminal

CR: carry terminal OUT: output terminal

Cgd: Parasitic Capacitor Cgs: Charge Capacitor

210: pull-up part 212: charging part

220: pull-down unit 230: buffer unit

240: discharge portion 250: first holding portion

260: second holding unit 270: switching unit

280: reset unit 290: carry unit

T1 to T14: first to fourteenth transistors C1 and C2: first and second capacitors

The present invention relates to a gate driving circuit and a display device including the same, and more particularly, to a gate driving circuit for improving a driving failure and a display device including the same.

BACKGROUND ART In general, a liquid crystal display device is a display device that obtains a desired image signal by applying an electric field to a liquid crystal having an anisotropic dielectric constant injected between an array substrate and an opposing substrate, and adjusting the light transmittance according to the intensity of the electric field.

The liquid crystal display device includes a display panel in which a plurality of pixel portions are formed by gate lines and data lines crossing the gate lines, a gate driver driving the gate lines, and a data driver driving the data lines. Such a gate driver and a data driver are generally mounted on a display panel in a chip form.

Recently, in order to increase productivity while reducing the overall size, a method of integrating the gate driver on the display substrate in the form of an integrated circuit has been attracting attention. This requires the use of low-resistance metals to improve drive margins.

However, in this case, the I-V (current-voltage) characteristics of the thin film transistor are improved to improve the low temperature driving margin. However, at a high temperature, a noise defect occurs in which an abnormal gate on signal appears in the gate off signal section.

Specifically, the coupling with the clock signal by the parasitic capacitance Cgd of the pull-up device increases the off voltage of the gate electrode, and at the same time, the leakage current increases as the temperature increases to turn on the pull-up device. As a result, the gate-on signal is intermittently generated in the gate-off signal section, thereby causing a problem of poor image quality.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a gate driving circuit and a display device including the same to improve the driving failure of the display device.

The gate driving circuit according to the embodiment for realizing the object of the present invention is composed of a shift register coupled to a plurality of stages, the m-th stage includes a pull-up unit, a pull-down unit and a charging unit. The pull-up unit receives a first clock signal to a drain electrode and outputs the first clock signal as a gate signal in response to a signal of a first node that is switched to a high level by a first input signal input to a gate electrode. One transistor is included. The pull-down part includes a second transistor configured to discharge the gate signal to an off voltage in response to a second input signal input to the gate electrode. The charging unit includes a charging capacitor formed between the gate electrode and the source electrode of the first transistor, wherein the capacitance of the charging capacitor is at least 10 times the capacitance of the parasitic capacitor between the drain electrode and the gate electrode of the first transistor. do.

According to an exemplary embodiment of the present invention, a display area includes a display area in which a plurality of pixel parts are formed by gate lines and data lines crossing the gate lines, to display an image, and the display area. A display panel including a peripheral area surrounding the data line, the data driver outputting a data signal to the data lines; And a plurality of stages connected in a cascade form, in the form of an integrated circuit in the peripheral area, wherein each stage includes a gate driving circuit configured to output gate signals to the gate lines. Here, the m-th stage includes a pull-up part, a pull-down part and a charging part. The pull-up unit receives a first clock signal to a drain electrode and outputs the first clock signal as a gate signal in response to a signal of a first node that is switched to a high level by a first input signal input to a gate electrode. One transistor is included. The pull-down part includes a second transistor configured to discharge the gate signal to an off voltage in response to a second input signal input to the gate electrode. The charging unit includes a charging unit including a charging capacitor formed between the gate electrode and the source electrode of the first transistor, and the capacitance of the charging capacitor is 10 times the capacitance of the parasitic capacitor between the drain electrode and the gate electrode of the first transistor. It is characterized by the above.

According to the gate driving circuit and the display device including the same, the driving failure of the display device can be improved by reducing the ripple with the clock signal to prevent the occurrence of an abnormal gate on signal in the gate off signal section.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a display device according to an exemplary embodiment of the present invention includes a display panel 100, a gate driver 200 (hereinafter referred to as a gate driving circuit) and a data driver 130 for driving the display panel 100. do.

The display panel 100 is disposed between the array substrate 110 and the opposite substrate 120 (for example, the color filter substrate) that are opposed to the array substrate 110 at a predetermined interval and between the array substrate 110 and the opposite substrate 120. The display panel includes an intervening liquid crystal layer (not shown) and is divided into a display area DA and a peripheral area PA surrounding the display area DA.

In the display area DA, a plurality of pixel parts are formed by the gate lines GL formed in one direction and the data lines DL formed in a direction crossing the gate lines GL to display an image. Each pixel unit includes a thin film transistor TFT as a switching element, a liquid crystal capacitor CLC, and a storage capacitor CST electrically connected to the thin film transistor TFT. In detail, the gate electrode and the source electrode of the thin film transistor TFT are electrically connected to the gate line GL and the data line DL, respectively, and the liquid crystal capacitor CLC and the storage capacitor CST are electrically connected to the drain electrode. do.

The peripheral area PA includes a first peripheral area PA1 positioned at one end of the data lines DL and a second peripheral area PA2 positioned at one end of the gate lines GL.

The data driver 130 outputs a data signal to the data lines DL in synchronization with the gate signal applied to the gate line GL, and includes at least one data driving chip 132. The data driving chip 132 is mounted on the flexible circuit board 134 having one end connected to the first peripheral area PA1 of the display panel 100 and the other end connected to the printed circuit board 140. The substrate 134 is electrically connected to the printed circuit board 134 and the display panel 100.

The gate driving circuit 200 includes a shift register in which a plurality of stages are cascaded, and sequentially outputs gate signals to the gate lines GL. The gate driving circuit 200 is formed in the form of an integrated circuit integrated in the second peripheral area PA2 of the display panel 100.

FIG. 2 is a detailed block diagram of a first embodiment of the gate driving circuit shown in FIG. 1.

Referring to FIG. 2, the gate driving circuit 200 according to an exemplary embodiment of the present invention may include first to n + 1 stages SRC1 to SRCn + 1 connected to each other to sequentially output a gate signal GOUT. The circuit part CS and the wiring part LS which provide various control signals to the circuit part CS are included.

The first to nth + 1th stages SRC1 to SRCn + 1 are composed of n driving stages SRC1 to SRCn and one dummy stage SRCn + 1.

Each stage SRC includes a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, a voltage terminal V, and a reset terminal RE. , A carry terminal CR and an output terminal OUT.

The clock signals of opposite phases are provided to the first clock terminal CK1 and the second clock terminal CK2. Specifically, the first clock signal CK is provided to the first clock terminal CK1 of the odd-numbered stages SRC1, SRC3... Among the first to n + 1th stages SRC1 to SRCn + 1. The second clock terminal CK2 is provided with a second clock signal CKB having a phase opposite to that of the first clock signal CK. On the other hand, the second clock signal CKB is provided to the first clock terminal CK1 of the even-numbered stages SRC2, SRC4 ... among the first to n + 1th stages SRC1 to SRCn + 1. The second clock terminal CK2 is provided with a first clock signal CK having a phase opposite to that of the second clock signal CKB.

In other words, the first clock signal CK1 and the second clock terminal CK2 of the odd-numbered stages SRC1, SRC3..., The first clock signal CK and the second clock signal CKB of opposite phases are provided. The second clock signal CKB and the first clock signal CK are respectively provided to the first clock terminal CK1 and the second clock terminal CK2 of the even-numbered stages SRC2 and SRC4 ..., respectively. Is provided.

The first input terminal IN1 is provided with a vertical start signal STV or a carry signal of a previous stage. That is, the vertical start signal STV is provided to the first input terminal IN1 of the first stage SRC1, which is the first stage, and the first input of the second to n + 1 stages SRC2 to SRCn + 1. The terminal IN1 is provided with a carry signal of the previous stages SRC1 to SRCn.

The second input terminal IN2 is provided with a gate signal or a vertical start signal STV of the next stage. That is, the gate signals of the next stages SRC2 to SRCn + 1 are provided to the second input terminals IN2 of the first to nth stages SRC1 to SRCn, and the n + 1 which is the last stage SRCn + 1. The vertical start signal STV is provided to the second input terminal IN2 of the stage SRCn + 1.

The voltage terminal V is provided with an off voltage VOFF. For example, the off voltage VOFF has a voltage level of -5 to -7V.

The reset terminal RE is commonly provided with a carry signal of the last stage n + 1 stage SRCn + 1.

The output terminal OUT outputs a high section of the clock signal provided to the first clock terminal CK1. That is, a high period of the first clock signal CK is output to the output terminal OUT of the odd stages SRC1, SRC3..., Among the first to n + 1th stages SRC1 to SRCn + 1. The high terminal of the second clock signal CKB is output to the output terminal OUT of the even-numbered stages SRC2 and SRC4... Therefore, the first to n + 1th stages SRC1 to SRCn + 1 may sequentially output the gate signal GOUT.

On the other hand, the gate driving circuit 200 is formed on one side of the circuit unit CS and includes a plurality of wirings for providing a synchronization signal and a driving voltage to the first to n + 1th stages SRC1 to SRCn + 1. It includes a part LS.

The wiring part LS includes a start signal wiring SL1, a first clock wiring SL2, a second clock wiring SL3, a voltage wiring SL4, and a reset wiring SL5.

The start signal line SL1 receives the vertical start signal STV from the outside, and receives the received vertical start signal STV from the first input terminal IN1 of the first stage and the second input terminal IN2 of the last stage. To provide. That is, the vertical start signal STV is provided to the first input terminal IN1 of the first stage SRC1 and the second input terminal IN2 of the n + 1th stage SRCn + 1.

The first clock wire SL2 receives the first clock signal CK from the outside, and receives the first clock signal CK from the first clock terminal CK1 of the odd-numbered stages SRC1, SRC3... And the second clock terminal CK2 of the even-numbered stages SRC2, SRC4 ....

The second clock wire SL3 receives a second clock signal CKB having a phase opposite to that of the first clock signal CK from the outside, and receives the second clock signal CKB from the odd-numbered stages SRC1 and SRC3. ... to the second clock terminal CK2 and the first clock terminal CK1 of the even-numbered stages SRC2, SRC4 ....

The voltage line SL4 receives the off voltage VOFF from the outside and provides the voltage to the voltage terminal V of the first to n + 1th stages SRC1 to SRCn + 1, and the reset line SL5 is the last stage. The carry signal of (SRCn + 1) is received and provided to the reset terminal RE of the first to n + 1th stages SRC1 to SRCn + 1.

In the meantime, the gate driving circuit 200 receives the carry signal of the m-th stage SRCm-1 as the first input signal in the m-th stage SRCm, and receives the m + 1th stage SRCm + 1. The case in which the gate signal of is supplied as the second input signal and driven is described. However, depending on the characteristics of the gate signal GOUT (for example, the length of the signal section, etc.), the m-2, m-3, m-4,... Receiving a carry signal such as a stage as a first input signal, and receiving m + 2, m + 3, m + 4,... It may be driven by receiving a gate signal such as a stage as a second input signal.

3 is a detailed circuit diagram of the stage shown in FIG. 2, and FIG. 4 is a signal waveform diagram of the stage shown in FIG.

3 and 4, the m th stage SRCm of the gate driving circuit 200 according to the exemplary embodiment of the present invention may be configured to include a first clock signal in response to a signal of a first input terminal (hereinafter, referred to as a first input signal). A signal of the pull-up unit 210 and the second input terminal (hereinafter, referred to as a second input signal) that outputs CK as the m-th gate signal GOUTm to pull-up the m-th gate signal GOUTm. And a pull-down part 220 that discharges the m-th gate signal GOUTm to an off voltage and pulls down in response to the signal. Here, the first input signal is a carry signal of the vertical start signal STV or the m-1th stage SRCm-1, and the second input signal is the m + 1th gate of the m + 1th stage SRCm + 1. Signal GOUTm + 1 or vertical start signal STV.

The pull-up unit 210 has a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1, and a source electrode connected to the first transistor T1 connected to the output terminal OUT. Is done. Therefore, the drain electrode of the first transistor T1 receives the first clock signal CK through the first clock terminal CK1.

The pull-down unit 220 has a gate electrode connected to the second input terminal IN2, a drain electrode connected to the output terminal OUT, and a source electrode connected to the voltage terminal V to provide an off voltage VOFF. Consisting of a second transistor T2.

The m-th stage SRCm further includes a pull-up driving unit which turns on the pull-up unit 210 in response to the first input signal and turns off the pull-up unit 210 in response to the second input signal. The pull-up driving unit includes a buffer unit 230, a discharge unit 240, and a charging unit 212.

The buffer unit 230 includes a third transistor T3 having a gate electrode and a drain electrode connected to the first input terminal IN1 in common, and a source electrode connected to the first node N1.

The discharge unit 240 has a gate electrode connected to the second input terminal IN2, a drain electrode connected to the first node N1, and a source electrode connected to the voltage terminal V so that the off voltage VOFF is applied. The fourth transistor T4 is provided.

The charging unit 212 includes a charging capacitor Cgs defined as a parasitic capacitor formed between the gate electrode and the source electrode of the first transistor. That is, the first electrode is connected to the first node N1 and the second electrode is formed of the charging capacitor Cgs connected to the output terminal OUT. The charging capacitor Cgs has a capacity 10 times larger than that of the parasitic capacitor Cgd formed between the gate electrode and the drain electrode of the first transistor T1.

When the third transistor T3 is turned on in response to the first input signal, the pull-up driving unit applies the first input signal to the first node N1 to switch the signal of the first node N1 to a high level. And charging charge capacitor Cgs at the same time. Subsequently, when charge or more than the threshold voltage of the first transistor T1 is charged in the charging capacitor Cgs and the first clock signal CK becomes a high period, the first transistor T1 is bootstraped to form a first voltage. The high section of the one clock signal CK is output to the output terminal OUT.

That is, the first transistor T1 is bootstraped and outputs the high period of the first clock signal CK as the gate-on signal of the m-th stage SRCm. Subsequently, when the fourth transistor T4 is turned on in response to the second input signal, the charge charged in the charging capacitor Cgs is discharged to the off voltage VOFF of the voltage terminal V, so that the first transistor T1 is turned on. ) Is turned off.

The m-th stage SRCm turns off the first holding part 250 which maintains the signal of the first node N1 at the off voltage VOFF state in the gate-off signal period, and the outputting m-th gate signal GOUTm. The apparatus further includes a second holding part 260 for maintaining the voltage VOFF and a switching part 270 for controlling the on / off operation of the second holding part 260.

The first holding part 250 includes a fifth transistor T5 and a sixth transistor T6. In the fifth transistor T5, a gate electrode is connected to the first clock terminal CK1, and a drain electrode is formed of the fifth transistor T5. It is connected to one node N1, and a source electrode is connected to the output terminal OUT. In the sixth transistor T6, a gate electrode is connected to the second clock terminal CK2, a drain electrode is connected to the first input terminal IN1, and a source electrode is connected to the first node N1.

The first holding part 250 maintains the signal of the first node N1 at the off voltage VOFF after the m-th gate signal GOUTm is discharged to the off voltage VOFF by the pull-down part 220. That is, when the fifth transistor T5 is turned on in response to the first clock signal CK, the m-th gate signal GOUTm discharged to the off voltage VOFF is applied to the first node N1 to generate the first node N1. The signal of one node N1 is kept at the off voltage VOFF. In addition, when the sixth transistor T6 is turned on in response to the second clock signal CKB having a phase opposite to that of the first clock signal CK, the first input signal having the off voltage VOFF state may be provided as the first input signal. It is applied to the node N1 to maintain the signal of the first node N1 at the off voltage VOFF.

As such, the fifth transistor T5 and the sixth transistor T6 are alternately turned on in response to the first clock signal CK and the second clock signal CKB, respectively, so that the signal of the first node N1 is turned on. Is maintained at the off voltage (VOFF).

The second holding part 260 is composed of a seventh transistor T7 and an eighth transistor T8. In the seventh transistor T7, a gate electrode is connected to the second clock terminal CK2, and the drain electrode is output. It is connected to the terminal OUT, the source electrode is connected to the voltage terminal (V) to receive an off voltage (VOFF). In the eighth transistor T8, the gate electrode is connected to the second node N2 of the switching unit 270, the drain electrode is connected to the output terminal OUT, and the source electrode is connected to the voltage terminal V to turn off. The voltage VOFF is provided.

The switching unit 270 includes ninth through twelfth transistors T9, T10, T11, and T12 and first and second capacitors C1 and C2.

The gate electrode and the drain electrode of the ninth transistor T9 are commonly connected to the first clock terminal CK1 to receive the first clock signal CK, and the source electrode is connected to the drain electrode of the tenth transistor T10. do. The gate electrode of the tenth transistor T10 is connected to the output terminal OUT, and the source electrode is connected to the voltage terminal V to receive an off voltage VOFF. The drain electrode of the eleventh transistor T11 is connected to the first clock terminal CK1, the gate electrode is connected to the first clock terminal CK1 through the first capacitor C1, and the source electrode is connected to the second node ( N2). Accordingly, the drain electrode and the gate electrode of the eleventh transistor T11 are provided with the first clock signal CK, and the second capacitor C2 is connected between the gate electrode and the source electrode of the eleventh transistor T11. The twelfth transistor T12 has a gate electrode connected to an output terminal OUT, a drain electrode connected to a second node N2, and a source electrode connected to a voltage terminal V to provide an off voltage VOFF. Receive.

When the first clock signal CK is output to the output terminal OUT while the ninth transistor T9 and the eleventh transistor T11 are turned on by the first clock signal CK, the output terminal OUT ) Is switched to the high level. As the output terminal OUT is switched to the high level, the tenth and twelfth transistors T10 and T12 are turned on, and the voltages output from the ninth and eleventh transistors T9 and T11 are the tenth and twelfth. The transistors are discharged to the off voltage VOFF through the transistors T10 and T12. Therefore, the signal of the second node N2 is maintained at a low level, and the eighth transistor T8 is turned off.

Thereafter, when the m-th gate signal GOUTm is discharged to the off voltage VOFF in response to the second input signal, the potential of the output terminal OUT gradually decreases to a low state. Accordingly, the tenth and twelfth transistors T10 and T12 are turned off, and the potential of the second node N2 is set to a high level by the voltage output from the ninth and eleventh transistors T9 and T11. Is switched. As the potential of the second node N2 is switched to the high level, the eighth transistor T8 is turned on and the potential of the output terminal OUT is turned off by the turned-on eighth transistor T8. VOFF) to discharge faster.

Thereafter, when the first clock signal CK is switched to the low level, the potential of the second node N2 is also switched to the low level, and the eighth transistor T8 is turned off. On the other hand, the seventh transistor T7 is turned on by the second clock signal CKB having a phase opposite to that of the first clock signal CK to discharge the potential of the output terminal OUT to the off voltage VOFF. .

As such, the seventh transistor T7 and the eighth transistor T9 of the second holding unit 260 alternately output the output terminal OUT in response to the signals of the second clock signal CKB and the second node N2, respectively. Is discharged to the off voltage (VOFF).

The m-th stage of the gate driving circuit 200 according to the embodiment of the present invention further includes a reset unit 280 and a carry unit 290.

In the reset unit 260, a gate electrode is connected to the reset terminal RE, a drain electrode is connected to the first node N1, and a source electrode is connected to the voltage terminal V to provide an off voltage VOFF. The thirteenth transistor T13 is formed. When the carry signal of the last stage n + 1 stage SRCn + 1 is provided to the reset terminal RE, the thirteenth transistor T13 is turned on so that the potential of the first node N1 is turned off ( VOFF). Therefore, the m-th gate signal GOUTm is discharged to the off voltage VOFF by the carry signal of the n + 1th stage SRCn + 1.

The carry unit 290 has a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1 to receive a first clock signal CK, and the source electrode has a carry terminal CR. The fourteenth transistor T14 is connected to The carry unit 290 outputs a high section of the first clock signal CK to the carry terminal CR as the potential of the first node N1 is changed to a high level.

As described above, the m-th stage SRCm has a value in which the capacitance of the charging capacitor Cgs is 10 times larger than the capacitance of the parasitic capacitor Cgd between the gate electrode and the drain electrode of the first transistor T1. As a result, ripple generated in the first node N1 connected to the control electrode of the first transistor T1 may be improved.

In general, the ripple generated at the first node N1 by the parasitic capacitor Cgd between the gate electrode and the drain electrode of the first transistor T1 by the coupling with the first clock signal CK is represented by Equation I below. Can be obtained using

Here, Vr is a ripple voltage generated at the first node N1, Cgd is a parasitic capacitance between the gate electrode and the drain electrode of the first transistor T1, Cgs is the capacitance of the charging capacitor, and ΔCKV is the first clock. This is the variation (peak value) of the signal CK.

As described above, as the capacitance of the charging capacitor Cgs increases, the ripple of the first node N1 generated by the first clock signal CK decreases. That is, since the capacitance of the charging capacitor Cgs has a value 10 times larger than the capacitance of the parasitic capacitor Cgd, the ripple generated in the first node N1 is reduced to a level where no high temperature noise occurs. As a result, poor driving of the display device can be improved.

On the other hand, if the capacitance of the charging capacitor Cgs is increased, the ripple of the first node N1 is reduced to improve the high temperature noise defect, while the third, fourth, fifth, and third connected to the first node N1 are improved. And a low temperature driving margin of the sixth transistors T3, T4, T5, and T6.

Therefore, the width / length ratio W / L of the next first transistor T1 may be formed to satisfy the condition of the following Equation II so as to improve the high temperature noise defect and not affect the low temperature driving margin. That is, the first transistor T1 is formed to satisfy the condition of Equation II to improve driving current characteristics of the first transistor T1 to improve low temperature driving margin.

Here, GLm_cap is the sum of the capacities of all the caps connected to the m-th gate line GLm, and the unit is [k], L is the number of gate lines, and Hz is a driving frequency.

At this time, if the first transistor T1 is formed to have a value greater than 0.15, high-temperature noise may occur due to excessive improvement of driving current characteristics. Therefore, forming the first transistor T1 to have a value less than 0.15 is preferable. desirable.

As such, in the m-th stage SRCm of the gate driving circuit 200 according to the present invention, the capacitance of the charging capacitor Cgs is 10 times the capacitance of the parasitic capacitor Cgd between the gate electrode and the drain electrode of the first transistor t1. The first transistor T1 is formed to have the above value and the resultant value of Equation II is 0.09 to 0.15, thereby improving the high temperature noise defect.

As described above, according to the present invention, the capacitance of the charging capacitor constituting the charging unit has a value of 10 times or more of the capacitance of the parasitic capacitor between the gate electrode and the drain electrode of the pull-up transistor. Is reduced. As a result, the gate-on signal that is abnormally generated in the gate-off signal period can be prevented, thereby improving the driving failure of the display device.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (9)

A plurality of stages are composed of shift registers that are cascaded The m stage A first transistor receiving a first clock signal through a drain electrode and outputting the first clock signal as a gate signal in response to a signal of a first node that is switched to a high level by a first input signal input to a gate electrode; Pull-up unit comprising; A pull-down unit including a second transistor configured to discharge the gate signal to an off voltage in response to a second input signal input to a gate electrode; A charging unit including a charging capacitor formed between the gate electrode and the source electrode of the first transistor, And the capacitance of the charging capacitor is more than 10 times the capacitance of the parasitic capacitor between the drain electrode and the gate electrode of the first transistor. The gate driving circuit according to claim 1, wherein the width / length ratio (W / L) of the first transistor is defined by the following equation:

Here, GLm_cap is the sum of the capacities of the caps connected to the m-th gate wiring, L is the number of gate wirings, and Hz is a driving frequency. 3. The display device of claim 2, further comprising: a buffer unit including a third transistor configured to switch the first node to a high level in response to the first input signal; A discharge unit including a fourth transistor configured to discharge the first node to an off voltage in response to the second input signal; A fifth transistor that maintains the signal of the first node at an off voltage in response to a second clock signal, and a sixth transistor that maintains the signal of the first node at an off voltage in response to the first clock signal; A first holding part; A second holding part including a seventh transistor configured to maintain the gate signal at an off voltage in response to the second clock signal, and an eighth transistor configured to alternately maintain the gate signal at an off voltage with the seventh transistor; And And a switching unit for switching on / off of the eighth transistor. The method of claim 3, wherein the switching unit A ninth transistor in which a drain electrode and a gate electrode are provided with the first clock signal in common; A drain electrode connected to the source electrode of the ninth transistor, the gate electrode provided with the gate signal, and the source electrode provided with an off voltage; A drain electrode receives a first clock signal, and a gate electrode includes an eleventh transistor connected to a source electrode of the ninth transistor; The drain electrode is connected to the source electrode of the eleventh transistor to form a second node, the gate electrode is provided with the gate signal in common with the gate electrode of the tenth transistor, and the twelfth transistor is provided with an off voltage to the source electrode. ; A first capacitor connected between the drain electrode and the gate electrode of the eleventh transistor; And A second capacitor connected between the gate electrode and the source electrode of the third transistor, And the eighth transistor is turned on / off by a signal of the second node. The method of claim 4, wherein the first input signal is a vertical start signal or a carry signal of an m-th stage. And the second input signal is a gate signal or a vertical start signal of an m + 1th stage. 5. The gate driving circuit according to claim 4, wherein the first clock signal and the second clock signal are out of phase with each other. A display panel including a display area in which a plurality of pixel parts are formed by gate wires and data wires crossing the gate wires to display an image, and a peripheral area surrounding the display area; A data driver which outputs a data signal to the data lines; And Comprising a plurality of stages are connected in a cascade form in the peripheral region, each stage includes a gate driving circuit for outputting the gate signals to the gate wirings, The m stage A first transistor receiving a first clock signal through a drain electrode and outputting the first clock signal as a gate signal in response to a signal of a first node that is switched to a high level by a first input signal input to a gate electrode; Pull-up unit comprising; A pull-down unit including a second transistor configured to discharge the gate signal to an off voltage in response to a second input signal input to a gate electrode; And a charging unit including a charging capacitor formed between the gate electrode and the source electrode of the first transistor, wherein the capacitance of the charging capacitor is equal to or more than 10 times the capacitance of the parasitic capacitor between the drain electrode and the gate electrode of the first transistor. Display device. 8. The gate driving circuit of claim 7, wherein the width / length ratio (W / L) of the first transistor is defined by the following equation:

Here, GLm_cap is the sum of the capacities of the caps connected to the mth gate line, L is the number of gate lines, and Hz is a driving frequency. The method of claim 8, wherein the first input signal is a vertical start signal or a carry signal of an m-th stage. And the second input signal is a gate signal or a vertical start signal of an m + 1th stage.

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