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KR20070107903A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
KR20070107903A
KR20070107903A KR1020060040462A KR20060040462A KR20070107903A KR 20070107903 A KR20070107903 A KR 20070107903A KR 1020060040462 A KR1020060040462 A KR 1020060040462A KR 20060040462 A KR20060040462 A KR 20060040462A KR 20070107903 A KR20070107903 A KR 20070107903A
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KR
South Korea
Prior art keywords
interlayer insulating
landing plug
manufacturing
semiconductor device
forming
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KR1020060040462A
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Korean (ko)
Inventor
홍재옥
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주식회사 하이닉스반도체
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Priority to KR1020060040462A priority Critical patent/KR20070107903A/en
Publication of KR20070107903A publication Critical patent/KR20070107903A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for manufacturing a semiconductor device is provided to etch an interlayer dielectric between landing plugs by performing an etch process using a bridge removal mask, and to prevent elements from become bad by remove bridges between landing plugs. A gate is formed on an upper surface of a semiconductor substrate(111) including an isolation region(113) and an active region(115). A first interlayer dielectric(123) is formed on the gate and the semiconductor substrate. A landing plug(119) is formed on an upper surface of the first interlayer dielectric. A photoresist layer pattern(125) having a shape of rectangle is formed to expose the isolation region. The first interlayer dielectric is etched by using the photoresist layer pattern as a mask. The photoresist layer pattern is removed by etching the first interlayer dielectric.

Description

반도체 소자의 제조방법{METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

도 1a 내지 도 1c는 종래기술에 따른 반도체 소자의 제조방법을 도시한 단면 및 평면도.1A to 1C are cross-sectional and plan views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 2는 종래기술에 따른 반도체 소자의 제조방법의 문제점을 설명하기 위해 도시한 SEM 사진도.Figure 2 is a SEM photograph shown to explain the problems of the manufacturing method of a semiconductor device according to the prior art.

도 3은 본 발명에 따른 반도체 소자를 도시한 평면도.3 is a plan view showing a semiconductor device according to the present invention.

도 4a 내지 도 4d는 본 발명에 따른 반도체 소자의 제조방법을 도시한 단면도.4A to 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 5는 본 발명에 따른 반도체 소자의 제조방법에 의해 형성된 제 2 층간절연막(127)에 보이드(void)가 발생한 경우를 도시한 단면도.5 is a cross-sectional view illustrating a case in which voids are generated in the second interlayer insulating film 127 formed by the method of manufacturing a semiconductor device according to the present invention.

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 랜딩 플러그 형성 공정시 발생되는 브릿지(bridge)를 제거함으로써 소자 불량을 방지할 수 있는 반도체 소자의 제조방법에 관한 기술이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing device defects by removing bridges generated during a landing plug forming process.

도 1a 내지 도 1c는 종래기술에 따른 반도체 소자의 제조방법을 도시한 단면 및 평면도이다.1A to 1C are cross-sectional and plan views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 1a를 참조하면, 소자분리 영역(13)과 활성 영역(15)이 구비된 반도체 기판(11) 상에 게이트(17)를 형성한다.Referring to FIG. 1A, a gate 17 is formed on a semiconductor substrate 11 having an isolation region 13 and an active region 15.

도 1b를 참조하면, 전체 표면 상부에 층간 절연막(21)을 형성한다. Referring to FIG. 1B, an interlayer insulating film 21 is formed on the entire surface.

이때, 상기 층간 절연막(21)이 상기 게이트(17) 사이에 완전히 매립되지 못해 보이드(void)(23)가 발생되는 것을 볼 수 있다.In this case, it can be seen that the void 23 is generated because the interlayer insulating layer 21 is not completely embedded between the gates 17.

도 1c를 참조하면, 콘택 마스크를 이용하여 상기 층간 절연막(21)을 선택적으로 식각하여 랜딩 플러그 콘택홀(미도시)을 형성한다. Referring to FIG. 1C, the interlayer insulating layer 21 is selectively etched using a contact mask to form a landing plug contact hole (not shown).

그 다음, 상기 랜딩 플러그 콘택홀을 포함한 상기 반도체 기판(11) 상에 랜딩 플러그용 폴리실리콘막(미도시)을 형성하고, 상기 층간 절연막(21)을 식각하여 랜딩 플러그(19)를 형성한다.Next, a landing plug polysilicon layer (not shown) is formed on the semiconductor substrate 11 including the landing plug contact hole, and the interlayer insulating layer 21 is etched to form a landing plug 19.

이때, 상기 보이드(void)(23) 내에도 상기 랜딩 플러그용 폴리실리콘막이 유입되어 상기 랜딩 플러그(19) 간에 브릿지(bridge)가 발생된다.At this time, the landing plug polysilicon film also flows into the void 23 to generate a bridge between the landing plugs 19.

도 2는 종래기술에 따른 반도체 소자의 제조방법의 문제점을 설명하기 위해 도시한 SEM 사진도이다.2 is a SEM photograph illustrating a problem of a method of manufacturing a semiconductor device according to the prior art.

도 2을 참조하면, 상기 보이드(void)(23)로 인하여 상기 랜딩 플러그(19) 간에 브릿지(bridge)가 발생되는 것을 볼 수 있다.Referring to FIG. 2, it can be seen that a bridge is generated between the landing plugs 19 due to the voids 23.

상술한 종래기술에 따른 반도체 소자의 제조방법은, 랜딩 플러그 형성 공정시 상기 층간 절연막(21)이 상기 게이트(17) 사이에 완전히 매립되지 못하여 보이드(void)(23)가 발생되는 경우, 상기 보이드(void)(23)에 의해 상기 랜딩 플러 그(19) 간에 브릿지(bridge)가 발생되어 소자 불량을 유발하는 문제점이 있다.In the above-described method of manufacturing a semiconductor device according to the related art, when the void 23 is generated because the interlayer insulating film 21 is not completely embedded between the gates 17 during the landing plug forming process, the voids are generated. There is a problem in that a bridge is generated between the landing plugs 19 by the void 23 and causes device defects.

본 발명은 상기와 같은 문제점을 해결하기 위하여 창출된 것으로, 랜딩 플러그 형성 공정 이후 브릿지 제거용 마스크를 이용한 사진 식각 공정으로 랜딩 플러그 사이의 층간 절연막을 식각함으로써 랜딩 플러그 간에 브릿지(bridge)를 제거하여 소자 불량을 방지할 수 있는 반도체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, and by removing the bridge between the landing plug by etching the interlayer insulating film between the landing plug by a photolithography process using a mask for removing the bridge after the landing plug forming process It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of preventing a defect.

상기한 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, (a) 소자분리 영역과 활성 영역이 구비된 반도체 기판 상부에 게이트를 형성하는 단계;(b) 게이트 및 반도체 기판 상에 제 1 층간절연막을 형성하는 단계; (c) 제 1 층간절연막 상에 랜딩 플러그를 형성하는 단계; (d) 소자분리 영역을 노출시키는 직사각형 형태의 감광막 패턴을 형성하는 단계; 및 (e) 감광막 패턴을 마스크로 제 1 층간절연막을 식각하고, 감광막 패턴을 제거하는 단계를 포함하는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: (a) forming a gate on a semiconductor substrate having an isolation region and an active region; Forming an interlayer insulating film; (c) forming a landing plug on the first interlayer insulating film; (d) forming a rectangular photosensitive film pattern exposing the device isolation region; And (e) etching the first interlayer insulating film using the photosensitive film pattern as a mask and removing the photosensitive film pattern.

이하, 첨부한 도면을 참조하여 본 발명의 실시예에 대해 상세히 설명하고자 한다. Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

도 3은 본 발명에 따른 반도체 소자를 도시한 평면도이다.3 is a plan view showing a semiconductor device according to the present invention.

도 3를 참조하면, 소자분리 영역(113)과 활성 영역(115)이 구비된 반도체 기판(111) 상에 게이트(117)가 형성되어 있다. 그리고, 상기 반도체 기판(111)에 접 속되는 랜딩 플러그(미도시)가 형성되어 있다. 그리고, 상기 랜딩 플러그 상부에 상기 활성 영역(115)의 길이 방향과 나란하게 형성되어 상기 활성 영역(115) 사이의 상기 소자분리 영역(113)을 노출시키는 직사각형 형태의 브릿지 제거용 마스크(121)가 형성되어 있다.Referring to FIG. 3, a gate 117 is formed on a semiconductor substrate 111 having an isolation region 113 and an active region 115. In addition, a landing plug (not shown) connected to the semiconductor substrate 111 is formed. In addition, a rectangular mask removal mask 121 is formed on the landing plug in parallel with the longitudinal direction of the active region 115 to expose the device isolation region 113 between the active regions 115. Formed.

도 4a 내지 도 4d는 본 발명에 따른 반도체 소자의 제조방법을 도시한 단면도로서, 도 3의 A-A' 절단면을 따라 도시한 것이다.4A through 4D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention, and are taken along the line AA ′ of FIG. 3.

도 4a를 참조하면, 상기 소자분리 영역(113)과 활성 영역(115)이 구비된 반도체 기판(111) 상에 게이트(미도시)를 형성한다.Referring to FIG. 4A, a gate (not shown) is formed on the semiconductor substrate 111 having the device isolation region 113 and the active region 115.

그 다음, 상기 게이트 및 반도체 기판(111) 상부에 제 1 층간 절연막(123)을 형성하고, 콘택 마스크를 이용하여 상기 제 1 층간 절연막(123)을 선택적으로 식각하여 랜딩 플러그 콘택홀(미도시)을 형성한다. Next, a first interlayer insulating layer 123 is formed on the gate and the semiconductor substrate 111, and the first interlayer insulating layer 123 is selectively etched using a contact mask to make a landing plug contact hole (not shown). To form.

그 다음, 상기 랜딩 플러그 콘택홀을 포함한 상기 반도체 기판(111) 상에 랜딩 플러그용 폴리실리콘막(미도시)을 형성하고, 상기 제 1 층간 절연막(123)을 식각하여 랜딩 플러그(119)를 형성한다.Next, a landing plug polysilicon layer (not shown) is formed on the semiconductor substrate 111 including the landing plug contact hole, and the first interlayer insulating layer 123 is etched to form a landing plug 119. do.

이때, 상기 랜딩 플러그(119) 간에 브릿지(bridge)(123)가 발생되는 것을 볼 수 있다.In this case, it can be seen that a bridge 123 is generated between the landing plugs 119.

도 4b를 참조하면, 전체 표면 상부에 감광막(미도시)을 형성하고, 상기 활성 영역(115)의 길이 방향과 나란하게 형성되어 상기 활성 영역(115) 사이의 상기 소자분리 영역(113)을 노출시키는 직사각형 형태의 브릿지 제거용 마스크(미도시)로 상기 감광막을 선택적으로 식각하여 감광막 패턴(125)을 형성한다.Referring to FIG. 4B, a photoresist film (not shown) is formed on the entire surface, and is formed to be parallel to the longitudinal direction of the active region 115 to expose the device isolation region 113 between the active regions 115. The photoresist layer is selectively etched using a rectangular bridge removing mask (not shown) to form the photoresist pattern 125.

도 4c를 참조하면, 상기 감광막 패턴(125)을 식각마스크로 상기 제 1 층간 절연막(123)을 식각하여 상기 소자분리 영역(113)을 노출시킨다.Referring to FIG. 4C, the device isolation region 113 is exposed by etching the first interlayer insulating layer 123 using the photoresist pattern 125 as an etch mask.

이때, 상기 브릿지(123)가 제거되어 상기 랜딩 플러그(119)가 전기적으로 분리됨에 따라 소자 불량을 방지할 수 있다.In this case, as the bridge 123 is removed and the landing plug 119 is electrically disconnected, device failure may be prevented.

도 4d를 참조하면, 상기 감광막 패턴(125)을 제거하고, 전체 표면 상부에 제 2 층간 절연막(127)을 형성한다.Referring to FIG. 4D, the photoresist pattern 125 is removed, and a second interlayer insulating layer 127 is formed on the entire surface.

이때, 상기 제 2 층간 절연막(127)은 산화막으로 형성하는 것이 바람직하다.In this case, the second interlayer insulating film 127 may be formed of an oxide film.

여기서, 도 5에 도시된 바와 같이, 상기 제 2 층간 절연막(127)이 완전히 증착되지 못하여 보이드(void)가 생기는 경우에도 상기 랜딩 플러그(119)가 전기적으로 분리된 상태이므로, 소자에 영향을 끼치지 않아 소자 불량을 방지할 수 있다. Here, as shown in FIG. 5, the landing plug 119 is electrically disconnected even when the second interlayer insulating layer 127 is not completely deposited, thereby affecting the device. Device defects can be prevented.

이상에서 살펴본 바와 같이, 본 발명에 따른 반도체 소자의 제조방법은 랜딩 플러그 형성 공정 이후 브릿지 제거용 마스크를 이용한 사진 식각 공정으로 랜딩 플러그 사이의 층간 절연막을 식각함으로써 랜딩 플러그 간에 브릿지(bridge)를 제거하여 소자 불량을 방지할 수 있는 효과를 제공한다. As described above, the method of manufacturing a semiconductor device according to the present invention removes a bridge between landing plugs by etching an interlayer insulating film between landing plugs by a photolithography process using a mask for removing a bridge after the landing plug forming process. It provides an effect that can prevent device failure.

아울러 본 발명의 바람직한 실시예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.In addition, a preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (4)

(a) 소자분리 영역과 활성 영역이 구비된 반도체 기판 상부에 게이트를 형성하는 단계;(a) forming a gate over the semiconductor substrate including the device isolation region and the active region; (b) 상기 게이트 및 상기 반도체 기판 상에 제 1 층간절연막을 형성하는 단계;(b) forming a first interlayer insulating film on the gate and the semiconductor substrate; (c) 상기 제 1 층간절연막 상에 랜딩 플러그를 형성하는 단계;(c) forming a landing plug on the first interlayer insulating film; (d) 상기 소자분리 영역을 노출시키는 직사각형 형태의 감광막 패턴을 형성하는 단계; 및(d) forming a photoresist pattern having a rectangular shape exposing the device isolation region; And (e) 상기 감광막 패턴을 마스크로 상기 제 1 층간절연막을 식각하고, 상기 감광막 패턴을 제거하는 단계(e) etching the first interlayer insulating layer using the photoresist pattern as a mask and removing the photoresist pattern 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, 상기 (c) 단계는The method of claim 1, wherein step (c) 콘택 마스크를 이용하여 상기 제 1 층간 절연막을 선택적으로 식각하여 랜딩 플러그 콘택홀을 형성하는 단계;Selectively etching the first interlayer insulating layer using a contact mask to form a landing plug contact hole; 상기 랜딩 플러그 콘택홀을 포함한 상기 반도체 기판 상에 랜딩 플러그용 폴리실리콘막을 형성하는 단계; 및Forming a polysilicon film for a landing plug on the semiconductor substrate including the landing plug contact hole; And 상기 제 1 층간 절연막을 식각하여 상기 랜딩 플러그를 형성하는 단계Etching the first interlayer insulating film to form the landing plug 를 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.Method of manufacturing a semiconductor device comprising a. 제 1 항에 있어서, 상기 (e) 단계 이후 전체 표면 상부에 제 2 층간 절연막을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 1, further comprising forming a second insulating interlayer on the entire surface after the step (e). 제 3 항에 있어서, 상기 제 2 층간 절연막은 산화막으로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.The method of claim 3, wherein the second interlayer insulating film is formed of an oxide film.
KR1020060040462A 2006-05-04 2006-05-04 Manufacturing method of semiconductor device Withdrawn KR20070107903A (en)

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