KR20070094263A - Liquid crystal display - Google Patents

Abstract

An LCD(Liquid Crystal Display) apparatus is provided to enable a gate driving unit to be cooled while a lower display panel in contact with a first metal is cooled and discharge heat emitted from a second metal through a hole, thereby preventing the threshold voltage of transistors forming the gate driving unit from being changed by cooling the gate driving unit in an aging test. An LCD(Liquid Crystal Display) apparatus(300) comprises the followings: a thin film display panel(100,200) which has plural pixels and a gate driving unit(400) for applying a gate signal to the pixels; a backlight unit(900) which is positioned under the thin film display panel; and a cooling unit(700) which is arranged between the thin film display panel and the backlight unit and positioned below the gate driving unit. The cooling unit includes a first to a third metal, a P-type semiconductor positioned between the first metal and the second metal, and an N-type semiconductor positioned between the second metal and the third metal.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

With reference to the accompanying drawings will be described in detail the embodiments of the present invention to make the present invention clear.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel of a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention.

FIG. 4 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG.

5 is a signal waveform diagram of the gate driver illustrated in FIG. 3.

6 is a schematic layout view of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view of the liquid crystal display of FIG. 6 taken along the line VII-VII. FIG.

FIG. 8 is an enlarged view of a portion of the liquid crystal display shown in FIG. 7.

FIG. 9 is a diagram illustrating the flow of current in the liquid crystal display shown in FIG. 8.

The present invention relates to a liquid crystal display device.

Recently, organic light emitting display (OLED), plasma display panel (PDP), and liquid crystal display (LCD) are substituted for heavy and large cathode ray tube (CRT). Flat panel display devices such as are being actively developed.

PDP is a device that displays characters or images using plasma generated by gas discharge, and OLED displays characters or images by using electroluminescence of specific organic materials or polymers. The liquid crystal display device applies an electric field to a liquid crystal layer interposed between two display panels, and adjusts the intensity of the electric field to adjust a transmittance of light passing through the liquid crystal layer to obtain a desired image.

Among such flat panel display devices, for example, a liquid crystal display includes a display panel including a pixel including a switching element and a display signal line, and a gate driver to turn on / off the switching element of the pixel by sending a gate signal to a gate line among the display signal lines; That is, it includes a shift register.

The shift register includes a plurality of stages connected to each other, and each stage includes a plurality of transistors.

Meanwhile, the liquid crystal display undergoes an aging test that applies a voltage higher or lower than the normal driving voltage in the final inspection step. In this case, when the shift register is integrated in the liquid crystal display, the threshold voltage of the transistor may change due to heat generated during the aging test process.

Accordingly, an object of the present invention is to provide a liquid crystal display device capable of reducing heat generated during an aging test process.

According to an aspect of the present invention, a liquid crystal display device includes a thin film display panel including a plurality of pixels and a gate driver configured to apply a gate signal to the pixels, a backlight unit disposed below the thin film display panel; And a cooling unit disposed between the thin film display panel and the backlight unit and positioned below the gate driver.

The cooling unit may include first to third metals, a P-type semiconductor positioned between the first metal and the second metal, and an N-type semiconductor positioned between the second metal and the third metal.

The gate driver may be integrated in the thin film panel.

The gate driver may include a stage generating the gate signal in synchronization with one of a plurality of clock signals.

In this case, one of the clock signals may be applied to the first metal, and the third metal may be connected to a ground voltage. Furthermore, a plurality of holes may be formed along the gate driver in a side of the gate driver in the backlight unit. It may be formed.

The pixel may include a switching element that operates according to the gate signal, and the switching element may be made of amorphous silicon.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, and a data driver 500 connected thereto. The gray voltage generator 800 connected to the signal generator 500 and a signal controller 600 for controlling the gray voltage generator 800 are included.

The liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _n , D ₁ -D _m and a plurality of pixels PX connected to the plurality of signal lines G ₁ -G _n , D ₁ -D _m , and arranged in a substantially matrix form. Include. On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _n and D ₁ -D _m are a plurality of gate lines G ₁ -G _n for transmitting a gate signal (also called a “scan signal”) and a plurality of data lines for transmitting a data signal ( D ₁ -D _m ). The gate lines G ₁ -G _n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and are substantially parallel to each other.

Each pixel PX, for example, the pixel PX connected to the i-th (i = 1, 2,, n) gate line G _i and the j-th (j = 1, 2,, m) data line Dj. ) Includes a switching element Q connected to the signal line G _i D _j , a liquid crystal capacitor Clc, and a storage capacitor Cst connected thereto. Holding capacitor Cst can be omitted as needed.

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

The storage capacitor Cst, which serves as an auxiliary part of the liquid crystal capacitor Clc, is formed by overlapping a separate signal line (not shown) and the pixel electrode 191 provided on the lower panel 100 with an insulator interposed therebetween. A predetermined voltage such as the common voltage Vcom is applied to the separate signal line. However, the storage capacitor Cst may be formed such that the pixel electrode 191 overlaps the front gate line directly above the insulator.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike FIG. 2, the color filter 230 may be formed above or below the pixel electrode 191 of the lower panel 100.

At least one polarizer (not shown) for polarizing light is attached to an outer surface of the liquid crystal panel assembly 300.

Referring back to FIG. 1, the gray voltage generator 800 generates two sets of gray voltage sets (or reference gray voltage sets) related to the transmittance of the pixel PX. One of the two sets has a positive value for the common voltage Vcom and the other set has a negative value.

The gate driver 400 is formed in the same process as the switching element Q of the pixel PX and integrated in the liquid crystal panel assembly 300, and may include gate lines G ₁ -G _n of the liquid crystal panel assembly 300. The gate signal connected to the gate line G ₁ -G _{n is} connected to the gate signal G _{1 through} G _n .

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300 and selects a gray voltage from the gray voltage generator 800 and uses the data line D ₁ as a data signal. -D _m ). However, when the gray voltage generator 800 provides only a predetermined number of reference gray voltages instead of providing all of the voltages for all grays, the data driver 500 divides the reference gray voltages to divide the gray voltages for all grays. Generate and select the data signal from it.

The signal controller 600 controls the gate driver 400, the data driver 500, and the like.

Each of the driving devices 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown). And attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, these driving devices 500, 600, and 800 may be integrated in the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _n , D ₁ -D _m , and the thin film transistor switching element Q. . In addition, the driving devices 400, 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1 and the data control signal CONT2, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal DAT are transmitted to the data driver 500. Export to).

The gate control signal CONT1 includes a scan start signal STV indicating a scan start and at least one clock signal controlling an output period of the gate-on voltage Von. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 is a load for applying a data signal to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of image data transmission for the pixels PX in one row [bundling]. Signal LOAD and data clock signal HCLK. The data control signal CONT2 is also an inverted signal that inverts the voltage polarity of the data signal relative to the common voltage Vcom (hereinafter referred to as " polarity of the data signal " by reducing the " voltage polarity of the data signal for the common voltage ") RVS) may be further included.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixels PX in one row (bundling), and each digital image signal DAT. By converting the digital image signal DAT into an analog data signal by selecting a gray scale voltage corresponding to), it is applied to the corresponding data lines D ₁ -D _m .

The gate driver 400 applies the gate-on voltage Von to the gate lines G ₁ -G _n in response to the gate control signal CONT1 from the signal controller 600, thereby applying the gate lines G ₁ -G _n . Turn on the switching element (Q) connected to. Then, the data signal applied to the data lines D ₁ -D _m is applied to the pixel PX through the switching element Q turned on.

The difference between the voltage of the data signal applied to the pixel PX and the common voltage Vcom is shown as the charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. The change in polarization is represented by a change in transmittance of light by a polarizer attached to the display panel assembly 300.

This process is repeated in units of one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), thereby all the gate lines G ₁ -G _n. ), The gate-on voltage Von is sequentially applied to the data signal to all the pixels PX, thereby displaying an image of one frame.

When one frame ends, the state of the inversion signal RVS applied to the data driver 500 is controlled so that the next frame starts and the polarity of the data signal applied to each pixel PX is opposite to the polarity of the previous frame. "Invert frame"). In this case, the polarity of the data signal flowing through one data line is changed (eg, row inversion and point inversion) or the polarity of the data signal applied to one pixel row is different depending on the characteristics of the inversion signal RVS within one frame. (E.g. column inversion, point inversion).

Next, the gate driver of the liquid crystal display according to the exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 3 to 5.

3 is a block diagram of a gate driver according to an exemplary embodiment of the present invention. FIG. 4 is an example of a circuit diagram of the j-th stage of the shift register for gate driver shown in FIG. 3, and FIG. 5 is a signal waveform diagram of the gate driver shown in FIG.

The gate driver 400 shown in FIG. 3 is a shift register including a plurality of stages 410 arranged in a line and connected to the gate lines G ₁ -G _n , respectively, and include a scan start signal STV, The initialization signal INT, the plurality of clock signals CLK1 and CLK2 and the gate off voltage Voff are input. An NMOS transistor T14 is connected to the end of each gate line G ₁ -G _n , and a gate off voltage Voff is input.

Each stage 410 includes a set terminal S, a gate voltage terminal GV, a pair of clock terminals CK1 and CK2, a reset terminal R, a frame reset terminal FR, and a gate output terminal ( OUT1) and carry output terminal OUT2. However, the dummy dummy stage does not have the reset terminal R and the frame reset terminal FR.

Each stage, for example, the j-th stage (ST _j) the set terminal (S), the carry output of the front end stage (ST _j-1), i.e. shear carry output [Cout (j-1)] is a reset terminal ( The gate output of the rear stage ST _{j + 1} , that is, the rear gate output Gout (j + 1) is input to R, and the clock signals CLK1 and CLK2 are input to the clock terminals CK1 and CK2. The gate off voltage Voff is input to the gate voltage terminal GV. The gate output terminal OUT1 outputs the gate output Gout (j) and the carry output terminal OUT2 outputs the carry output Cout (j).

However, the scan start signal STV is input to the first stage of the shift register 400 instead of the front carry output. Further, when the clock signal CLK1 is input to the clock terminal CK1 of the j-th stage ST _j and the clock signal CLK2 is input to the clock terminal CK2, the (j-1) th and (j) adjacent thereto are The clock signal CLK2 is input to the clock terminal CK1 of the ₊ 1th stage ST _j-1 and ST _{j + 1} , and the clock signal CLK1 is input to the clock terminal CK2.

Each clock signal CLK1 and CLK2 is equal to the gate-on voltage Von when the voltage level is high and the gate-off voltage Voff when the voltage level is high so as to drive the switching element Q of the pixel. Do. As shown in FIG. 5, each clock signal CLK1 and CLK2 may have a duty ratio of 50%, and a phase difference between the two clock signals CLK1 and CLK2 may be 180 °.

Referring to FIG. 4, each stage of the gate driver 400 according to an embodiment of the present invention, for example, the j th stage, includes the input unit 420, the pull-up driver 430, And a pull-down driver 440 and an output unit 450. These include at least one NMOS transistor T1-T15, and the pull-up driver 430 and the output unit 450 further include capacitors C1-C3. However, PMOS transistors may be used instead of NMOS transistors. In addition, the capacitors C1-C3 may actually be parasitic capacitances between the gate and the drain / source formed during the process.

The input unit 420 includes three transistors T11, T10, and T5 connected in series to the set terminal S and the gate voltage terminal GV. Gates of the transistors T11 and T5 are connected to the clock terminal CK2, and gates of the transistor T5 are connected to the clock terminal CK1. The contact between the transistor T11 and the transistor T10 is connected to the contact J1, and the contact between the transistor T10 and the transistor T11 is connected to the contact J2.

The pull-up driving unit 430 includes a transistor T4 connected between the set terminal S and the contact J1, a transistor T12 connected between the clock terminal CK1 and the contact J3, and a clock terminal. And a transistor T7 connected between the CK1 and the contact J4. The gate and the drain of the transistor T4 are commonly connected to the set terminal S, the source is connected to the contact J1, and the gate and the drain of the transistor T12 are commonly connected to the clock terminal CK1. And the source is connected to contact J3. The gate of the transistor T7 is connected to the contact J3 and at the same time connected to the clock terminal CK1 through the capacitor C1, the drain is connected to the clock terminal CK1, the source is connected to the contact J4. , Capacitor C2 is connected between contact J3 and contact J4.

The pull-down driver 440 receives the gate-off voltage Voff through a source and outputs the transistors T6, T9, T13, T8, T3, and T2 through the drain to the contacts J1, J2, J3, and J4. It includes. The gate of the transistor T6 is connected to the frame reset terminal FR, the drain is connected to the contact J1, the gate of the transistor T9 is connected to the reset terminal R, and the drain is connected to the contact J1. The gates of the transistors T13 and T8 are commonly connected to the contact J2, and the drains are connected to the contacts J3 and J4, respectively. The gate of the transistor T3 is connected to the contact J4, the gate of the transistor T2 is connected to the reset terminal R, and the drains of the two transistors T3 and T2 are connected to the contact J2.

The output unit 450 includes a pair of transistors T1 and T15 having a drain and a source connected between the clock terminal CK1 and the output terminals OUT1 and OUT2 and a gate connected to the contact J1, respectively. And a capacitor C3 connected between the gate and the drain of T1, that is, between the contact J1 and the contact J2. The source of transistor T1 is also connected to contact J2.

The operation of such a stage will now be described.

For convenience of explanation, the voltage corresponding to the high level of the clock signals CLK1 and CLK2 is referred to as a high voltage, and the magnitude of the voltage corresponding to the low level of the clock signals CLK1 and CLK2 is equal to the gate-off voltage Voff. This is called low voltage.

First, when the clock signal CLK2 and the front carry output Cout (j-1) become high, the transistors T11 and T5 and the transistor T4 are turned on. Then, the two transistors T11 and T4 transfer a high voltage to the contact J1, and the transistor T5 transfers a low voltage to the contact J2. As a result, the transistors T1 and T15 are turned on so that the clock signal CLK1 is output to the output terminals OUT1 and OUT2. At this time, since the voltage of the contact J2 and the clock signal CLK1 are both low voltages, the output voltage [ Gout (j) and Cout (j)] become low voltage. At the same time, the capacitor C3 charges a voltage having a magnitude corresponding to the difference between the high voltage and the low voltage.

At this time, since the clock signal CLK1 and the rear gate output Gout (j + 1) are low and the contact J2 is also low, the transistors T10, T9, T12, T13, T8, and T2 connected to the gate are connected. ) Are all off.

Subsequently, when the clock signal CLK2 becomes low, the transistors T11 and T5 are turned off. At the same time, when the clock signal CLK1 becomes high, the output voltage of the transistor T1 and the voltage of the contact J2 become high. do. At this time, a high voltage is applied to the gate of the transistor T10, but since the potential of the source connected to the contact J2 is also the same high voltage, the potential difference between the gate sources becomes zero, so that the transistor T10 remains turned off. . Thus, the contact J1 is in a floating state, whereby the potential is further increased by the high voltage by the capacitor C3.

On the other hand, since the potentials of the clock signal CLK1 and the contact J2 are high voltage, the transistors T12, T13, and T8 are turned on. In this state, the transistor T12 and the transistor T13 are connected in series between the high voltage and the low voltage, so that the potential of the contact J3 is divided by the resistance value of the resistance state at the turn-on of the two transistors T12 and T13. Voltage value. However, assuming that the resistance value of the resistance state at the turn-on of the two transistors T13 is set to be very large compared to the resistance value of the resistance state at the turn-on of the transistor T12, for example, about 10,000 times, the voltage of the contact J3 is a high voltage. Is almost the same as Accordingly, the transistor T7 is turned on and connected in series with the transistor T8, so that the potential of the contact J4 is divided by the resistance value of the resistance state at the turn-on of the two transistors T7 and T8. Have At this time, if the resistance values of the resistance states of the two transistors T7 and T8 are set to be almost the same, the potential of the contact J4 has an intermediate value between the high voltage and the low voltage, whereby the transistor T3 is turned off. Keep it. At this time, since the rear gate output Gout (j + 1) is still low, the transistors T9 and T2 also remain turned off. Therefore, the output terminals OUT1 and OUT2 are connected only to the clock signal CLK1 and cut off from the low voltage to emit a high voltage.

On the other hand, the capacitor C1 and the capacitor C2 charge voltages corresponding to the potential difference between both ends, respectively, and the voltage of the contact J3 is lower than the voltage of the contact J5.

Subsequently, when the rear gate output Gout (j + 1) and the clock signal CLK2 go high and the clock signal CLK1 goes low, the transistors T9 and T2 are turned on to low voltage to the contacts J1 and J2. To pass. At this time, the voltage of the contact J1 falls to the low voltage while the capacitor C3 discharges, but it takes some time to completely lower to the low voltage due to the discharge time of the capacitor C3. Accordingly, the two transistors T1 and T15 remain turned on for a while even after the rear gate output Gout (j + 1) becomes high, whereby the output terminals OUT1 and OUT2 are connected to the clock signal CLK1. To emit low voltage. Subsequently, when the capacitor C3 is completely discharged and the potential of the contact J1 reaches a low voltage, the transistor T15 is turned off and the output terminal OUT2 is cut off from the clock signal CLK1, so that the carry output Cout (j) is performed. Becomes floating and maintains low voltage. At the same time, the output terminal OUT1 is continuously connected to the low voltage through the transistor T2 even when the transistor T1 is turned off, thereby continuously outputting the low voltage. At this time, the gate output Gout (j + 1) of the rear stage ST _{j + 1} is applied to the transistor T14 connected to the front gate line G _j so that the transistor T14 is turned on, thereby turning off the gate. The voltage Voff is output to the gate line G _j . The gate line G _j is then fixed once more with a low voltage.

On the other hand, since the transistors T12 and T13 are turned off, the contact J3 is in a floating state. In addition, the voltage of the contact J5 is lower than the voltage of the contact J4. The transistor T7 is turned off because the voltage of the contact J3 is kept lower than the voltage of the contact J5 by the capacitor C1. . At the same time, since the transistor T8 is also turned off, the voltage at the contact J4 is lowered by that amount, so that the transistor T3 also remains turned off. In addition, the transistor T10 maintains the turn-off state because the gate is connected to the low voltage of the clock signal CLK1 and the voltage of the contact J2 is also low.

Next, when the clock signal CLK1 becomes high, the transistors T12 and T7 turn on, the voltage of the contact J4 rises, turns on the transistor T3, and transfers a low voltage to the contact J2. ) Continues to emit low voltage. That is, even if the rear gate output Gout (j + 1) has a low output, the voltage of the contact J2 can be made low.

Meanwhile, since the gate of the transistor T10 is connected to the high voltage of the clock signal CLK1 and the voltage of the contact J2 is a low voltage, the gate of the transistor T10 is turned on to transfer the low voltage of the contact J2 to the contact J1. On the other hand, the clock terminal CK1 is connected to the drains of the two transistors T1 and T15 so that the clock signal CLK1 is continuously applied. In particular, the transistor T1 is made relatively larger than the rest of the transistors, so that the parasitic capacitance between gate drains is large, so that the voltage change of the drain may affect the gate voltage. Therefore, when the clock signal CLK1 becomes high, the gate voltage may increase due to the parasitic capacitance between the gate and drain gates, thereby turning on the transistor T1. Therefore, the low voltage of the contact J2 is transferred to the contact J1 to maintain the gate voltage of the transistor T1 at a low voltage, thereby preventing the transistor T1 from turning on.

Thereafter, the voltage at the contact J1 maintains a low voltage until the front carry output Cout (j-1) becomes high, and the voltage at the contact J2 has the clock signal CLK1 high and the clock signal CLK2. Is low, the low voltage is maintained through the transistor T3, and vice versa, the low voltage is maintained through the transistor T5.

On the other hand, the transistor T6 receives the initialization signal INT generated in the last dummy stage ST _{n + 1} and transfers the gate-off voltage Voff to the contact J1 to transfer the voltage of the contact J1 once more. Set to low voltage.

In this manner, the stage 410 is based on the front carry signal Cout (j-1) and the back gate signal Gout (j + 1) and is synchronized with the clock signals CLK1 and CLK2 to carry the carry signal Cout ( j)] and the gate signal Gout (j).

Next, the liquid crystal display according to the exemplary embodiment of the present invention will be described in more detail with reference to FIGS. 6 to 9.

FIG. 6 is a schematic layout view of the liquid crystal display shown in FIG. 1, and FIG. 7 is a cross-sectional view of the liquid crystal display of FIG. 6 taken along the line VII-VII, and FIG. 8 is a liquid crystal display shown in FIG. 7. 9 is an enlarged view of a portion, and FIG. 9 is a diagram illustrating a current flow in the liquid crystal display shown in FIG. 8.

Referring to FIG. 6, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a flexible printed circuit film 510 and a flexible printed circuit film connected thereto. A plurality of data driver integrated circuits 540 mounted on the 510, and a printed circuit board 550 connected to the edge of the flexible printed circuit film 510.

In addition, as described above, the gate driver 400 is integrated outside the display area D of the liquid crystal panel assembly 300.

A backlight unit 900 that provides light to the liquid crystal panel assembly 300 is positioned below the lower panel 200, and a cooling unit 700 is disposed between the lower panel 200 and the backlight unit 900. Along the line 400 in the longitudinal direction. In addition, holes H are formed in the lower backlight unit 900 of the cooling unit 700, and a plurality of holes H are formed at predetermined intervals along the gate driver 400 in the vertical direction.

In the cooling unit 700, first to third metals 701, 702, and 703 are positioned below the lower panel 200 and above the backlight unit 900, respectively, and the first metal 701 and the second metal. The P-type semiconductor P and the N-type semiconductor N are disposed between the metal 702 and between the third metal 703 and the second metal 702, respectively. In addition, the first metal 701 and the third metal 703 are separated from each other.

When the first metal 701 is connected to a constant power source and the third metal 703 is connected to the ground voltage, current flows to the first to third metals 701, 702, and 703.

For example, when the clock signal CLK1 described above is applied to the first metal 701, a closed circuit is formed to flow a current along the path a shown by an arrow in FIG. 9.

Accordingly, an endothermic reaction occurs in the first metal 701 and an exothermic reaction occurs in the second metal 702, thereby cooling the lower panel 200. As is known, this is a Peltier effect. When a current flows between different types of semiconductors, heat is transferred from the first metal 701 to transfer holes of the P-type semiconductor to the N-type semiconductor. 2 because it is transferred to the metal 702. As a result, the lower panel 200 which is in contact with the first metal 710 is cooled, and the gate driver 400 thereon is also cooled, and the heat emitted from the second metal 702 is discharged through the hole H. Discharged.

In this manner, when the gate driver 400 is cooled during the aging test, the threshold voltage of the transistors TR1-TR14 constituting the gate driver 400 may be prevented from changing.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (7)

A thin film display panel including a plurality of pixels and a gate driver configured to apply a gate signal to the pixels; A backlight unit disposed below the thin film display panel, and A cooling unit disposed between the thin film panel and the backlight unit and positioned under the gate driver Liquid crystal display comprising a. In claim 1, The cooling unit includes first to third metals, a P-type semiconductor positioned between the first metal and the second metal, and an N-type semiconductor positioned between the second metal and the third metal. In claim 2, And the gate driver is integrated in the thin film display panel. In claim 3, And the gate driver includes a stage configured to generate the gate signal in synchronization with one of a plurality of clock signals. In claim 4, One of the clock signals is applied to the first metal, and the third metal is connected to a ground voltage. In claim 5, And a plurality of holes formed in the backlight unit along the gate driver in the side where the gate driver is located. In claim 6, The pixel includes a switching element that operates according to the gate signal, The switching element is made of amorphous silicon Liquid crystal display.

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