KR20070090251A - Formation and treatment of a sige structure - Google Patents

Abstract

The invention relates to a method for forming a structure (30) provide with a layer (2) removed from a donor plate (10) comprising, prior to removal, a first Si1-xGex layer (1) and a second layer (2) placed on the first Si1-yGey layer (1) (x and y ranges, respectively, from 0 to 1, and x differs from y). The inventive method consists: a) in implanting atomic species in such a way that an embrittlement area (4) under the second (2), b) in gluing the donor plate (10) to a receiving plate (20), c) in heating for detaching the removed layers (1', 2) from the donor plate (10) in the embrittlement area (4), d) in carrying out a rapid thermal annealing (also called RAT) at a temperature equal to or greater than about 1000 °C for a time equal to or less than 5 minutes and e) in selectively etching the remaining part of the first layer (1') in front of the second layer (2).

Description

Formation and processing method of silicon structure {FORMATION AND TREATMENT OF A SiGe STRUCTURE}

The present invention provides a structure manufacturing method comprising a removing layer of a semiconductor material taken from a donor wafer, wherein the donor wafer is formed of Si _{1 - x} Ge _x before the removal, and Si _{1 - y} on the first layer. Is composed of a second layer of Ge _y ( x , y each ranging from 0 to 1, where x is different from y ),

a) implanting the atomic species to form a weak region below the second layer;

b) donor wafer and receiving wafer bonding step;

c) providing thermal and / or mechanical energy to detach the removal layer from the donor wafer in the weak region;

d) The removal layer treatment step relates to a method that is configured continuously.

Layer removal uses Smart-Cut® techniques known to those skilled in the art. One example of applying this removal method is described in US document US2004 / 0053477, where the crystallographic structure of the second layer is elastically deformed by the first layer structure.

Step d) for the removal layers treatment should be implemented to remove the defective area and to reduce the surface roughness mainly generated in the steps a) and c). The defect area thickness is typically 150 nanometers (nm) for hydrogen atom implants.

By way of example, mechanical polishing or chemical-mechanical planarization (CMP, chemical mechanical polishing) may be performed to remove surface roughness, and / or sacrificially osidizing steps of the defect area may be performed.

Bond according to step b) is therefore carried out by the conventional elastic insulating material, Si on the insulating structure _{1-semiconductors,} such as Ge _{y y} - _{- On-x} Ge _x / Si ₁ the insulation structure can be obtained.

As disclosed in US2004 / 0053477, a subsequent step in step d) may be carried out to remove the remaining portion of the first layer, thus allowing only the second layer to remain on the receiving wafer. Thus, Si _{1 - y} Ge _y on the insulating structure can be produced.

The first layer remainder removal operation can be effectively performed by selective chemical etching with a suitable etchant. Selective chemical etching can ultimately produce the desired layer with good surface quality and without great risk of damaging it (which can occur if a single polishing is performed).

However, selective chemical etching requires pretreatment of the etch surface, and typically mechanical polishing means are used. Pretreatment for such etching is necessary to reduce severe roughness, which in turn causes locally over-uniform etching, which creates through defects or holes in the second layer.

However, continuous polishing and chemical etching operations are intended to make the post-desorption termination step long, complex and economically expensive (as well as the overall removal procedure).

In addition, chemical etching in some cases leads to at least partially non-bonding problems of the bonding interface. In particular, the bonding layer face can delaminate, ie attack the layer, thereby cropping out of the resulting structure face. Examples that may be mentioned are HF treatment of sSOI (insulator phase strained silicon) structures composed of SiO ₂ buried under strained Si, or H2O2: HF: HAc (HAc) of sSi / SiGeOI (insulator phase SiGe phase strained silicon) structures. Is an acetic acid abbreviation), wherein the SiGe and buried SiO ₂ layers are easy to etch under the strained Si layer.

Thus, considering the final product quality, the results obtained are not satisfactory.

Another way to overcome this problem is to dilute the etchant to better control these actions. However, this solution is not satisfactory because it substantially prolongs the procedure time and does not completely solve the delamination problem.

Another solution that can be considered is to reinforce the bonding interface prior to etching so that the interface is more resistant to chemicals. For this purpose, post-desorption stable heat treatment may be considered for several hours at about 1000 ° C. or higher.

However, SOI (silicon on insulator) in the manufacture of such a solution is known, Si _{1 -} is not appropriate in heterogeneous layers transition of _y Ge _{y - x} Ge _x and Si _1. In fact, this heat treatment diffuses Ge from the layer with the highest Ge content to the layer with the lowest Ge content, so that the Ge content is homogenized across the two layers so that the physical and electrical properties of these two layers are no longer differentiated. It may not be.

If the two layers are substantially the same, subsequent etching is no longer optional.

In addition, it is often desirable to prevent any diffusion from one layer to another. This is especially the case when the second layer is strained Si (ie y = 0) and the final sSOI structure is obtained to fully enjoy the electrical properties (ie improved particle mobility) of the structure.

Thus, due to Ge diffusion from one layer to the other layer (the diffusion typically starts at about 800 ° C.), the temperature treatment is limited, so the low temperature reinforcement is only partial. Thus, the problem of delamination still exists.

One object of the present invention is to avoid delamination at the side of the bonding layer when performing a final chemical etch.

Another object of the present invention is to reduce the running time, the economic cost and the number of treatments after step c) performed on the removal layer, in particular to eliminate the use of mechanical polishing.

Another object of the present invention is to fabricate a structure, such as a semiconductor-on-insulator structure, consisting of a removal layer comprising a material that is less stable than Si, such as strained Si or SiGe.

Another object of the present invention is to reduce the material content sacrificed during the removal layer treatment.

Another object of the present invention is to propose a simple removal layer treatment method which can be easily integrated with the overall removal method applying Smart-Cut ^® technology.

In order to solve these problems, the present invention provides, in a first aspect, a structure manufacturing method comprising a removing layer of semiconductor material taken from a donor wafer, wherein the donor wafer is formed of Si _{1 - x} Ge _x before the removal. A second layer of Si _{1 - y} Ge _y on the first layer and the first layer ( x , y each range from 0 to 1, x being different from y ),

a) implanting the atomic species to form a weak region below the second layer;

b) donor wafer and receiving wafer bonding step;

c) providing thermal and / or mechanical energy to detach the removal layer from the donor wafer in the weak region;

d) a rapid thermal annealing (RTA) step performed at a temperature of about 1000 ° C. or higher for no more than 5 minutes;

e) The selective etching of the remaining portion of the first layer opposite the second layer relates to a method in which it is continuously configured.

Other possible features of the present invention are as follows:

Step d) proceeds for about 10 seconds to about 30 seconds at a temperature in the range from about 1000 ° C to about 1200 ° C;

Step d) proceeds at about 1100 ° C. for about 10 seconds;

Step d) proceeds in a reducing atmosphere;

Step d) is carried out in a reducing atmosphere of argon and hydrogen or in an argon reducing atmosphere;

Sacrificial oxidation of the first layer proceeds between steps c) and d);

Plasma activation of at least one bonding surface proceeds before step b);

Heat treatment of at least about 30 minutes to reinforce the bond also proceeds after step b);

The atomic species implanted during step a) consists of a single atomic component;

The atomic species implanted during step a) consists of two distinct atomic components, thus step a) constitutes a co-implant;

After step c) no mechanical polishing is performed;

After step e) comprising Si _{1 - y} Ge _y crystal growth on the second layer to thicken the second layer;

And the second layer is elastically deformed ₁ Si _- is formed in a _y Ge _y;

And Si donor wafer ₁ on the second _layer and a third layer of Ge _{x x,} and;

The donor wafer consists of a multi-layer structure comprising a support substrate formed of bulk Si, a SiGe buffer structure and first layers of Si _{1 - x} Ge _x and a second layer of alternating strain Si _{1 - y} Ge _y Multiple removals from the wafer are possible;

The strained Si _{1 - y} Ge _y each layer is thicker than the critical balance thickness;

Prior to step b), further comprising forming a bonding layer on the donor wafer and / or the receiving wafer, wherein the bonding layer is electrically connected, for example SiO ₂ , Si ₃ N ₄ or Si _x O _y N _z. It consists of an insulating material.

According to a second aspect of the present invention, the present invention proposes to apply the structure forming method in the formation of a semiconductor-on-insulator structure.

The features, objects and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the method with reference to the accompanying drawings:

1a to 1f show steps according to the method according to the invention for forming a structure composed of layers removed by Smart-Cut ^® .

2A to 2B show a first modification of the present invention.

3A to 3B show a second modification of the present invention.

4 is a measurement result by secondary ion mass spectrometry to determine the germanium concentration in the strained silicon layer removed by the present invention, compared with the germanium concentration in (unstrained) Si calculated from the diffusion constants obtained from the literature do.

FIG. 5 shows a contrast study of germanium diffusion coefficients in an unmodified silicon layer and a strained silicon layer.

The following describes an embodiment of the method of the present invention and the application of the present invention, based on removal layers by Smart-Cut®, in particular Si and SiGe, formed of a Type IV material or alloy.

1A and 1E illustrate a first layer formed of Si _{1 - x} Ge _x (x∈ [0; 1]) and Si _{1 - y} Ge _y (to transfer from donor wafer 10 to receiving wafer 20 according to the present invention). The first method for removing the second layer formed by y∈ [0; 1]) is shown.

Figure 1a is removed Si _1-y Ge _y is showing the wear donor buffer 10 consisting of two layers 2 formed of _a-x Ge _x and Si 1, the first layer ₁ formed of a.

Typically, donor wafer 10 comprising Si _{1 - x} Ge _x comprises a bulk substrate 5 formed of Si on which a buffer structure of SiGe (not shown) made of other layers, for example, is formed upon crystal growth. In particular, in such a buffer structure, the Ge content may vary gradually from 0% on bulk substrates to about 100 kPa% at the boundary with one layer formed of Si _{1 - x} Ge _x (which is also preferably formed by crystal growth). Can be. The optional thickness of the Si _{1 - x} Ge _x layer can be, for example, about 1 micron.

The second layer of Si _{1 - y} Ge _y is formed on top of the first layer 1 formed of Si _{1 - x} Ge _x . In the first case, the second layer continues to grow at that position directly after the formation of the first layer 1. In the second case, the second layer 2 is grown after a short first layer 1 surface pretreatment step, for example CMP polishing.

Second layer 2 is advantageously formed by epitaxy growth applying known techniques such as CVD and MBE (chemical vapor deposition and molecular beam epitaxy). Therefore, Si _{0 .8} in the case of the second layer 2 formed of a Ge _{0 .2} first layer 1 and modifications (strained) Si (i.e., y = 0) formed of about 100 ohms is strong thickness (Å) to about 800Å A second layer having a range can be formed.

If the silicon concentrations of the two layers 1 and 2 are different, the second layer 2 is deformed by the first layer 1 so that the lattice factor is substantially the same as that of the growth substrate, and internal elastic deformation is imparted. The internal deformation is extensible if the silicon content in the second layer 2 alloy is greater than that of the first layer and vice versa. A fairly thin second layer 2 should be formed: too thick a layer above the critical balance thickness will cause strain relaxation in the thickness layer of the film towards the Si _{1 - y} Ge _y nominal lattice factor and / or cause defects to occur. Can be. Regarding this subject, reference may be made to Fridedrich Schaffler, Semiconductor Technology, 12 (1997) 1515-1549 entitled 'High Mobility Si and Ge Structures'.

However, in the special case of depositing the modifying material at very low temperatures, it will be possible to form the deformed second layer 2 of thickness greater than the critical balance thickness (discussed below).

Referring to FIG. 1B, the weak region 4 is formed under the donor wafer 10 second layer 2. In particular, the implant is Si _{1 -} may be formed on the first layer of Ge _{x x} (Fig. 1b being shown).

The fragile region 4 is formed by implanting atomic species, and the depth and fragility of the implant are determined by the dose, the nature and the energy. In particular, the implant energy is adjusted such that a weak region is formed below the second layer 2. In the case of a first layer 1 having a thickness of about 0.5 micrometers or more and a second layer 2 having a thickness of about 100 microns to about 800 microns, for example about 200 microns, the soft area 4 is between about 1500 microns and about 3000 microns, More specifically, it may be formed to about 2000 kPa.

For example, the 20 kilo electron volts (Kev) to the energy and 3x10 ¹⁶ atoms of 80KV / cm ² to about 10x10 dose of ¹⁶ atoms / cm ^2, preferably from about 30KeV and energy of about 6x10 ¹⁶ atoms / cm ² It is possible to implant hydrogen species at a dose. Implant depths on the order of 1000 mm to 5000 mm are obtained.

Optionally, the factors that determine the implant atomic species are adjusted to minimize the roughness that appears in the soft zone 4 after detachment. In fact, the degree of post-detachment roughness is partially related to these factors. Thus, it is possible to select co-plants of atomic species such as hydrogen and helium or argon or other inert gases. In the case of co-implants, it can be seen that the soft zone 4 is thinner than in the case of simple implants (for details see especially FR 04/09980).

With energy of about 1 × 10 ¹⁶ / cm ^{2 in the} range of 20 KeV to 80KeV and about 1 × 10 ¹⁶ / cm ² hydrogen co-implant with energy in the range of 20KeV to 80KeV, an implant depth of about 1000 kV to 5000 kW can be obtained.

Referring to FIG. 1C, a bonding step between the receiving wafer 20 and the donor wafer 10 surface containing the implant is performed.

The receiving wafer 20 may be made of bulk Si or other materials.

Prior to the bonding step, a bonding layer, for example a layer consisting of SiO ₂ , Si ₃ N ₄ , Si _x O _y N _z , may be formed on each one and / or other surface to which it is bonded. Such a bonding layer formation technique may be a laminate in order to avoid deterioration of the second layer deformation or consequently diffusion in the first layer.

Optionally, at least one of the surfaces to be bonded prior to contacting the receiving wafer 20 and the donor wafer 10 may be pretreated, for example with SC1 and SC2 solutions, ozone-containing solutions, or other surface cleaning and pretreatment techniques.

The binding itself is performed by molecular bonding primarily due to the hydrophilic nature of each of the surfaces to which it is bound.

It is also possible to carry out plasma activation on one or both bonding surfaces immediately before bonding, which in principle allows future bonding interfaces to be reinforced without high temperature heat treatment. In particular, plasma activation is performed and finally after binding and removal, the binding energy is about 0.8 joules per square meter (J / m ² ) or more. For example, the plasma can be obtained from an inert gas such as Ar or N ₂ or an oxidizing gas such as O ₂ .

Optionally, a low temperature annealing heat treatment (800 ° C. or less) is performed prior to bonding, so that the bonding interface can be further reinforced.

FIG. 1D provides thermal and / or mechanical energy to break weak bonds in weak region 4, thus providing donor wafer 10 with a first portion 10 'and a first layer comprising the first layer remaining portion 1 ". The removal layer detachment in the soft zone 4, which is desorbed to the second portion 30, including another portion 1 ', is shown.The thermal energy causes a thermal effect on the gas species enclosed in the soft zone 4, thus causing weak bond breakage. cause.

Desorption can be performed for a long time or for a short time depending on whether the temperature is low or high at a temperature of about 300 ° C to about 600 ° C.

For example, in the removal layer formed of Si _{1 - x} Ge _x and Si _{1 - y} Ge _y , 2 to 15 minutes to 30 minutes at a temperature of about 500 ° C. to about 600 ° C., more preferably at 600 ° C. Heat treatment may be performed for a time.

If the detachment is performed only by heat treatment, the detachment may occur without necessarily having to reverse the contact of the remaining donor wafer 10 '.

In this case, and optionally, a new heat treatment can be performed after the desorption step, without the need for additional wafers and additional operations requiring a suitable device, without having to remove the wafers from the furnace (where the desorption heat treatment has been performed). In addition, the donor wafer remaining portion 10 'protects the first and second layers 1' and 2 that are removed from possible contaminants, oxidants, or other species, and enables new heat treatment in other atmospheres.

Heat treatment may also be performed after the wafers have been physically separated (and after exiting the tally furnace). The heat treatment may be performed in addition to or in place of plasma activation performed prior to bonding. In all cases, the heat treatment for reinforcing bonding interface 6 is at a temperature in the range from about 350 ° C. to about 800 ° C., in particular at about 350 ° C. to about 700 ° C., more preferably at about 600 ° C., from about 30 minutes to about 4 It may be performed for a time, and thus may be performed so that the bond is sufficiently strengthened (and thus avoids the risk of side delaminating during selective etching performed after removal).

According to the present invention, subsequent to desorption, rapid thermal annealing (RTA) is performed at a temperature of 1000 ° C. or higher, for a time not exceeding about 5 minutes, with or without a step prior to bonding interface reinforcement.

The RTA is preferably carried out in a reducing atmosphere such as argon and hydrogen or argon alone.

For example, the RTA may be performed at about 1000 ° C. and about 1200 ° C. for about 10 seconds to about 30 seconds, preferably at about 1100 ° C. for about 10 seconds.

The temperature above 1000 ° C. or higher is not the usual temperature applied when two layers 1 and 2 with different Ge concentrations are present. In fact, the heat treatment carried out at a temperature that can lead to diffusion from the layer with the highest Ge concentration to the layer with the lowest concentration tends to equalize the Ge content between the two layers so that the physical and electrical properties of the two layers are more It is recognized that no abnormality is discriminated (e.g., "Diffusion of Ge in Si _{1 - x} Ge _x / Si Single Quantum Wells Around Inactive and Oxidative" by M Griglione et al., Journal of Applied Physics, 88th edition, no. 3, Aug. 1, 2000) The diffusion is disadvantageous not only in most of the prior art methods but also in the present invention, because in particular the differentiation of layers 1 'and 2 is the first layer 1' and the opposing second layer. This allows for the continuous selective etching of 2. For this reason, the known method is maintained as above, even below 1000 ° C., in particular below 800 ° C. (see especially FR 04/09980). Technique is carried out by applying to.

However, Applicants have conducted a series of experiments on Si _{1 - x} Ge _x / modified Si _{1 - y} Ge _y / SiO ₂ / bulk Si wafer structures obtained immediately after desorption, whereby Ge diffusion during treatment at 800 ° C. or higher was previously Seen not to stand out than was suggested. In particular, Applicants have shown that the aforementioned RTA can be performed without substantial diffusion between the first layer 1 'and the second layer 2.

4 is a series of results obtained by the applicant.

Measurements were made for structures 30 similar to structure 30 shown in FIG. 1E obtained after removal layers 1 'and 2 stripping. In this study, the first layer 1 'was formed of 20% germanium (i.e. x = 0.2) and had a thickness of about 200 microns, the second layer 2 was formed of strained silicon (i.e. y = 0) and had a thickness of about 200 Å.

4 graphical abscissa shows the probe depth in the sample sample from the first layer 1 'free surface.

4 is divided into a vertical line 12 representing an interface between the first layer 1 'and the second layer 2, wherein the left portion 1' representing the first layer 1 'and the right portion 2 representing the second layer 2 are represented.

The “y” axis in FIG. 4 represents the measured germanium concentration.

The measurement was carried out by secondary ion mass spectroscopy on three kinds of samples heat-treated at temperatures of 750 ° C., 800 ° C. and 850 ° C. for 4 hours; Respective results are shown with diffusion profiles 62, 63 and 64.

To match that observed in the prior materials, at an elevated temperature higher from about 800 ℃, Si _{0 .8} layer 1 'Ge diffusion from the second layer thickness at the bottom of the Ge _{0 .2} This has been confirmed that the larger.

FIG. 4 also shows "Ge diffusion in Si _{1 - x} Ge _x / Si single quantum wells around inactive and oxidative" by M Griglione et al. (Journal of Applied Physics, 88th edition, no 3, Aug. 1, 2000) ) comprises a diffusion profile theoretically calculated from the data provided in, this is the study with respect to the relaxed silicon / Si _{0 .85 0 .15} Ge layer. diffusion profiles 52, 53 and 54 is 750 ℃, 800 each temperature This is the result of integrating the heat treatment at 4 ° C. and 850 ° C. for 4 hours.

Comparing the measured diffusion profiles 62, 63, 64 and the corresponding theoretical diffusion profiles 52, 53, 54, the Ge at the second layer 2 of the strained Si away from the interface 12 with the first layer 1 'measured by the applicant It can be seen that is significantly lower than the theoretical case of the second layer of relaxed Si. This Ge concentration difference between measurement and theory is larger the further away from the interface between the two layers. In particular, from about 10 dB deep below interface 12, the difference between theory and measurement becomes significant. The differences are summarized in the table below, showing the ratio between the theoretically calculated Ge concentration and the Ge concentration measured by the applicant.

depth 220 ohms strong 230 omstrong 250 ohms Heat treatment at 800 ℃ 1/9 1/70 1/600 Heat treatment at 850 ℃ 1/2 1/6 1/25

In the case of preheating performed at 750 ° C, the difference between theory and measurement is small-see diffusion profiles 62 and 52. In addition, the sample measurement without heat treatment was substantially the same as the diffusion profile in the sample treated at 750 ° C. Accordingly, the Applicant was convinced that the diffusion profile between ambient temperature and 750 ° C. was substantially unchanged.

In contrast, Applicants have shown that the diffusion profiles 62 and 63 are closer to the initial profile (after epitaxy) than the prior material diffusion profiles (ie, diffusion profiles 53, 54).

Referring to FIG. 5, the Applicant calculated the diffusion coefficient “D” (in square centimeters per second) (ie, the y-axis) as a function of the heat treatment temperature performed on the sample (the abscissa is 10000 to the inverse of the Kelvin temperature “T”). Multiplied by).

Points 83 and 84 respectively show the diffusion coefficients in the measurement diffusion profiles 63, 64 of FIG. 3. Points 73 and 74 were found by Griglione (see above) and correspond to diffusion after heat treatment for 4 hours at 800 ° C. and 850 ° C., respectively.

Thus, it can be seen that the diffusion coefficients in the strained Si second layer 2 are about four times smaller than in the relaxed Si second layer at the temperature considered.

The results obtained by the Applicant show that the Ge diffusion is surprisingly reduced for the modified Si second layer 2 compared to the relaxed Si case. It will therefore be possible to post-desorption heat treatments that are carried out at temperatures higher than the temperatures normally applied.

Applicants have therefore performed high temperature rapid thermal annealing (RTA) according to the present invention and have shown that the effect of germanium diffusion in the second layer 2, which is strain Si, is much lower than inferred from the preceding data.

Thus, the RTA can reduce the post-tear roughness before the selective etching and stabilize the bonding interface sufficiently to limit the problems caused by the delamination during the selective etching.

The post-tally roughness has conventionally been limited to applying prior to (H and He co-implant) implants and / or applying fracture annealing at 600 ° C. to reduce roughness.

In addition, RTA results in the smoothing of the SiGe layer on the wafer side to encapsulate the oxide layer, as described in FR 03/02623, and also tends to limit the delamination problem at the interface during selective etching. .

Optionally, prior to the RTA, the first layer 1 'can perform the sacrifice (sacrificial) oxide at a portion, Si _1, which must be removed by etching before the RTA carried out _- to get _x Ge _x thickness decreases and the roughness reducing effect Can be.

The sacrificial oxidation is carried out at a temperature of, for example, 650 ° C. or lower. The thickness to be removed may be about 500 kPa to 1500 kPa, preferably 1000 kPa, depending on the thickness of the remaining first layer 1 '.

In Figure 1f, Si _1-x Ge _x of the first layer 1 'is selectively removed, the final transformation Si ₁ on an insulator structure _- get _y Ge _y. Optionally, the strained Si _{1 - y} Ge _y layer can then be thickened by epitaxy.

In order to selectively remove the first layer 1 ', which is Si _{1 - x} Ge _x , selective chemical etching is performed and a chemical suitable for the material is applied.

Thus, in the first embodiment, the second layer 2 is formed of strain Si (ie y = 0); HF: H ₂ O ₂ : CH ₃ COOH, SC1 (NH ₄ OH / H ₂ O ₂ / H ₂ O), or HNA (HF / HNO ₃ / H ₂ O) can be used to remove the first layer 1 '. Can be.

In CH ₃ COOH: H ₂ O ₂ : HF a selectivity of about 40: 1 between SiGe and sSi is obtained.

Examples of selectable concentrations for CH ₃ COOH: H ₂ O ₂ : HF are 4: 3: 0.25 and 1: 1: 5 for SC1.

Etch time is directly related to etch rate. Typically about 5 minutes for 800 kPa when etched with CH ₃ COOH: H ₂ O ₂ : HF.

In a second embodiment, the first layer 1 'has a Ge concentration of 20% or less (ie, x ≦ 0.2) and the second layer 2 has a Ge concentration of 25% or more (ie, y ≧ 0.25); TMAH or KOH can be used to remove the residual layer of the first layer 1 '.

Optionally, to significantly reduce non-uniformity of surface roughness and thickness in pre-co-implant and / or plasma activation and / or low temperature heat treatment and / or removal layers 1 'and 2 to reinforce the bonding interface. RTA with sacrificial oxidation is performed to allow selective etching to be performed substantially the same as prior material, but to eliminate possible disadvantages such as the need to perform pre-mechanical polishing.

In addition, the problems associated with the above-mentioned edge delamination are solved due to the reinforced bonding (by performing at least RTA).

Finally, fine etching of the strained Si _{1 - y} Gey (eg, treatment with SC1) surface layer can be performed after selective etching to remove small amounts of material from which Ge could diffuse.

The method optionally provides a furnace for performing final softening of the strained Si _{1 - x} Ge _x layer when it is necessary to further soften the remaining roughness after the high temperature stabilization step and / or selective etching to close the bonding interface. Termination by annealing or RTA.

Optionally, a final crystal growth step (e.g. epitaxy, for example MBE or CVD) can be performed to thicken the second layer 2 formed of the strain Si _{1 - y} Ge _y .

According to a second variant of the invention, referring to FIGS. 2A and 2B, the donor wafer 10 is formed of a first layer 1 formed of Si _{1 - x} Ge _x , a second formed of Si _{1 - y} Ge _y prior to removal. Layer, and a third layer formed of Si _{1 - x} Ge _x . According to the present invention, the weak region is formed under the second layer 2, for example, in the first layer 1. Si _{1 -} with _x Ge _{x -} selective etching for _x Ge _x, on an insulator structure 30 (as shown in Figure 2b) as described above, the modified Si _{1 - y} Ge _y the second layer and the Si ₁ formed of a With the third layer formed, it is carried out after RTA to form the final strain Si _{1 - y} Ge _y / Si _{1 - x} Ge _x .

Optionally, the second layer formed of strain Si _{1 - y} Ge _y can be made even thicker by crystal growth.

Alternatively and alternatively, a second selective modification Si _{1 - y} Ge _y The chemical etching step can then be performed.

When x = 0 (ie, when the second layer 2 is formed of modified Si), the species are for example KOH (potassium hydroxide), NH ₄ OH (ammonium hydroxide), TMAH (tetramethyl) Ammonium hydroxide), EDP (ethylene diamine / pyrocatechol / pyrazine) can be applied. In this case, the second layer formed of a strained Si is Si ₁ In the first chemical _attack and functions only as a stop layer for protecting the third layer formed of _x Ge _x. SiGeOI structure 30 (not shown) is obtained. Optionally, a strained Si layer can be grown on SiGeOI and the new strained layer can have a crystalline structure of better quality than the first layer 1 already etched.

In a third variant of the invention, with reference to Figures 3a and 3b, the donor wafer 10 is removed prior to, alternately Si _{1 - x} Ge _x first layers 1A, 1B, 1C, 1D, 1E and variants formed by Si _It consists of a multilayer structure comprising second layers 2A, 2B, 2C, 2D, 2E formed of _{1 - y} Ge _y . A number of removal steps in accordance with the present invention are performed on donor wafer 10, followed by each removal followed by recycling of the remaining portion of donor wafer 10 and preparing for a new removal. Thus, for example, modified Si on insulator _{1 - y} Ge _y first structural member 30A and variations Si on insulator _{1 - y} Ge _y second structure 30B is to be formed from the same donor wafer 10. This type of removal is disclosed in US 2004/0053477.

In a special case of the invention, each strained layer of donor wafer 10 [“2” in FIGS. 1A-1F, 2A and 2B, “2A”, “2B”, “2C”, “2D” and “in FIGS. 3A and 3B) 2E "] is thick and without thickness alleviating elastic deformation, i. This is made possible by low temperature epitaxy formation. For example, a strained Si layer deposited at a temperature in the range of 450 ° C. to 650 ° C. in a growth support substrate formed of Si _0.8 Ge _0.2 typically reaches about 30 nm to 60 nm thick without one or more of these strain reliefs.

If such a thick strained layer is formed, in order to avoid strain relaxation, it is necessary not to exceed the predetermined limit temperature in the continuous treatment (which is close to the lamination temperature), and especially in the treatment between lamination and desorption by Smart-Cut ^® . Care must be taken.

In the case of thick strained layers, plasma activation prior to bonding (discussed above) is advantageously carried out at typical ambient temperatures of about 100 ° C. or less. In addition, a bonding layer of at least one dielectric material, such as SiO ₂ , is advantageously formed on one or both surfaces to which it is bonded, and the dielectric material layer helps to maintain elastic deformation continuously (ie after detachment). In addition to plasma activation, a post-desorption heat treatment at temperature T (discussed above) can be performed and T is advantageously lower than the temperature at which the thick strained layer is deposited, if no bonding layer is provided. .

Obviously, those skilled in the art will readily facilitate the present invention when a small amount of paper is added to the Si _{1 - x} Ge _x and Si _{1 - y} Ge _y layers, for example a small amount (about 5% or less) of doped species and / or carbon added. Can be implemented.

Claims (35)

In a structure manufacturing method comprising a removing layer of a semiconductor material taken from a donor wafer, the donor wafer is formed of a first layer formed of Si _{1 - x} Ge _x and a Si _{1 - y} Ge _y on the first layer before the removal. Consists of two layers ( x and y each range from 0 to 1, where x is different from y ), a) implanting the atomic species to form a weak region below the second layer; b) donor wafer and receiving wafer bonding step; c) providing energy to detach the removal layer from the donor wafer in the weak region; d) a rapid thermal annealing (RTA) step performed at a temperature of about 1000 ° C. or higher for no more than 5 minutes; e) the selective etching of the remaining portion of the first layer opposite the second layer is continuously configured. The method of claim 1, wherein step d) proceeds for about 10 seconds to about 30 seconds at a temperature in a range from about 1000 ° C. to about 1200 ° C. 6. The method of claim 1, wherein step d) proceeds at about 1100 ° C. for about 10 seconds. The method of any one of the preceding claims, wherein step d) proceeds in a reducing atmosphere. The method of claim 1, wherein step d) is performed in a reducing atmosphere of argon and hydrogen or an argon reducing atmosphere. The method of claim 1, wherein the sacrificial oxidation of the first layer proceeds between steps c) and d). The method of any one of the preceding claims, wherein plasma activation of at least one bonding surface proceeds before step b). The method of any one of the preceding claims, wherein the heat treatment of at least about 30 minutes to reinforce the bond also proceeds after step b). The process of claim 1, wherein the heat treatment proceeds for about 30 minutes to about 4 hours at a temperature in the range of about 350 ° C. to about 800 ° C. before step d). The method of claim 1, wherein the heat treatment proceeds at a temperature in a range from about 350 ° C. to about 700 ° C. 7. The method of claim 1, wherein the heat treatment proceeds at a temperature of about 600 ° C. The method of any one of the preceding three, wherein the heat treatment proceeds after step c) and continues in step c) in the same furnace. The method of claim 1, wherein the heat treatment consists of a simple change from the desorption temperature of step c) to a selected temperature for heat treatment. The method of claim 1, wherein step c) proceeds at about 600 ° C. for about 30 minutes to 2 hours. The method of claim 8, wherein the heat treatment proceeds after step e) at about 1000 ° C. to 1100 ° C. for about 2 hours. The method of any one of the preceding claims, wherein the atomic species implanted during step a) consists of a single atomic component. The method of claim 1, wherein the atomic species implanted during step a) is hydrogen. The method of claim 1, wherein the selected hydrogen dosage is 3 × ^{10 16} atoms / cm ^2. To 10ｘ10 ¹⁶ atoms / cm ² And the hydrogen implant energy is selected from 20 KeV to 80 KeV. The method of claim 1, wherein the selected hydrogen dosage is ⁶ × ^{10 16} atoms / cm ^2. And a hydrogen implant energy of about 30 KeV. 16. The method of any one of claims 1 to 15, wherein the atomic species implanted during step a) consists of two distinct atomic components, thus step a) constitutes a co-implant. The method of claim 1, wherein the co-implant of step a) is a co-implant of helium and hydrogen. The method of claim 1, wherein the selected helium and hydrogen dosages are each 1 × 10 ¹⁶ atoms / cm ^2. And G 1ｘ10 ¹⁶ atoms / cm ² And the selected helium and hydrogen implant energies are between 20 KeV and 80 KeV. The method of claim 1, wherein the selected helium and hydrogen implant energies are on the order of 50 KeV and 30 KeV, respectively. The method of any one of the preceding claims, wherein after step c) does not comprise performing mechanical polishing. The method of any one of the preceding claims, wherein after step e) comprises Si _{1 - y} Ge _y crystal growth on the second layer to thicken the second layer. The method of any one of the preceding claims, wherein the second layer is formed of elastically strained Si _{1 - y} Ge _y . The method of claim 1, wherein the donor wafer comprises a support substrate and a SiGe buffer structure formed of bulk Si under the first and second layers. 26. The method of claim 1, wherein the donor wafer further comprises a third layer of Si _1-x Ge _x on the second layer. The method of claim 1, further comprising, after step e), selectively etching the second layer opposite the third layer. 26. The donor wafer of claim 1, wherein the donor wafer comprises a support substrate formed of bulk Si, a SiGe buffer structure and first layers of Si _{1 - x} Ge _x and alternating strain Si _{1 -y} Ge _y . A structure manufacturing method comprising a multi-layer structure comprising a second layer and capable of multiple removal from the same donor wafer. 31. The method of any of claims 26-30, wherein the strained Si _{1 - y} Ge _y layer is thicker than the critical balance thickness. The process of claim 1 further comprising, prior to step a), forming the strained layer at a lamination temperature in the range from about 450 ° C. to about 650 ° C., wherein the treatment performed between the lamination and the desorption obtained in step c) A method of making a structure, which is implemented at a temperature lower than or equal to the lamination temperature. 33. The method of any one of claims 26-32, wherein y is zero. The method of any one of the preceding claims, further comprising, prior to step b), forming a bonding layer on the donor wafer and / or the receiving wafer, the bonding layer being for example SiO ₂ , Si ₃ N ₄ or A method of manufacturing a structure, comprising an electrically insulating material such as Si _x O _y N _z . Application of the method of manufacturing a structure according to the preceding claims for the manufacture of semiconductor-on-insulator structures.

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