KR20070082921A - Method of forming an isolation layer of the fin type field effect transistor and method of manufacturing the fin type field effect transistor using the same - Google Patents

Abstract

A method for fabricating an isolation layer of a fin-type FET is provided to remarkably decrease the number of process for fabricating a fin-type FET by forming isolation layers having different steps in the peripheral and cell regions of a substrate by a minimized process. A substrate(100) divided into a cell region and a peripheral region that are exposed to an opening of a hard mask pattern is etched to form a trench so that a silicon fin(110) is defined by the trench to be guaranteed as the channel region of the fin-type transistor. A liner layer(112) having substantially the same thickness is formed on the bottom and the top surfaces of the trench and on the surface of the hard mask pattern. A planarized insulation layer is formed to fill the trench having the liner layer. A photoresist pattern is formed to cover the insulation layer in the peripheral region. A part of the insulation layer in the cell region is firstly wet-etched to form an insulation layer pattern. The photoresist pattern is removed. While the liner layer and the hard mask pattern are removed by a second wet-etch process, the insulation layer in the cell region and a part of the upper part of the insulation layer pattern in the cell region are etched to form isolation layers(120a,120b) having different heights in the peripheral and cell regions.

Description

Method of manufacturing an isolation layer of the fin type field effect transistor and method of manufacturing the fin type field effect transistor using the same}

1 to 6 are cross-sectional views illustrating a method of manufacturing a device isolation film of a fin type field effect transistor according to an embodiment of the present invention.

7 to 9 are perspective views illustrating a method of manufacturing a fin type field effect transistor using the device isolation film manufacturing method of FIGS. 1 to 6.

<Explanation of symbols for main parts of the drawings>

100: substrate 104: hard mask pattern

106: trench 110: silicon fin

112 liner film 114 insulating film

116: insulating film pattern 118: photoresist pattern

120a: device isolation layer in cell region 120b: device isolation layer in peripheral region

132: gate insulating film pattern 142: gate electrode

The present invention relates to a method of manufacturing a device separator and a method of manufacturing a transistor using the same, and more particularly, to a method of manufacturing a device separator of a pin-type field transistor having a different step and a method of manufacturing a pin-type field transistor using the same.

As semiconductor devices continue to be highly integrated in terms of high performance, high speed, low power consumption, and economical aspects, not only the size of the cell region, which is an element formation region, but also the channel length of MOS transistors formed in the cell region are reduced. Problems such as punch-through, short channel effect, increased parasitic capacitance (junction capacitance) between the junction region and the substrate, and leakage current increase as the channel length of the transistor decreases It is becoming. Accordingly, various methods for maximizing the performance of the transistors while reducing the size of the transistors formed on the semiconductor substrate have been researched and developed. Representative examples thereof include a fin structure and a gate all around (GAA) structure transistor.

In the fin field effect transistor, since gate electrodes exist on both sides of the channel (that is, both sidewalls of the fin are used as channels), channel control of the gate electrode occurs on both sides. Therefore, the short channel effect can be suppressed.

However, since the fin type field effect transistor does not need to be formed in the peripheral region of the substrate where the process margin is not required, the device isolation layer having the same height as the substrate height must be formed in the peripheral region separately from the cell region. .

Therefore, current processes for forming the fin-type field effect transistor only in the cell region of the substrate include a plurality of wet processes and photoresist patterns for forming a photoresist pattern to cover the peripheral region and a device isolation film having a low height in the cell region. The baking process for hardening is applied. In this case, in order to form the device isolation layer in the cell region while minimizing damage to the photoresist pattern, there is a problem in that about three times of HF cleaning and about two times of baking process of the photoresist pattern have to be performed.

Accordingly, a first object of the present invention is to provide a method capable of shortening the manufacturing process of an element isolation film having different steps (height) in the cell region and the peripheral region of the substrate when manufacturing the fin type field effect transistor.

It is a second object of the present invention to provide a method of manufacturing a fin type field effect transistor using the device isolation film forming method.

According to the method of fabricating an isolation layer of a fin type field effect transistor according to an embodiment of the present invention for achieving the first object, first, by etching the substrate divided into a cell region and a peripheral region exposed to the opening of the hard mask pattern By forming the trench, a silicon fin defined by the trench is formed to secure the channel region of the fin type transistor. A liner film having substantially the same thickness is formed on the bottom, side, and hard mask patterns of the trench. A planarized insulating layer is formed to bury the trench in which the liner layer is formed. A photoresist pattern covering the insulating layer of the peripheral area is formed. A portion of the insulating film of the cell region is first wet etched to form an insulating film pattern. The photoresist pattern is removed. The liner layer and the hard mask pattern are removed by a second wet etching, and a portion of the insulating layer pattern of the peripheral region and the cell region is etched. As a result, device isolation layers of the fin type field effect transistor having different heights are formed in the peripheral region and the cell region.

According to a method of manufacturing a fin type field effect transistor according to an embodiment of the present invention for achieving the above-described second object, first, by etching a substrate divided into a cell region and a peripheral region exposed to the opening of the hard mask pattern to form a trench By forming, a silicon fin defined by the trench is formed to secure the channel region of the fin transistor. A liner film having substantially the same thickness is formed on the bottom, side, and hard mask patterns of the trench. A planarized insulating layer is formed to bury the trench in which the liner layer is formed. A photoresist pattern covering the insulating layer of the peripheral area is formed. A portion of the insulating film of the cell region is first wet etched to form an insulating film pattern. The photoresist pattern is removed. The liner layer and the hard mask pattern are removed by a second wet etching, and a portion of the insulating layer pattern of the peripheral region and the cell region is etched. As a result, device isolation layers of the fin type field effect transistor having different heights are formed in the peripheral region and the cell region. Subsequently, a gate oxide film having substantially the same thickness is formed on the surface of the silicon fin exposed from the device isolation layer. A gate electrode is formed on the silicon fin and the device isolation layer on which the gate oxide film is formed. As a result, a fin field effect transistor is formed in the device isolation film in the cell region.

According to the above-described process, the process may be performed to minimize the number of device isolation layers having different steps in the peripheral region and the cell region of the substrate. That is, the device isolation layer having different steps may be formed using only two wet etching processes without performing the baking process of the photoresist pattern formed on the peripheral region of the substrate. In addition, when the device isolation layer having a lower height than the surface of the substrate is formed in the cell region, the exposed liner layer may be removed in situ.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey.

In the accompanying drawings, the dimensions of the substrates, layers (films), regions, openings, electrodes, patterns, or structures are shown in greater detail than actual for clarity of the invention. In the present invention, each layer (film), region, opening, electrode, pattern or structure is placed on the substrate, each layer (film) or pattern "on", "on bottom", "on top" or "side". When referred to as being formed, it means that each layer (film), region, opening, pattern or structure is formed directly over or below the substrate, each layer (film), region, electrode or patterns, or other layers ( Film), other regions, other patterns, openings, or other structures may additionally be formed on the substrate. In addition, where each layer (film), region, pattern, electrode or structure is referred to as "first", "second", "third" or top, bottom, it is not intended to limit these members but only each layer. (Film), regions, openings, patterns or structures for distinguishing. In addition, the cleaning and drying generally performed after performing the etching process or the stripping process mentioned in the embodiment of the present invention may be omitted since it is obvious to those skilled in the art.

Device Separation Method for Fin Field Effect Transistor

1 to 6 are cross-sectional views illustrating a method of manufacturing a device isolation film of a fin type field effect transistor according to an embodiment of the present invention.

Referring to FIG. 1, a hard mask pattern 104 having an opening is formed on a substrate 100 including a cell region and a field region.

Specifically, the substrate 100 is divided into a cell region having a high degree of integration of the formed patterns and a peripheral area having a significantly lower degree of integration of the formed patterns than the cell area. In particular, since the width of the trench to be formed and the width of the exposed substrate are larger than the width to be formed in the cell region, the formation of the fin type field effect transistor is not required in the peripheral region.

A pad oxide film (not shown) is formed on the substrate 100 made of silicon. The pad oxide film is formed to have a thickness of about 50 to about 200 kPa, preferably about 100 kPa from the surface of the silicon substrate 100. The pad oxide layer may be formed by performing a thermal oxidation process or a chemical vapor deposition (CVD) process, and then serves to prevent damage to the silicon substrate when forming the hard mask pattern.

Next, a hard mask pattern 104 is formed on the substrate 100 on which the pad oxide film is formed, which defines a region in which the device isolation layer is formed. The hard mask pattern 104 is formed by sequentially forming a nitride film (not shown) and a first photoresist pattern (not shown) on the pad oxide film, and then dry etching the nitride film exposed by the first photoresist pattern. Form.

The nitride film is silicon nitride, and a low pressure chemical vapor deposition (LPCVD) process or plasma enhanced chemical vapor deposition (PECVD) using SiH ₂ Cl ₂ gas, SiH ₄ gas, NH ₃ gas, or the like. It is formed by performing the process.

The first photoresist pattern is a photoresist composition is applied on the nitride film to have a substantially uniform thickness, baked to form a photoresist film (not shown) and then subjected to exposure and development processes on the photoresist film. It is formed by performing sequentially.

Subsequently, the nitride film exposed to the first photoresist pattern is etched to form a hard mask pattern 104 having an opening exposing the surface of the pad oxide film. Thereafter, the first photoresist pattern is removed by performing an ashing process / strip process.

Referring to FIG. 2, the substrate 100 exposed through the opening of the hard mask pattern 104 is etched to form a trench 106 in the substrate. As a result, a silicon fin 110 defined by the trench is formed.

In detail, a trench 106 having a depth of about 1500 to 3500 μm is formed by sequentially etching the pad oxide layer exposed to the opening of the hard mask pattern 104 and the substrate 100. The trench 106 preferably has a depth of 2500 kPa. Since the trench 106 is formed in the substrate, the substrate 100 is simultaneously defined as an active region corresponding to the silicon fin 110 and an isolation region in which an isolation layer (not shown) is formed. The silicon fin is formed to secure the channel region of the fin type transistor.

Subsequently, in order to cure damage to the substrate 100 caused by the formation of the trench 106 and to prevent leakage current, the surface of the silicon substrate exposed to the trench is heat treated and nitride liner layer 112 is formed of nitride. Form. The first liner layer 112 made of nitride is formed by nitriding the side and bottom surfaces of the trench formed in the silicon substrate in a nitrogen atmosphere or by depositing low pressure chemical vapor on the bottom, side and hard mask patterns of the trench. Formed by performing the process.

Referring to FIG. 3, a first insulating layer 114 is buried in the trench 106 and has a flattened top surface.

Specifically, a preliminary insulating film (not shown) covering the hard mask pattern 104 is formed while the trench 106 in which the liner layer 112 is formed is buried. For example, the preliminary insulating layer may be formed by depositing silicon oxide on the substrate under a process condition having a pressure of about 1 to 2 mTorr and a bias power of about 1000 to 1500W.

Subsequently, a chemical mechanical polishing process is performed to planarize the top surface of the preliminary insulating layer (not shown) until the top surface of the hard mask pattern 104 is exposed. Due to the chemical mechanical polishing process, the preliminary insulating film is formed of an insulating film 114 having a planarized top surface.

Referring to FIG. 4, after forming the second photoresist pattern 118 covering the planarized insulating layer 114 formed in the peripheral region, the insulating layer 114 exposed to the hard mask pattern 104 existing in the cell region. Etch). As a result, the insulating film pattern 116 existing only in the trench 106 formed in the cell region is formed.

Specifically, while protecting the insulating film in the peripheral area by using the second photoresist pattern 118, dry etching the insulating film 114 by applying a hard mask pattern 104 as an etching mask in the cell region to the Lower the height As a result, the insulating layer is formed of an insulating layer pattern 116 having a height that exposes a portion of the liner layer 112 formed on the side of the hard mask pattern and the side of the trench. That is, the insulating layer pattern 116 is formed such that its upper surface is lower than the upper surface of the silicon fin 110.

Referring to FIG. 5, the second photoresist pattern is removed by performing an ashing process and a cleaning process using an oxygen plasma. As the second photoresist pattern is removed, the hard mask pattern 104 and the insulating layer 114 formed in the peripheral area are exposed.

Referring to FIG. 6, the liner layer 112 and the hard mask pattern 104 exposed in the cell region may be removed, and the insulating layer 114 of the peripheral region and the insulating layer pattern 116 of the cell region may be removed. Some etch.

Specifically, the device isolation layer having the same height as the surface of the silicon substrate is removed while the liner layer 112 made of nitride and the hard mask pattern are removed by performing a wet cleaning process using an aqueous solution of phosphoric acid. 120b). In this case, the insulating film pattern existing in the cell region is also etched by the thickness of the insulating film of the peripheral region is formed as a device isolation layer 120a having a lower surface than the silicon fin.

Fabrication of Fin Field Effect Transistors

7 to 9 are perspective views illustrating a method of manufacturing a fin type field effect transistor using the device isolation film manufacturing method of FIGS. 1 to 6.

Referring to FIG. 7, a structure protrudes between the device isolation layers 120a of the cell region having a height lower than that of the device isolation layer 120b of the peripheral region, and has a top surface higher than the top surface of the device isolation layer 120a. A gate insulating layer 150 is formed on the substrate 100 on which the silicon fins 110 are formed. Here, since the method of manufacturing the device isolation layers 120a and 120b and the silicon fin 110 is described in detail with reference to FIGS. 1 to 6, it is omitted to avoid duplication.

For example, the gate insulating layer 130 may be formed on a surface of the silicon fin 110 that is exposed and used as a channel region by performing a thermal oxidation process. In addition, it may be formed on the surface of the silicon fin 110 by performing a chemical vapor deposition process. Here, the gate insulating film 130 is a silicon oxide film (SiO ₂ ).

As another example, the gate insulating layer 130 may be a thin film made of a metal oxide having a higher dielectric constant than the silicon oxide layer. Thin films made of the metal oxides tend to be formed by performing atomic layer deposition. In particular, in the atomic layer deposition process for forming the thin film including the metal oxide, the reaction material is repeatedly provided at least once in the order of supplying a purge → purging → providing an oxidizing agent → purging. As a result, a gate insulating layer 130 made of metal oxide is formed on the surface of the silicon fin 110. Here, the reaction material is a material containing a metal precursor, in the case of a material containing a hafnium precursor, TEMAH (tetrakis ethyl methyl amino hafnium, Hf [NC ₂ H ₅ CH ₃ ] ₄ ), hafnium butyl oxide (Hf (O -tBu) ₄ ) and the like, and in the case of a material containing an aluminum precursor, include TMA (trimethyl aluminum, Al (CH ₃ ) ₃ ) and the like. In addition, the oxidizing agent includes O ₃ , O ₂ , H ₂ O, plasma O ₂ , remote plasma O ₂ and the like. For example, when the gate insulating layer 150 includes hafnium oxide, the gate insulating layer 150 is formed by performing atomic layer deposition which is repeated at least once in the order of provision of TEMAH → purge → provision of O ₃ → purge.

Referring to FIG. 8, the conductive layer 140 and the gate mask (not shown) covering the silicon fin 110 and the device isolation layers 120a and 120b having the gate insulating layer 130 are sequentially formed.

The conductive layer is made of polysilicon doped with an impurity and then patterned into a gate electrode. The conductive layer may have a multilayer structure including a doped polysilicon layer and a metal silicide layer. The gate mask is formed of a material having a high etching selectivity with respect to a subsequently formed interlayer insulating film (not shown). For example, when the interlayer insulating film is made of an oxide such as silicon oxide, the gate mask is made of silicon nitride.

9, the conductive layer 140 and the gate insulating layer 130 exposed to the gate mask are sequentially patterned using the gate mask as an etching mask. Accordingly, a gate structure including a gate insulating layer pattern 132, a gate electrode 142, and a gate mask (not shown) is formed on each of the silicon fins 110.

Subsequently, a source / drain region (not shown) is formed by implanting impurities under the surface of the silicon fin exposed between the gate structures using the gate structures as an ion implantation mask, and then performing a heat treatment process. The result is increased channel drive capability by the gate, resulting in a fin field effect transistor that can minimize short channel effects.

As described above, according to the present invention, it is possible to form a process to minimize device isolation layers having different steps in the peripheral region and the cell region of the substrate. That is, the device isolation layer having different steps may be formed using only two wet etching processes without performing the baking process of the photoresist pattern formed on the peripheral region of the substrate. In addition, when the device isolation layer having a height lower than the surface of the substrate is formed in the cell region, the exposed liner layer may be removed in situ, thereby significantly shortening the manufacturing method of the fin type field effect transistor.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (4)

Forming a silicon fin defined by the trench to form a trench by etching a substrate divided into a cell region exposed to an opening of a hard mask pattern and a peripheral region to form a channel region of a fin type transistor; Forming a liner film having substantially the same thickness on the bottom, side, and hard mask patterns of the trench; Forming a planarized insulating film for embedding the trench in which the liner film is formed; Forming a photoresist pattern covering the insulating film in the peripheral region; First wet etching a portion of the insulating layer in the cell region to form an insulating layer pattern; Removing the photoresist pattern; And Device isolation layers having different heights in the peripheral region and the cell region may be removed by partially etching the liner layer and the hard mask pattern by a second wet etching process and etching the upper portion of the insulating layer pattern in the peripheral region and the cell region. A device isolation film manufacturing method of a fin type field effect transistor comprising the step of forming. The method of claim 1, wherein the forming of the planarized insulating film is performed. Depositing an oxide covering the top surface of the hard mask pattern while sufficiently embedding the trench; And And chemically mechanically polishing the upper portion of the oxide until the upper surface of the hard mask pattern is exposed. The fin type field effect transistor of claim 1, wherein the first wet etching is performed using a LAL etching solution including water, hydrofluoric acid, and ammonium bifluoride, and the second wet etching is performed using an aqueous solution of phosphoric acid and an aqueous solution of hydrofluoric acid. Device separation membrane manufacturing method. Forming a silicon fin defined by the trench to form a trench by etching a substrate divided into a cell region exposed to an opening of a hard mask pattern and a peripheral region to form a channel region of a fin type transistor; Forming a liner film having substantially the same thickness on the bottom, side, and hard mask patterns of the trench; Forming a planarized insulating film for embedding the trench in which the liner film is formed; Forming a photoresist pattern covering the insulating film in the peripheral region; First wet etching a portion of the insulating layer in the cell region to form an insulating layer pattern; Removing the photoresist pattern; The liner layer and the hard mask pattern, which are exposed due to the formation of the insulating layer pattern, are removed by second wet etching, and the upper portion of the insulating layer pattern and the insulating layer pattern of the device cell region are partially etched in the peripheral region and the cell region. Forming device isolation layers having different heights; Forming a gate oxide film on a surface of the silicon fin exposed from the device isolation layer; And And forming a gate electrode film on the silicon and device isolation film on which the gate oxide film is formed.

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