KR20070080100A - Frame data correction circuit and liquid crystal display including the same - Google Patents

Abstract

A frame date correction circuit and a liquid crystal display device having the same are provided to reduce response time of an LCD(Liquid Crystal Display) panel by storing a DCC correction value or compensation reference data in a voltage code format. A frame date correction circuit includes a frame memory(526), an LUT(Look-Up Table), and a DCC(Dynamic Capacitance Compensation) converter(528). The frame memory stores all or a portion of the previous frame data during one frame period. The LUT stores a DCC compensation value in a voltage code format corresponding to some bits of the previous frame data and some bits of the current frame data. The DCC converter converts the current frame data based on the DCC compensation value and outputs the result. Compensation reference data is stored in the voltage code format in the LUT.

Description

Frame data correction circuit and liquid crystal display including the same {Frame date correction circuit and liquid crystal display comprising the same}

1 is a diagram illustrating a schematic configuration of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an internal block diagram of a timing controller according to an embodiment of the present invention.

3 is a data processing block diagram of FIG. 2.

4 is an ACC block and a DCC block diagram of FIG. 3.

FIG. 5 is an internal block diagram of a gray signal converter of FIG. 4.

6 is a graph illustrating luminance according to a gradation level according to an exemplary embodiment of the present invention.

7 is a graph illustrating luminance according to a voltage level according to an embodiment of the present invention.

8 is a graph illustrating a voltage code according to a gradation level according to an embodiment of the present invention.

9 is a diagram illustrating a look up table according to an exemplary embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100: liquid crystal panel 200: gate driver

300: data driver 400: voltage generator

500: timing controller 510: data processing block

512: ACC block 514: DCC block

516: Timing redistribution block 522: Gray scale extension

524: Gray scale reduction unit 526: Frame memory

528: gradation signal conversion unit 530: control signal generation block

542: lookup table 546: DCC converter

The present invention relates to a frame data correction circuit and a liquid crystal display including the same, and more particularly, to a frame data correction circuit capable of improving the response characteristic of the liquid crystal and a liquid crystal display including the same.

In general, a liquid crystal display (Liquid Crystal Display) is a flat panel display device that displays an image using a liquid crystal (Liquid Crystal), is thinner and lighter than other display devices, has the advantage of low power consumption and low driving voltage There is this.

In a liquid crystal display device, a liquid crystal layer is interposed between a first display panel on which a reference electrode and a color filter are formed, and a second display panel on which a thin film transistor and a pixel electrode are formed, and apply different potentials to the pixel electrode and the reference electrode. By forming an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance to represent the image.

In the liquid crystal display, image data including R, G, and B is input from an external graphic source, and the image data is transferred to the liquid crystal panel through a timing controller. In this case, the timing controller includes a DCC (Dynamic Capacitance Compensation) block for improving the response speed of the liquid crystal and an Automatic Color Correction (ACC) block for improving the color characteristics. Here, the ACC block may be implemented with analog or digital gamma. Analog gamma is implemented as an external resistor in the form of a string, while digital gamma implements gamma by storing data in the form of a look up table in memory. Accordingly, in the case of digital gamma stored as data in a memory, it is easy to control the timing controller, and gamma related technologies such as dynamic gamma control (DGC) and temperature compensation gamma may be applied.

The DCC block is stored in the form of a lookup table in the memory like the digital gamma of the ACC block. In this case, the value stored in the memory is a gray value. That is, when the image data is 8 bits, values of 0 to 255 or coefficients for interpolation are stored.

As such, the ACC block and the DCC block are embodied differently in the form of voltage and gray value, respectively. Therefore, when the gamma profile is changed by an arbitrary condition in the ACC block, even if the gray scale value measured as the optimum value of the liquid crystal response according to the gamma profile before the change is applied, other voltages are eventually applied to the liquid crystal.

An object of the present invention is to provide a frame data correction circuit capable of improving the response characteristics of liquid crystals.

Another object of the present invention is to provide a liquid crystal display device including a frame data correction circuit capable of improving response characteristics of liquid crystals.

The technical problems of the present invention are not limited to the above-mentioned technical problems, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

Frame data correction circuit according to an embodiment of the present invention for achieving the above technical problem, a frame memory for storing all bits or some bits of the previous frame data for one frame, some bits of the current frame data and the previous frame data And a DCC converter for converting and outputting current frame data based on the DCC correction value based on the DCC correction value.

According to another aspect of the present invention, there is provided a liquid crystal display including: a liquid crystal panel including a plurality of unit pixels defined in an area where a plurality of gate lines and data lines intersect, and driving the liquid crystal panel. A control signal generation block for generating a gate and data control signal for the ACC block, and an ACC block that extends one frame into multiple frames to receive at least one gray level between two arbitrary gray level values by receiving image data from an external source. And a frame memory for storing all or some bits of the frame data output from the ACC block for one frame, and DCC correction values in the form of voltage codes corresponding to some bits of the current frame data and some bits of the previous frame data. A lookup table for storing the current program based on the DCC correction value A timing controller including a frame data correction circuit including a DCC converter configured to convert and output the data; a driving voltage generator configured to receive the control signal and generate a plurality of driving voltages; A gate driver to apply and a data driver to apply a data voltage to the data line.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, the invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention;

1 is a diagram illustrating a schematic configuration of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, the liquid crystal display according to the exemplary embodiment of the present invention includes a liquid crystal panel 100, a gate driver 200, a data driver 300, a voltage generator 400, and a timing controller 500. It includes.

The liquid crystal panel 100 includes a plurality of gate lines and data lines that cross each other, and pixels formed in an area where each gate line and data line cross each other, and are used for display whenever the gate lines are sequentially scanned. An analog voltage is applied to the corresponding pixel via the data line.

The timing controller 500 inputs image data consisting of R, G, and B, a data enable signal DE indicating a frame viewpoint, a synchronization signal SYNC, and a clock signal CLK from an external graphic source. do. The image data is transmitted to the data driver 300 after data processing such as timing redistribution is performed by the data processing block of the timing controller 500. In addition, the timing controller 500 generates and transmits various control signals for controlling the display operation by using the data enable signal DE, the synchronization signal SYNC, and the clock signal CLK.

The voltage generator 400 generates a gate on / off voltage for scanning the gate line, outputs the gate on / off voltage to the gate driver 200, and generates a gray voltage, which is a pixel applied voltage, and transmits the gray voltage to the data driver 300.

The data driver 300 selects a gray voltage corresponding to the image data transmitted from the timing controller 500 and applies the gray voltage to the liquid crystal panel 100.

2 is an internal block diagram of a timing controller according to an embodiment of the present invention, FIG. 3 is a data processing block diagram of FIG. 2, and FIG. 4 is an ACC block and DCC block diagram of FIG. 3.

As shown in FIG. 2, the timing controller 500 according to an embodiment of the present invention includes a data processing block 510 and a control signal generation block 530.

The data processing block 510 includes an ACC block 512, a DCC block 514, and a timing redistribution block 516, as in FIG. 3, with the timing redistribution block 516 being a typical function of the timing controller 500. As a block to perform the operation, the format of the image data input from the graphic source is converted in accordance with the circuit specification of the data driver 300.

The ACC block 512 includes a gray scale expansion unit 522 and a gray scale reduction unit 524, and the DCC block 514 includes a frame memory 526 and a gray level signal converter 528.

First, N bits of video data are input to the gray scale expansion unit 522, and the gray scale expansion unit 522 expands the number of bits of the video data into (N + d) bits. Then, in order to convert the output of the timing controller 500 into the number of bits that can be processed by the data driver 300, the gray scale reduction unit 524 reduces the data of the (N + d) bit back to N bits. At this time, the gray scale reduction unit 524 reduces the number of bits of the data and simultaneously adds '1' to the gray level value of the upper N bits and the gray level value alternately in predetermined frame units according to the extension bit d. Configure the frame to occur. That is, when the gray value of the N-bit data is 'A', the frame data is configured such that the frequency of occurrence of 'A' and 'A + 1' is adjusted according to the extension bit d during a predetermined frame. Gray levels between the expressible gray values may be expressed. Here, although the gray scale reduction unit 524 reduces the (N + d) bit data to N bits, the present invention is not limited thereto and may be changed according to the bit processing capability of the data driver 300.

The N bits of data output from the gray scale reduction unit 524 are transmitted to the DCC block 514, and the upper m bits of the N bits of data are input to the frame memory 526. The frame memory 526 stores image data displayed on the liquid crystal display in a frame unit and may be disposed outside the timing controller 500.

On the other hand, the m-bit data before one frame stored in the frame memory 526 and the N-bit data of the current frame output from the gradation reduction unit 524 are input to the gradation signal converter 528. The gray level signal converter 528 obtains a DCC correction value from a look-up table using data of the current frame and the previous frame, and estimates or calculates the DCC converted data from the (Nm) bits of the DCC correction value and the input data. The final output is obtained.

In addition, the control signal generation block 530 is provided with a control signal for controlling the display, for example, a data enable signal DE, a sync signal SYNC, and a clock signal CLK indicating a frame time point. A gate control signal, a data control signal, and the like are generated. The generated gate control signal and the data control signal are transmitted to the gate driver 200 and the data driver 300, respectively.

FIG. 5 is an internal block diagram of a gray signal converter of FIG. 4.

As shown in FIG. 5, the lookup table 542 includes m-bit previous frame data output from the frame memory 526 of FIG. 4 and a current frame of N bits output from the gray scale reduction unit 524 of FIG. 4. The data of the upper m bits of the data is input, respectively. In the look-up table 542, a m-bit DCC correction value is determined using the previous frame data and the current frame data as addresses, and the value is output to the DCC converter 546. The DCC converter 546 inputs the m-bit DCC correction value output from the lookup table 542 and the (Nm) bit of the current frame data. The DCC conversion is performed by configuring N bits by operation using these data. Data is obtained.

Although not shown in the drawing, the look-up table 542 does not provide the DCC correction value directly, but provides only correction reference data and coefficients, and the DCC correction value is a correction reference data and coefficients. It can be obtained by the operation of the DCC converter 546 using. N bits are constructed based on the DCC correction value thus obtained.

6 is a graph showing luminance according to a gradation level according to an embodiment of the present invention, FIG. 7 is a graph showing luminance according to a voltage level according to an embodiment of the present invention, and FIG. 8 is an embodiment of the present invention. It is a graph which shows the voltage code according to the gradation level according to an example. 9 is a diagram illustrating a look up table according to an exemplary embodiment of the present invention.

As shown in FIG. 6, when the target gamma value is 2.2 (A), assuming that an arbitrary gradation level is G ₁ , the luminance at this time is represented by L ₂ , and in order to obtain the corresponding luminance as in FIG. Likewise, the luminance of L ₂ may be obtained by applying a voltage value corresponding to V ₂ . At this time, the reference data for correction according to the set target gamma value is stored in the lookup table 542. Here, when the target gamma value is changed to 2.6 (C), assuming that an arbitrary gradation level is G ₁ , the luminance at this time is represented by L ₃ , and as shown in FIG. 7 to obtain the corresponding luminance, The voltage value corresponding to V ₁ must be applied to L ₃ . Luminance can be obtained.

As such, when the target gamma value is changed, the luminance is changed, and the voltage value for representing the corresponding luminance is also changed. As shown in FIG. 8, the gradation level is shifted from G ₂ to G ₁ to the liquid crystal panel. The applied voltage code value is changed from V _code2 to V _code1 . Therefore, the reference data for correction also vary according to the target gamma value.

As shown in FIG. 9, the lookup table 542 of the present invention stores the reference data for correction used when the DCC correction value or interpolation is applied in the form of a voltage code instead of a gray value. In this case, the voltage code is stored as an unsigned 12-bit binary number, and the DCC converter 546 converts and outputs current frame data based on the DCC correction value stored as the voltage code value. For example, as shown in FIG. 9, when the gray level is 0 in the previous frame data G _{n -1} and the gray level is 16 in the current frame data G _n , the voltage code corresponding to the gray value 20 is Stored in binary, the DCC converter 546 converts and outputs the current frame data based on the DCC correction value stored as the voltage code value. Here, the lookup table 542 may be represented by, for example, a 5 × 5 matrix. Row and column address indicates a previous frame data (G _{n -1)} and the current frame data (G _n) corresponding to a multiple of 16 gray-scale, respectively. At this time, the correction reference data for these frame data is stored at the intersection of the row and the column, that is, the hatched portion, and is generally a portion representing a still image.

When the DCC correction value or the correction reference data is stored in the form of a voltage code, unlike the conventional art of storing the correction reference data according to the set target gamma value as a gray scale value, the correction reference data may be stored in the form of a voltage code. Therefore, when the target gamma value is changed, when the gamma profile is changed according to the change of the input histogram, such as DGC, when the gamma profile is changed according to the liquid crystal panel or external temperature, such as gamma for temperature compensation, Even if it is partially or totally changed, the DCC correction value or the reference data for correction stored in the lookup table can be easily changed, so that an optimum liquid crystal response can be displayed without adding or changing a circuit. As a result, optimal video characteristics can be exhibited.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, the embodiments described above are to be understood in all respects as illustrative and not restrictive.

Frame data correction circuit and a liquid crystal display including the same according to an embodiment of the present invention, the DCC correction value or correction reference data stored in the look-up table in the form of a voltage code to add a separate circuit and Optimum liquid crystal response characteristics can be exhibited without changing.

Claims (7)

A frame memory for storing all or some bits of previous frame data for one frame; A lookup table for storing a DCC correction value in the form of a voltage code corresponding to some bits of current frame data and some bits of the previous frame data; And And a DCC converter configured to convert and output current frame data based on the DCC correction value. The method of claim 1, And a look-up table storing correction reference data used in the interpolation method for extracting the DCC correction value in the form of a voltage code. The method of claim 1, The voltage code is stored as an unsigned binary number. A liquid crystal panel including a plurality of unit pixels defined in a region where the plurality of gate lines and the data lines cross each other; A control signal generation block for generating a gate and a data control signal for driving the liquid crystal panel, and one frame for receiving at least one gray level value between two arbitrary gray level values by receiving image data from outside; An ACC block extending into a frame, a frame memory storing all or some bits of the frame data output from the ACC block for one frame, a voltage corresponding to some bits of the current frame data and some bits of the previous frame data A timing control unit including a frame data correction circuit including a lookup table storing a DCC correction value in a code form and a DCC converter converting and outputting current frame data based on the DCC correction value; A driving voltage generator configured to receive the control signal and generate a plurality of driving voltages; A gate driver which receives the driving voltage and applies it to the gate line; And And a data driver for applying a data voltage to the data line. The method of claim 4, wherein And a look-up table in which correction reference data used in the interpolation method for extracting the DCC correction value is stored in the form of a voltage code. The method of claim 4, wherein And the voltage code is stored as an unsigned binary number. The method of claim 4, wherein The ACC block may include a gray scale expansion unit which extends a predetermined number of bits of the image data; And And a gray scale reduction unit configured to reduce the number of bits of data in accordance with the number of bits that may be processed by the data driver.

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