KR20070079217A - LCD and its manufacturing method - Google Patents

Abstract

The liquid crystal display of the present invention and a method of manufacturing the same by using diffraction exposure removes the protrusions of the active pattern generated at the time of patterning the active pattern, the source / drain electrode and the data line at the time of forming the contact hole, and thus the wave noise. Providing a first substrate and a second substrate to simplify the manufacturing process by reducing the number of masks while improving the yield by preventing yield; Forming a gate electrode, a gate line, and a common line on the first substrate; Forming a first insulating film on the first substrate; Forming an active pattern, a source / drain electrode, a conductive layer pattern on the first substrate, and forming a storage electrode connected to the drain electrode; Forming a second insulating film on the first substrate; Removing the partial region of the second insulating layer to form a first contact hole exposing an inner side surface of the storage electrode, and patterning the conductive layer pattern to substantially cross the gate line to define a data line Forming; Forming a pixel electrode electrically connected to the drain electrode through the first contact hole, and forming a common electrode alternately disposed with the pixel electrode; And bonding the first substrate and the second substrate to each other.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME}

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG.

3 is a plan view illustrating a portion of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention.

4A to 4D are cross-sectional views sequentially showing manufacturing processes taken along lines IIIa-IIIa 'and IIIb-IIIb' of the array substrate shown in FIG.

5A through 5D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 3.

6A to 6E are cross-sectional views illustrating the second mask process illustrated in FIGS. 4B and 5B in detail.

7A and 7B are cross-sectional views specifically showing the third mask process shown in FIGS. 4C and 5C.

8 is a plan view illustrating a portion of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention.

9A to 9D are cross-sectional views sequentially showing manufacturing processes taken along lines VIIIa-VIIIa 'and VIIIb-VIIIb' of the array substrate shown in FIG. 8;

10A to 10D are plan views sequentially illustrating a manufacturing process of the array substrate illustrated in FIG. 8.

11A to 11E are cross-sectional views illustrating the second mask process shown in FIGS. 9B and 10B in detail.

12A and 12B are cross-sectional views specifically showing the third mask process shown in FIGS. 9C and 10C.

** Explanation of symbols for main parts of drawings **

108,208 Common electrode 108l, 208l: Common line

108L, 208L: Common electrode line 110,210: Array substrate

116,216 Gate line 117,217 Data line

118,218 pixel electrode 118L, 218L pixel electrode line

121,221 gate electrode 122,222 source electrode

123,223: Drain electrode 124 ', 224': Active pattern

The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a liquid crystal display device and a method for manufacturing the same by reducing the number of masks to simplify the manufacturing process and at the same time prevent the wave noise to improve the yield.

Recently, with increasing interest in information display and increasing demand for using a portable information carrier, a lightweight flat panel display (FPD), which replaces a conventional display device, a cathode ray tube (CRT), is used. The research and commercialization of Korea is focused on. In particular, the liquid crystal display (LCD) of the flat panel display device is an image representing the image using the optical anisotropy of the liquid crystal, is excellent in resolution, color display and image quality, and is actively applied to notebooks or desktop monitors have.

The liquid crystal display is largely composed of a color filter substrate as a first substrate, an array substrate as a second substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

In this case, a thin film transistor (TFT) is generally used as a switching element of the liquid crystal display, and an amorphous silicon thin film is used as a channel layer of the thin film transistor.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (ie, photolithography process) for fabricating an array substrate including a thin film transistor, a method of reducing the number of mask processes in terms of productivity is required. It is required.

Hereinafter, a structure of a general liquid crystal display device will be described in detail with reference to FIG. 1.

1 is an exploded perspective view schematically illustrating a general liquid crystal display.

As shown in the figure, the liquid crystal display device is largely a liquid crystal layer (liquid crystal layer) formed between the color filter substrate 5 and the array substrate 10 and the color filter substrate 5 and the array substrate 10 ( 30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 for implementing colors of red (R), green (G), and blue (B); A black matrix 6 that separates the sub-color filters 7 and blocks light passing through the liquid crystal layer 30, and a transparent common electrode that applies a voltage to the liquid crystal layer 30. 8)

In addition, the array substrate 10 may be arranged vertically and horizontally to define a plurality of gate lines 16 and data lines 17 and a plurality of gate lines 16 and data lines 17 that define a plurality of pixel regions P. The thin film transistor T, which is a switching element formed in the cross region, and the pixel electrode 18 formed on the pixel region P, are formed.

The color filter substrate 5 and the array substrate 10 configured as described above are joined to face each other by sealants (not shown) formed on the outer side of the image display area to form a liquid crystal display panel. 5) and the array substrate 10 are bonded through a bonding key (not shown) formed in the color filter substrate 5 or the array substrate 10.

2A to 2E are cross-sectional views sequentially illustrating a manufacturing process of an array substrate in the liquid crystal display shown in FIG. 1.

As shown in FIG. 2A, a gate electrode 21 made of a conductive metal material is formed on the substrate 10 using a photolithography process (first mask process).

Next, as illustrated in FIG. 2B, the first insulating film 15a, the amorphous silicon thin film, and the n + amorphous silicon thin film are sequentially deposited on the entire surface of the substrate 10 on which the gate electrode 21 is formed. An active pattern 24 made of an amorphous silicon thin film is formed on the gate electrode 21 by selectively patterning the amorphous silicon thin film and the n + amorphous silicon thin film by using a photolithography process (second mask process).

In this case, the n + amorphous silicon thin film pattern 25 patterned in the same form as the active pattern 24 is formed on the active pattern 24.

2C, a source electrode is formed on the active pattern 24 by depositing a conductive metal material on the entire surface of the substrate 10 and then selectively patterning the same by using a photolithography process (third mask process). And the drain electrode 23 are formed. In this case, the n + amorphous silicon thin film pattern formed on the active pattern 24 has a predetermined region removed through the third mask process to form an ohmic − between the active pattern 24 and the source / drain electrodes 22 and 23. An ohmic contact layer 25 'for ohmic contact is formed.

Next, as shown in FIG. 2D, a second insulating film 15b is deposited on the entire surface of the substrate 10 on which the source electrode 22 and the drain electrode 23 are formed, and then a photolithography process (fourth mask process). A portion of the second insulating layer 15b is removed to form a contact hole 40 exposing a portion of the drain electrode 23.

Finally, as shown in FIG. 2E, a transparent conductive metal material is deposited on the entire surface of the substrate 10 and then selectively patterned using a photolithography process (fifth mask process) to drain through the contact hole 40. The pixel electrode 18 electrically connected to the electrode 23 is formed.

As described above, fabrication of an array substrate including a thin film transistor requires a total of five photolithography processes to pattern a gate electrode, an active pattern, a source / drain electrode, a contact hole, a pixel electrode, and the like.

The photolithography process is a series of processes in which a pattern drawn on a mask is transferred onto a substrate on which a thin film is deposited to form a desired pattern. The photolithography process includes a plurality of processes such as photoresist coating, exposure, and development. As a result, many photolithography processes have many problems, such as lowering the production yield and increasing the probability of defects in the formed thin film transistors.

In particular, a mask designed to form a pattern is very expensive, and as the number of masks applied to the process increases, the manufacturing cost of the liquid crystal display device increases in proportion.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a liquid crystal display device having a reduced number of masks used for manufacturing a thin film transistor and a method of manufacturing the same.

Another object of the present invention is to provide a liquid crystal display device and a method of manufacturing the same, which solves wave noise defects and improves device reliability and yield.

Other objects and features of the present invention will be described in the configuration and claims of the invention described below.

In order to achieve the above object, the manufacturing method of the liquid crystal display device of the present invention comprises the steps of providing a first substrate and a second substrate; Forming a gate electrode, a gate line, and a common line on the first substrate; Forming a first insulating film on the first substrate; Forming an active pattern, a source / drain electrode, a conductive layer pattern on the first substrate, and forming a storage electrode connected to the drain electrode; Forming a second insulating film on the first substrate; Removing the partial region of the second insulating layer to form a first contact hole exposing an inner side surface of the storage electrode, and patterning the conductive layer pattern to substantially cross the gate line to define a data line Forming; Forming a pixel electrode electrically connected to the drain electrode through the first contact hole, and forming a common electrode alternately disposed with the pixel electrode; And bonding the first substrate and the second substrate to each other.

The liquid crystal display device of the present invention is formed on the first substrate, the gate electrode, the gate line and the common line made of the first conductive material; A first insulating film formed on the first substrate; A source / drain electrode and a data line formed on the first substrate and formed of an active pattern made of an amorphous silicon thin film and a second conductive material; An amorphous silicon thin film pattern formed under the data line in the shape of the data line and made of the amorphous silicon thin film; A second insulating film formed on the first substrate; A common electrode and a pixel electrode disposed alternately on the first substrate and made of a third conductive material; And a second substrate bonded to and opposed to the first substrate.

Hereinafter, exemplary embodiments of a liquid crystal display and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view illustrating a part of an array substrate of a liquid crystal display according to a first exemplary embodiment of the present invention. In the actual array substrate, N gate lines and M data lines cross each other, and MxN pixels exist, but the description is simplified. In the drawings, one pixel is shown.

In this case, the present embodiment describes a liquid crystal display device of an in-plane switching (IPS) method in which the liquid crystal molecules are driven in a horizontal direction with respect to the substrate to improve the viewing angle, for example, but the present invention is not limited thereto. The present invention can also be applied to a twisted nematic (TN) type liquid crystal display device.

As shown in the figure, a gate line 116 and a data line 117 are formed on the array substrate 110 of the first embodiment to be arranged horizontally and horizontally on the substrate 110 to define a pixel region. A thin film transistor, which is a switching element, is formed in an intersection area between the line 116 and the data line 117.

The thin film transistor includes a gate electrode 121 constituting part of the gate line 116, a source electrode 122 connected to the data line 117, and a drain electrode 123 connected to the storage electrode 123l. have. In addition, the thin film transistor is formed by a first insulating film (not shown) for insulating the gate electrode 121 and the source / drain electrodes 122 and 123 and a gate voltage supplied to the gate electrode 121. It includes an active pattern (not shown) for forming a conductive channel between the electrode 122 and the drain electrode 123.

In this case, the source electrode 122 is connected to the data line 117 to form part of the data line 117, and the drain electrode 123 connected to the storage electrode 123l is a second insulating film (not shown). ) Is electrically connected to the pixel electrode line 118L and the pixel electrode 118 through the first contact hole 140a formed in the first contact hole 140a.

The common electrode 108 and the pixel electrode 118 for generating a transverse electric field are alternately arranged in the pixel region. In this case, the pixel electrode 118 is connected to the pixel electrode line 118L arranged in parallel with the gate line 116. In addition, the common electrode 108 is connected to the common electrode line 108L substantially parallel to the gate line 116 and is substantially connected to the gate line 116 through the second contact hole 140b. It is electrically connected to the common line 108l arranged in parallel.

The common line 108l is connected to first connection lines 108a and 108a 'arranged at both sides of the data line 117, that is, at the left and right edges of the pixel area. The first connection lines 108a and 108a 'are connected to each other by a second connection line 108b arranged at one side of the gate line 116.

In this case, the first connection lines 108a and 108a 'are arranged to be substantially parallel to the data line 117, and the second connection lines 108b are arranged to be substantially parallel to the gate line 116. It is.

The storage electrode 123l overlaps a portion of the second connection line 108b below the first insulating layer to form a storage capacitor. The storage capacitor serves to maintain a constant voltage applied to the liquid crystal capacitor until the next signal. That is, the pixel electrode 118 together with the common electrode 108 forms a liquid crystal capacitor. In general, the voltage applied to the liquid crystal capacitor is not maintained until the next signal comes in and leaks out. Therefore, in order to maintain the applied voltage, the storage capacitor must be connected to the liquid crystal capacitor.

In addition to maintaining the signal, the storage capacitor has effects such as stabilization of gray scale display and reduction of flicker and afterimage.

The array substrate 110 according to the present embodiment configured as described above may be manufactured through a total of four mask processes by forming active patterns, source / drain electrodes 122 and 123, and data lines 117 using diffraction exposure.

In addition, in the present embodiment, in order to form the data line 117, a conductive layer pattern is first formed to protrude up to the first connection line 108a. When the first contact hole 140a and the second contact hole 140b are formed, the final data line 117 is patterned by disconnecting the protrusion of the conductive layer pattern protruding above the first connection line 108a. To form. In this case, since the active pattern under the data line 117 is also patterned in the form of the side surface of the data line 117, it is possible to prevent wave noise, which will be described in detail through the following manufacturing process of the liquid crystal display. .

For reference, reference numeral 117 ′ represents the dummy pattern formed of the conductive film pattern and separated from the data line 117 when the data line 117 is patterned.

4A to 4D are cross-sectional views sequentially illustrating a manufacturing process along lines IIIa-IIIa 'and IIIb-IIIb' of the array substrate illustrated in FIG. 3, and FIGS. 5A to 5D are views of the array substrate illustrated in FIG. 3. It is a top view which shows a manufacturing process sequentially.

4A to 4D sequentially show the manufacturing process along the line IIIa-IIIa 'of the array substrate shown in FIG. 3, and sequentially show the manufacturing process along the IIIb-IIIb' line to the right.

As shown in FIGS. 4A and 5A, the gate line 116, the common line 108l, and the first connection line 108a including the gate electrode 121 on the substrate 110 made of a transparent insulating material such as glass. , 108a ') and the second connection line 108b. In this case, as described above, the common line 108l is connected to the first connection lines 108a and 108a 'arranged at the left and right edges of the pixel area, and the first connection lines 108a and 108a' are connected to each other. ) Are connected to each other by the second connection line 108b arranged at one side of the gate line 116.

In this case, the first connection lines 108a and 108a 'are arranged to be substantially parallel to the data lines, and the second connection lines 108b are arranged to be substantially parallel to the gate lines 116.

The gate electrode 121, the gate line 116, the common line 108l, the first connection lines 108a and 108a 'and the second connection line 108b are formed by depositing a first conductive layer on the entire surface of the substrate 110. It is then formed by patterning through a photolithography process (first mask process).

The first conductive layer may include aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum (Mo), or the like. The same low resistance opaque conductive material can be used. In addition, the gate electrode 121, the gate line 116, the common line 108l, the first connection lines 108a and 108a ', and the second connection line 108b are formed by stacking two or more low-resistance conductive materials. It can also be formed into a multi-layered structure.

Next, as shown in FIGS. 4B and 5B, the gate electrode 121, the gate line 116, the common line 108l, the first connection lines 108a and 108a 'and the second connection line 108b are shown. ), The first insulating film 115a, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are sequentially deposited on the entire surface of the substrate 110 on which the substrate 110 is formed, and then the photolithography process (second mask process) is performed. By selectively patterning the thin film, the n + amorphous silicon thin film, and the second conductive film, an active pattern 124 'made of the amorphous silicon thin film is formed on the gate electrode 121 and a source electrode 122 made of the second conductive film. ) And the drain electrode 123 are formed. In this case, the third conductive layer pattern 130 ′ ″ formed of the second conductive layer and later patterned into the data line is formed in a direction substantially perpendicular to the gate line 116.

In this case, the third conductive layer pattern 130 ′ ″ may be formed to protrude so that at least one portion of the third conductive layer pattern 130 ′ ″ overlaps the portions of the first connection lines 108a and 108a ′. Although a part of the conductive film pattern 130 ′ ″ protrudes and overlaps with a part of the first connection line 108a on the left side, the present invention is not limited thereto.

The n + amorphous silicon thin film is formed on the active pattern 124 'and is patterned in the same shape as the source / drain electrodes 122 and 123 to form a predetermined region and the source / drain of the active pattern 124'. An ohmic contact layer 125 ″ ″ that ohmic-contacts the electrodes 122, 123 is formed.

At this time, an amorphous silicon thin film pattern 124 "made of the same amorphous silicon thin film as the active pattern 124 'is formed under the third conductive film pattern 130'", and reference numeral 125 "denotes the n + An n + amorphous silicon thin film pattern formed of an amorphous silicon thin film and patterned in the same form as the third conductive film pattern 130 ′ ″ is shown.

The active pattern 124 ′ and the amorphous silicon thin film pattern 124 ″ are patterned so that side surfaces thereof protrude from the source / drain electrodes 122 and 123 and the third conductive layer pattern 130 ′ ″, respectively. This is the result of patterning using diffraction exposure.

As described above, in this embodiment, the active pattern 124 ', the source / drain electrodes 122 and 123, and the third conductive film pattern 130' "are simultaneously used in one mask process (second mask process) using diffraction exposure. The second mask process will be described in detail with reference to the accompanying drawings.

6A to 6E are cross-sectional views illustrating in detail a process of simultaneously forming an active pattern, a source / drain electrode, and a third conductive film pattern in FIGS. 4B and 5B, and sequentially illustrating a second mask process of the present embodiment. have.

As shown in FIG. 6A, the substrate 110 on which the gate electrode 121, the gate line 116, the common line 108l, the first connection lines 108a and 108a ', and the second connection line 108b are formed. The first insulating film 115a, the amorphous silicon thin film 124, the n + amorphous silicon thin film 125, and the second conductive film 130 are sequentially deposited on the entire surface.

In this case, a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum and molybdenum alloy may be used as the second conductive layer 130.

Thereafter, the photoresist film 170 made of a photoresist such as photoresist is formed on the entire surface of the substrate 110, and then light is selectively irradiated onto the photoresist film 170 through the diffraction mask 180 of the present embodiment.

In this case, the diffraction mask 180 used in the present embodiment is applied with a transmission region I and a slit pattern that transmit all of the irradiated light so that only a part of the light is transmitted and a portion of the slit region II and all of the irradiated light are blocked. The blocking region III is provided to block the light, and only the light passing through the diffraction mask 180 is irradiated to the photosensitive film 170.

Subsequently, after the photoresist film 170 exposed through the diffraction mask 180 is developed, light is blocked or partially blocked through the blocking region III and the slit region II, as shown in FIG. 6B. The photoresist patterns 170a to 170d having a predetermined thickness remain in the region, and the photoresist layer is completely removed in the transmission region I through which all the light is transmitted, thereby exposing the surface of the second conductive layer 130.

In this case, the first photoresist pattern 170a to the third photoresist pattern 170c formed through the blocking region III are formed thicker than the fourth photoresist pattern 170d formed in the slit region II. In addition, the photoresist film is completely removed in the region where all the light is transmitted through the transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto, and a negative photoresist may be used.

Next, when the second conductive layer 130 formed below is patterned using the photoresist patterns 170a to 170d formed as the mask, the second layer is formed on the substrate 110 as illustrated in FIG. 6C. The first conductive film pattern 130 ′ and the second conductive film pattern 130 ″ formed of the conductive film are formed.

The amorphous silicon thin film and the n + amorphous silicon thin film under the first conductive film pattern 130 ′ and the second conductive film pattern 130 ″ may be selectively removed using the photoresist pattern 170a to 170d as a mask. In this case, an active pattern 124 ′ consisting of the amorphous silicon thin film and an n + amorphous silicon thin film and a first n + amorphous silicon thin film pattern 125 ′ are formed in a predetermined region on the gate electrode 121. An amorphous silicon thin film pattern 124 ″ and a second n + amorphous silicon overlapping a portion of the first connection line 108 a and formed of an amorphous silicon thin film and an n + amorphous silicon thin film in a predetermined region above the first connection line 108 a. The thin film pattern 125 "is formed.

When an ashing process is performed to remove a portion of the photoresist patterns 170a to 170d, as illustrated in FIG. 6D, a predetermined area of the active pattern 124 ′, that is, diffraction exposure is applied. The fourth photoresist pattern of the slit region II is completely removed to expose the surface of the first conductive layer pattern 130 ′.

In this case, the first photoresist pattern to the third photoresist pattern correspond to the blocking region III by the fifth photoresist pattern 170a 'through the seventh photoresist pattern 170c', in which the thickness of the fourth photoresist pattern is removed. It remains only in a predetermined area. Here, the fifth photoresist pattern 170a ′ to the seventh photoresist pattern 170c ′ have a form in which a part of a side surface thereof is removed through the ashing process.

Thereafter, as shown in FIG. 6E, a predetermined region (ie, a channel region) of the active pattern 124 ′ is formed by using the remaining fifth photoresist pattern 170a ′ through seventh photoresist pattern 170c ′ as a mask. When the first conductive layer pattern is selectively etched, the source electrode 122 and the drain electrode 123 formed of the second conductive layer are formed on the gate electrode 121. In this case, a portion of the source electrode 122 extending in the pixel area direction constitutes the storage electrode 123l.

In this case, the first n + amorphous silicon thin film pattern formed on the active pattern 124 'is patterned to form ohmic contact between the active pattern 124' and the source / drain electrodes 122 and 123. (125 '").

In addition, the second conductive film pattern 130 ″ and the second n + amorphous silicon thin film pattern 125 ″ on the amorphous silicon thin film pattern 124 ″ are patterned in the shape of the seventh photoresist pattern 170c ′. The third conductive film pattern 130 ′ ″ and the third n + amorphous silicon thin film pattern 125 ″ ″ are formed.

As described above, when the active pattern 124 ', the source / drain electrodes 122 and 123, and the third conductive layer pattern 130' '' are simultaneously patterned using diffraction exposure, the source / The side surfaces of the active pattern 124 ′ under the drain electrodes 122 and 123 and the amorphous silicon thin film pattern 124 ″ under the third conductive layer pattern 130 ′ ″ may be formed on the source / drain electrodes 122 and 123. And patterned to protrude relative to the third conductive film pattern 130 ″ ″.

4C and 5C, the second insulating layer 115b is formed on the entire surface of the substrate 110 on which the source electrode 122, the drain electrode 123, and the third conductive layer pattern 130 ′ ″ are formed. After the deposition, the first contact hole 140a exposing a part of the side surface of the storage electrode 123l and the second contact exposing a part of the common line 108l through a photolithography process (third mask process). In this case, the protruding side surface of the third conductive film pattern is disconnected by the hole H formed in the longitudinal direction of the first connection line 108a to finally form the third conductive film pattern. The data line 117 and the dummy pattern 117 'are formed.

That is, as shown in FIG. 7A, the second insulating film 115b is deposited on the entire surface of the substrate 110 on which the source electrode 122, the drain electrode 123, and the third conductive layer pattern 130 ′ ″ are formed. Thereafter, a predetermined photoresist pattern 170 'is formed on the second insulating film 115b through a photolithography process (third mask process).

As shown in FIG. 7B, the second insulating film 115b, the storage electrode 123 ′, the ohmic contact layer 125 ′ ″ and the active pattern 124 are formed by using the photoresist pattern 170 ′ as a mask. The first contact hole 140a exposing a portion of the side surface of the storage electrode 123 'is formed by etching a portion of the region'. 'The second insulating layer is formed by using the photoresist pattern 170' as a mask. 115b), a portion of the third conductive film pattern, the third n + amorphous silicon thin film pattern 125 " " and the amorphous silicon thin film pattern 124 " are etched to form the third conductive film pattern with the data line 117. A hole H which is disconnected in the pattern 117 'is formed in the longitudinal direction of the first connection line 108a. In this case, an upper portion of the common line 108l may be formed on the storage electrode 123 ′ (or the third conductive layer pattern) and the ohmic contact layer 125 ′ ″ (or the third n + amorphous silicon thin film pattern 125 ″ ”. ) And the first insulating film 115a on the common line 108l when the active pattern 124 ′ (or the amorphous silicon thin film pattern 124 ″) is etched. The second contact hole 140b exposing a part of the surface is formed.

In this case, the amorphous silicon thin film pattern 124 ″ under the data line 117 is also patterned as the side shape of the data line 117, and the side surfaces of the data line 117 and the amorphous silicon thin film pattern 124 ″. Is exposed to the outside through the hole (H).

As described above, in the present exemplary embodiment, even though the active pattern 124 ', the source / drain electrodes 122 and 123, and the data line 117 are formed using diffraction exposure, the amorphous silicon thin film pattern 124 under the data line 117 is formed. ") Does not protrude from the side of the data line 117, so that the wave noise problem due to signal interference between the existing amorphous silicon thin film pattern 124" and the common electrode 108 adjacent to the data line 117 is solved. It can be solved.

4D and 5D, the first contact hole 140a is deposited by selectively depositing a transparent conductive material on the entire surface of the substrate 110 and then selectively patterning the same by using a photolithography process (fourth mask process). A pixel electrode line 118L electrically connected to the storage electrode 123l through a second electrode; and a common electrode line 108L electrically connected to the common line 108l through the second contact hole 140b. ).

In this case, a portion of the pixel electrode line 118L and the common electrode line 108L extend into the pixel region to form the pixel electrode 118 and the common electrode 108, respectively, and the pixel electrode 118 and the common electrode 108 are alternately arranged in the pixel region to generate a transverse electric field in the pixel region.

In this case, the transparent conductive material includes a conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO).

In addition, the pixel electrode 118 is electrically connected to the lower dummy pattern 117 ′ having side surfaces exposed through the hole H, and the storage electrode 123l is formed between the first insulating layer 115a. The storage capacitor overlaps with a portion of the second connection line 108b below.

The array substrate 110 configured as described above is bonded to face the color filter substrate (not shown) by a sealant (not shown) formed outside the image display area to form a liquid crystal display panel. The bonding of the color filter substrate is performed through a bonding key (not shown) formed on the array substrate 110 and the color filter substrate.

At this time, in the first embodiment, the dummy pattern disconnected from the data line remains on the first connection line when the data line is patterned, but the present invention is not limited thereto. The data line may be patterned so as not to be described in detail with reference to the following second embodiment.

FIG. 8 is a plan view illustrating a part of an array substrate of a liquid crystal display according to a second exemplary embodiment of the present invention. In the actual array substrate, N gate lines and M data lines cross each other to provide MxN pixels, but the description is simplified. In the drawings, one pixel is shown.

As shown in the figure, a gate line 216 and a data line 217 are formed in the array substrate 210 of the second embodiment, which are arranged horizontally and horizontally on the substrate 210 to define a pixel region. A thin film transistor, which is a switching element, is formed in an intersection area between the line 216 and the data line 217.

The thin film transistor includes a gate electrode 221 constituting a portion of the gate line 216, a source electrode 222 connected to the data line 217, and a drain electrode 223 connected to the storage electrode 223l. have. In addition, the thin film transistor includes a first insulating film (not shown) for insulating the gate electrode 221 and the source / drain electrodes 222 and 223 and the source electrode by a gate voltage supplied to the gate electrode 221. An active pattern (not shown) forming a conductive channel between the 222 and the drain electrode 223 is included.

In this case, the source electrode 222 is connected to the data line 217 to form part of the data line 217, and the drain electrode 223 connected to the storage electrode 223l is a second insulating film (not shown). ) Is electrically connected to the pixel electrode line 218L and the pixel electrode 218 through the first contact hole 240a formed in the first contact hole 240a.

The common electrode 208 and the pixel electrode 218 for generating a transverse electric field are alternately arranged in the pixel region. In this case, the pixel electrode 218 is connected to the pixel electrode line 218L substantially parallel to the gate line 216. In addition, the common electrode 208 is connected to the common electrode line 208L arranged in parallel with the gate line 216, and has a first connection line (B) below it through the second contact hole 240b. 208a) is electrically connected.

In this case, the common line 208l is arranged substantially parallel to the gate line 216, and the common line 208l is arranged at both sides of the data line 217, that is, at the left and right edges of the pixel area. It is connected to the first connection lines 208a and 208a '. In addition, the first connection lines 208a and 208a 'on the left and right sides of the pixel region are connected to each other by a second connection line 208b arranged at one side of the gate line 216.

In this case, the first connection lines 208a and 208a 'are arranged to be substantially parallel to the data line 217, and the second connection lines 208b are arranged to be substantially parallel to the gate line 216. It is.

The storage electrode 223l overlaps a portion of the second connection line 208b below with the first insulating layer therebetween to form a storage capacitor.

The array substrate 210 according to the present embodiment configured as described above may be manufactured through a total of four mask processes by forming active patterns, source / drain electrodes 222 and 223, and data lines 217 using diffraction exposure.

In addition, in the present exemplary embodiment, in order to form the data line 217, a conductive layer pattern is first formed to protrude up to the first connection line 208a. In addition, when the first contact hole 240a is formed, the final data line 217 is formed by forming the second contact hole 240b such that the protrusion of the conductive layer pattern protruding above the first connection line 108a is removed. Done. In this case, since the active pattern under the data line 217 is also patterned in the form of the side surface of the data line 217, it is possible to prevent wave noise, which will be described in detail through the following manufacturing process of the liquid crystal display.

9A to 9D are cross-sectional views sequentially illustrating a manufacturing process along lines VIIIa-VIIIa 'and VIIIb-VIIIb' of the array substrate illustrated in FIG. 8, and FIGS. 10A to 10D are views of the array substrate illustrated in FIG. 8. It is a top view which shows a manufacturing process sequentially.

10A to 10D sequentially show the manufacturing process along the line VIIIa-VIIIa 'of the array substrate shown in FIG. 8, and sequentially show the manufacturing process along the line VIIIb-VIIIb' on the right side.

9A and 10A, a gate line 216, a common line 208l, and a first connection line 208a including a gate electrode 221 on a substrate 210 made of a transparent insulating material such as glass. 208a ') and a second connection line 208b. In this case, as described above, the common line 208l is connected to the first connection lines 208a and 208a 'arranged at the left and right edges of the pixel area, and the first connection lines 208a and 208a' are connected to each other. ) Are connected to each other by the second connection line 208b arranged on one side of the gate line 216.

In this case, the first connection lines 208a and 208a 'are arranged to be substantially parallel to the data line, and the second connection lines 208b are arranged to be substantially parallel to the gate line 216.

The gate electrode 221, the gate line 216, the common line 208l, the first connection lines 208a and 208a ′, and the second connection line 208b are formed by depositing a first conductive layer on the entire surface of the substrate 210. It is then formed by patterning through a photolithography process (first mask process).

Next, as illustrated in FIGS. 9B and 10B, the gate electrode 221, the gate line 216, the common line 208l, the first connection lines 208a and 208a ′, and the second connection line 208b are illustrated. ), The first insulating film 215a, the amorphous silicon thin film, the n + amorphous silicon thin film and the second conductive film are sequentially deposited on the entire surface of the substrate 210 on the formed substrate 210, and then the amorphous silicon is formed by using a photolithography process (second mask process). By selectively patterning the thin film, the n + amorphous silicon thin film, and the second conductive film, an active pattern 224 'made of the amorphous silicon thin film is formed on the gate electrode 221 and a source electrode 222 made of the second conductive film. ) And the drain electrode 223 are formed. In this case, a third conductive layer pattern 230 ″ ″ formed of the second conductive layer and later patterned as a data line is formed in a direction substantially perpendicular to the gate line 216.

In this case, the third conductive layer pattern 230 ′ ″ may be formed to protrude so that at least one portion thereof overlaps with a portion of the first connection lines 208a and 208a ′. Although a part of the conductive film pattern 230 ′ ″ protrudes and overlaps a part of the first connection line 208a on the left side, the present invention is not limited thereto.

The n + amorphous silicon thin film is formed on the active pattern 224 ', and is patterned in the same form as the source / drain electrodes 222 and 223 to form a predetermined region and the source / drain of the active pattern 224'. An ohmic contact layer 225 ′ ″ that ohmic-contacts the electrodes 222, 223 is formed.

In this case, an amorphous silicon thin film pattern 224 ″ formed of the same amorphous silicon thin film as the active pattern 224 ′ is formed below the third conductive film pattern 230 ″ ″, and reference numeral 225 ″ denotes n +. An n + amorphous silicon thin film pattern formed of an amorphous silicon thin film and patterned in the same shape as the third conductive film pattern 230 ′ ″ is shown.

The active pattern 224 ′ and the amorphous silicon thin film pattern 224 ″ are patterned to protrude side surfaces from the source / drain electrodes 222 and 223 and the third conductive layer pattern 230 ′ ″, respectively. This is the result of patterning using diffraction exposure.

As described above, in the present embodiment, the active pattern 224 ', the source / drain electrodes 222 and 223, and the third conductive film pattern 230' "are simultaneously used in one mask process (second mask process) using diffraction exposure. The second mask process will be described in detail with reference to the accompanying drawings.

11A through 11E are cross-sectional views illustrating in detail a process of simultaneously forming an active pattern, a source / drain electrode, and a third conductive film pattern in FIGS. 9B and 10B, and sequentially illustrating a second mask process of the present embodiment. .

As shown in FIG. 11A, the substrate 210 on which the gate electrode 221, the gate line 216, the common line 208l, the first connection lines 208a and 208a ′, and the second connection line 208b are formed. The first insulating film 215a, the amorphous silicon thin film 224, the n + amorphous silicon thin film 225, and the second conductive film 230 are sequentially deposited on the entire surface.

Thereafter, a photoresist film 270 made of a photoresist such as photoresist is formed on the entire surface of the substrate 210, and then light is selectively irradiated onto the photoresist 270 through the diffraction mask 280 of the present embodiment.

In this case, the diffraction mask 280 used in the present embodiment is applied with a transmission region I and a slit pattern that transmit all of the irradiated light so that only a part of the light is transmitted and a portion of the slit region II and all of the irradiated light are blocked. A blocking region (III) for blocking is provided, and only the light passing through the diffraction mask 280 is irradiated onto the photosensitive film 270.

Subsequently, after developing the photosensitive film 270 exposed through the diffraction mask 280, as shown in FIG. 11B, light is blocked or partially blocked through the blocking region III and the slit region II. The photoresist patterns 270a to 270d having a predetermined thickness remain in the exposed region, and the photoresist layer is completely removed in the transmission region I through which all the light is transmitted, thereby exposing the surface of the second conductive layer 230.

In this case, the first photoresist pattern 270a to the third photoresist pattern 270c formed through the blocking region III are formed thicker than the fourth photoresist pattern 270d formed in the slit region II. In addition, the photosensitive film is completely removed in the region where all the light is transmitted through the transmission region I. This is because a positive photoresist is used, and the present invention is not limited thereto, and a negative photoresist may be used. .

Next, when the second conductive layer 230 formed below the pattern is formed by using the photoresist patterns 270a to 270d formed as described above, the second layer is formed on the substrate 210 as illustrated in FIG. 11C. The first conductive film pattern 230 ′ and the second conductive film pattern 230 ″ formed of the conductive film are formed.

The amorphous silicon thin film and the n + amorphous silicon thin film under the first conductive film pattern 230 ′ and the second conductive film pattern 230 ″ may be selectively removed using the photosensitive film patterns 270a to 270d as masks. In this case, an active pattern 224 ′ consisting of the amorphous silicon thin film and an n + amorphous silicon thin film and a first n + amorphous silicon thin film pattern 225 ′ are formed in a predetermined region on the gate electrode 221. An amorphous silicon thin film pattern 224 ″ and a second n + amorphous silicon overlapping a portion of the first connection line 208 a and formed of an amorphous silicon thin film and an n + amorphous silicon thin film in a predetermined region above the first connection line 208a. The thin film pattern 225 "is formed.

Then, when the ashing process of removing a portion of the photoresist patterns 270a to 270d is performed, as shown in FIG. 11D, an upper portion of the active pattern 224 ′, that is, a slit region to which diffraction exposure is applied ( The fourth photoresist layer pattern of II) is completely removed to expose the surface of the first conductive layer pattern 230 ′.

In this case, the first photoresist pattern to the third photoresist pattern correspond to the blocking region III by the fifth photoresist pattern 270a 'through the seventh photoresist pattern 270c', in which the thickness of the fourth photoresist pattern is removed. It remains only in a predetermined area. Here, the fifth photoresist pattern 270a ′ to the seventh photoresist pattern 270c ′ have a form in which a part of a side surface thereof is removed through the ashing process.

Thereafter, as shown in FIG. 11E, a predetermined region (ie, a channel region) of the active pattern 224 ′ is formed by using the remaining fifth photoresist pattern 270a ′ through seventh photoresist pattern 270c ′ as a mask. When the first conductive layer pattern is selectively etched, a source electrode 222 and a drain electrode 223 formed of the second conductive layer are formed on the gate electrode 221. In this case, a part of the source electrode 222 extending in the pixel region direction constitutes the storage electrode 223l.

In this case, the first n + amorphous silicon thin film pattern formed on the active pattern 224 ′ is patterned to form ohmic contact between the active pattern 224 ′ and the source / drain electrodes 222 and 223. (225 '").

In addition, the second conductive film pattern 230 ″ and the second n + amorphous silicon thin film pattern 225 ″ formed on the amorphous silicon thin film pattern 224 ″ are patterned in the form of the seventh photoresist pattern 270c ′. The third conductive film pattern 230 ′ ″ and the third n + amorphous silicon thin film pattern 225 ″ ″ are formed.

As such, when the active pattern 224 ', the source / drain electrodes 222 and 223, and the third conductive layer pattern 230' ″ are simultaneously patterned using diffraction exposure, the source / Sides of the active pattern 224 ′ under the drain electrodes 222 and 223 and the amorphous silicon thin film pattern 224 ″ under the third conductive layer pattern 230 ′ ″ may be formed on the source / drain electrodes 222 and 223. And patterned to protrude relative to the third conductive film pattern 230 ′ ″.

Thereafter, as shown in FIGS. 9C and 10C, the second insulating layer 215b is disposed on the entire surface of the substrate 210 on which the source electrode 222, the drain electrode 223, and the third conductive layer pattern 230 ′ ″ are formed. After the deposition, the first contact hole 240a is formed through the photolithography process (third mask process) to expose a portion of the side surface of the storage electrode 2223. In this case, the third mask process forms the first contact hole 240a. The protruding side surface of the third conductive film pattern is removed by the hole H formed in the longitudinal direction of the first connection line 208a and at the same time, a second contact hole 240b exposing a part of the first connection line 208a. ) Is formed.

That is, as shown in FIG. 12A, the second insulating layer 215b is deposited on the entire surface of the substrate 210 on which the source electrode 222, the drain electrode 223, and the third conductive layer pattern 230 ′ ″ are formed. Thereafter, a predetermined photosensitive film pattern 270 'is formed on the second insulating film 215b through a photolithography process (third mask process), wherein the photosensitive film pattern 270' of the second embodiment is formed in the first embodiment. By patterning the width of the hole H to be wider than that of the photoresist pattern, the protrusion of the third conductive layer pattern 230 ′ ″ on the first connection line 208a may be completely removed through an etching process to be described later. It becomes possible. That is, the photosensitive film pattern 270 ′ of the present exemplary embodiment is patterned to completely expose the protrusion of the third conductive film pattern 230 ′ ″ on the first connection line 208a.

12B, the second insulating layer 215b, the storage electrode 223 ′, the ohmic contact layer 225 ′ ″, and the active pattern 224 are formed by using the photoresist pattern 270 ′ as a mask. The first contact hole 240a exposing a portion of the side surface of the storage electrode 223 'is formed by etching a portion of the'. 'The second insulating film (see below) is formed using the photoresist pattern 270' as a mask. 215b), a portion of the third conductive layer pattern, the third n + amorphous silicon thin film pattern 225 " and the amorphous silicon thin film pattern 224 " are etched to form a first insulating film (on top of the first connection line 208a). A hole H exposing 215a is formed.

Here, the hole (H) is formed in the longitudinal direction of the first connection line (208a), at this time, the formation of the hole (H) of the third conductive film pattern protruding above the first connection line (208a) By removing the protrusion, a data line 217 formed of the third conductive layer pattern is formed. In this case, the region D between the side surface of the amorphous silicon thin film pattern 224 ″ under the third conductive film pattern and the side surface of the photoresist film pattern 270 ′ above the third conductive film pattern, the third n + amorphous layer The first insulating layer 215a of the region D is etched while the silicon thin film pattern 225 ″ ″ and the amorphous silicon thin film pattern 224 ″ are etched to expose a portion of the first connection line 208a. 2 contact holes 240b are formed.

In addition, the amorphous silicon thin film pattern 224 ″ under the data line 217 is patterned in the form of the side of the data line 217, and the side surfaces of the data line 217 and the amorphous silicon thin film pattern 224 ″. Is exposed to the outside through the hole (H).

Thereafter, as illustrated in FIGS. 9D and 10D, a transparent conductive material is deposited on the entire surface of the substrate 210 and then selectively patterned using a photolithography process (fourth mask process) to form the first contact hole 240a. A pixel electrode line 218L electrically connected to the storage electrode 223l through the second electrode, and a common electrode 208 electrically connected to the first connection line 208a through the second contact hole 240b. ).

In this case, a part of the pixel electrode line 218L extends into the pixel region to form the pixel electrode 218, and the common electrode 208 is connected to the common electrode line 208L formed on the common line 208l. Will be connected.

The pixel electrode 218 and the common electrode 208 are alternately arranged in the pixel region to generate a transverse electric field in the pixel region.

In addition, the storage electrode 223l overlaps a portion of the lower second connection line 208b with the first insulating layer 215a therebetween to form a storage capacitor.

The array substrate 210 configured as described above is bonded to face the color filter substrate (not shown) by a sealant (not shown) formed at the outer side of the image display area to form a liquid crystal display panel. The bonding of the color filter substrate is performed through a bonding key (not shown) formed on the array substrate 210 and the color filter substrate.

In the present embodiment, an amorphous silicon thin film transistor using an amorphous silicon thin film as the channel layer is described as an example. However, the present invention is not limited thereto. do.

In addition, the present invention can be used not only in liquid crystal display devices but also in other display devices fabricated using thin film transistors, for example, organic light emitting display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors. have.

Many details are set forth in the foregoing description but should be construed as illustrative of preferred embodiments rather than to limit the scope of the invention. Therefore, the invention should not be defined by the described embodiments, but should be defined by the claims and their equivalents.

As described above, the liquid crystal display and the method of manufacturing the same according to the present invention reduce the number of masks used in the manufacturing of the thin film transistor by simultaneously patterning the active pattern, the source / drain electrodes and the data line using diffraction exposure, thereby reducing the manufacturing process and cost. Provides the effect of reducing

In addition, the manufacturing method of the liquid crystal display according to the present invention can prevent wave noise by patterning the active pattern under the data line in the form of the side of the data line when forming the contact hole. As a result, the image quality is improved and the yield is improved by removing defects.

Claims (48)

Providing a first substrate and a second substrate; Forming a gate electrode, a gate line, and a common line on the first substrate; Forming a first insulating film on the first substrate; Forming an active pattern, a source / drain electrode, a conductive layer pattern on the first substrate, and forming a storage electrode connected to the drain electrode; Forming a second insulating film on the first substrate; Removing the partial region of the second insulating layer to form a first contact hole exposing an inner side surface of the storage electrode, and patterning the conductive layer pattern to substantially cross the gate line to define a data line Forming; Forming a pixel electrode electrically connected to the drain electrode through the first contact hole, and forming a common electrode alternately disposed with the pixel electrode; And And attaching the first substrate and the second substrate to each other. The method of claim 1, wherein the gate electrode forms part of the gate line. The method of claim 1, further comprising forming a first connection line connected to the common line and arranged substantially parallel to the data line. 4. The method of claim 3, further comprising forming a second connection line connected to the first connection line and arranged substantially parallel to the gate line. The method of claim 4, wherein the common electrode, the first connection line, and the second connection line are formed through substantially the same mask process. The method of claim 1, wherein the forming of the active pattern, the source / drain electrodes, and the conductive layer pattern is performed. Forming an amorphous silicon thin film, an n + amorphous silicon thin film, and a conductive film on the first substrate; A first photoresist pattern, a second photoresist pattern, and a third photoresist pattern having a first thickness are formed in the first region, the second region, and the third region of the first substrate, respectively, and have a second thickness in the fourth region. Forming a fourth photoresist pattern; The amorphous silicon thin film, the n + amorphous silicon thin film, and the conductive film are selectively removed by using the first to fourth photoresist patterns as masks, thereby forming the amorphous silicon thin films in the first, second and fourth regions. A first n + amorphous silicon thin film pattern consisting of an active pattern, the n + amorphous silicon thin film, and a first conductive film pattern consisting of the conductive film are formed, and an amorphous silicon thin film pattern consisting of the amorphous silicon thin film and the n + are formed in the third region. Forming a second n + amorphous silicon thin film pattern made of an amorphous silicon thin film and a second conductive film pattern made of the conductive film; Removing the fourth photoresist pattern and simultaneously removing a portion of the first to third photoresist patterns to form a fifth to seventh photoresist pattern having a third thickness; Forming a source electrode, a drain electrode, and a storage electrode connected to the drain electrode by selectively removing the first conductive film pattern using the fifth photoresist pattern and the sixth photoresist pattern as masks; And And selectively removing the second conductive film pattern using the seventh photosensitive film pattern as a mask to form a conductive film pattern made of the conductive film. The ohmic contact of claim 6, wherein the fifth nth photosensitive film pattern and the sixth photosensitive film pattern are used as masks to selectively remove the first n + amorphous silicon thin film pattern, thereby ohmic contact between the active pattern and the source / drain electrodes. A method of manufacturing a liquid crystal display device, further comprising the step of forming a layer. The method of claim 7, further comprising forming a third n + amorphous silicon thin film pattern formed of the n + amorphous silicon thin film by selectively removing the second n + amorphous silicon thin film pattern using the seventh photoresist pattern as a mask. Method of manufacturing a liquid crystal display device characterized in that. The method of claim 5, wherein the widths of the fifth photoresist pattern to the seventh photoresist pattern are substantially smaller than the first photoresist pattern to the third photoresist pattern, respectively, through an ashing process. The method of claim 6, wherein the conductive film pattern has a shape substantially the same as that of an amorphous silicon thin film pattern below, but a narrow width thereof. 7. The method of claim 6, wherein the first region is a region in which a source electrode is formed. 7. The method of claim 6, wherein the second region is a region in which a drain electrode is formed. The method of claim 6, wherein the third region is a region in which a conductive film pattern is formed. The method of claim 6, wherein the fourth region is a channel region of an active pattern. 7. The method of claim 6, wherein the first thickness is thicker than the second thickness. The method of claim 8, wherein the forming of the first contact hole and the data line comprises removing an area of the second insulating layer, the storage electrode, the ohmic contact layer, and the active pattern to expose an inner side surface of the storage electrode. Forming a first contact hole, and removing a portion of the second insulating film, the conductive film pattern, the third n + amorphous silicon thin film pattern, and the second amorphous silicon thin film pattern to form a data line formed of the conductive film Method of manufacturing a liquid crystal display device. 17. The liquid crystal display of claim 16, further comprising forming a second contact hole exposing a portion of the common line by removing a portion of the second insulating layer and the first insulating layer. Way. The method of claim 16, wherein the second amorphous silicon thin film pattern under the data line is patterned in the same form as the data line. The method of claim 16, wherein the sidewall of the conductive layer pattern protrudes from the pixel region to overlap a portion of the first connection line. The method of claim 16, wherein a portion of the conductive layer pattern is removed to form a data line and a dummy pattern formed of the conductive layer and disconnected from each other. 21. The method of claim 20, wherein the dummy pattern is formed on the first connection line. 20. The method of claim 19, wherein a protruding side surface of the conductive film pattern is removed to form a data line formed of the conductive film. 18. The method of claim 16, further comprising forming a pixel electrode line formed on the storage electrode and connected to the pixel electrode. 24. The method of claim 23, wherein the pixel electrode line is arranged to be substantially parallel to the gate line. 18. The method of claim 17, further comprising forming a common electrode line formed on the common line and connected to the common electrode. 27. The method of claim 25, wherein the common electrode line is arranged to be substantially parallel to the gate line. 24. The method of claim 23, wherein the pixel electrode line is electrically connected to the storage electrode through the first contact hole. 27. The method of claim 25, wherein the common electrode line is electrically connected to the common line through the second contact hole. The method of claim 3, further comprising selectively removing a portion of the first insulating layer to form a second contact hole exposing a portion of the first connection line when the data line is formed. A method of manufacturing a liquid crystal display device. 30. The method of claim 29, wherein the common electrode is electrically connected to the first connection line through the second contact hole. A gate electrode, a gate line, and a common line formed on the first substrate and made of the first conductive material; A first insulating film formed on the first substrate; A source / drain electrode and a data line formed on the first substrate and formed of an active pattern made of an amorphous silicon thin film and a second conductive material; An amorphous silicon thin film pattern formed under the data line in the shape of the data line and made of the amorphous silicon thin film; A second insulating film formed on the first substrate; A common electrode and a pixel electrode disposed alternately on the first substrate and made of a third conductive material; And And a second substrate bonded to and opposed to the first substrate. 32. The liquid crystal display device according to claim 31, wherein the gate electrode forms part of the gate line. 32. The liquid crystal display device of claim 31, further comprising a first connection line connected to the common line and arranged substantially parallel to the data line. 34. The liquid crystal display device of claim 33, further comprising a second connection line connected to the first connection line and arranged substantially parallel to the gate line. 35. The liquid crystal display device according to claim 34, wherein the first connection line and the second connection line are made of the same conductive material as the first conductive material. 35. The liquid crystal display device according to claim 34, further comprising a storage electrode made of the second conductive film and connected to the drain electrode. 32. The liquid crystal display device according to claim 31, further comprising an ohmic contact layer made of an n + amorphous silicon thin film and ohmic contact between the active pattern and the source / drain electrodes. 34. The liquid crystal display of claim 33, further comprising a dummy pattern formed on the first connection line and made of the second conductive material. 37. The liquid crystal display of claim 36, further comprising a first contact hole exposing an inner side surface of the storage electrode. 32. The liquid crystal display device according to claim 31, wherein the data line and the amorphous silicon thin film pattern under the data line are patterned in the same shape and exposed to the outside. 40. The liquid crystal display of claim 39, further comprising a pixel electrode line formed on the storage electrode and connected to the pixel electrode. 32. The liquid crystal display device of claim 31, further comprising a common electrode line formed on the common line and connected to the common electrode. 42. The liquid crystal display device of claim 41, wherein the pixel electrode line is electrically connected to the storage electrode through the first contact hole. 43. The liquid crystal display device according to claim 42, further comprising a second contact hole exposing a portion of the common line. 45. The liquid crystal display of claim 44, wherein the common electrode line is electrically connected to the common line through the second contact hole. The liquid crystal display device of claim 33, further comprising a second contact hole exposing a portion of the first connection line. 47. The liquid crystal display of claim 46, wherein the common electrode is electrically connected to the first connection line through the second contact hole. 37. The liquid crystal display device according to claim 36, wherein the storage electrode overlaps a portion of the second connection line below the first insulating layer with the first insulating layer therebetween to form a storage capacitor.

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