KR20070063291A - Data masking circuit - Google Patents

Abstract

A data masking circuit is provided to receive DM data even at a high frequency operation, by enabling DM data by an external clock signal(PLCKWC) and disabling DM data enabled by a reset signal. In a data masking circuit of a semiconductor memory device, a first latch part(200) latches data input in response to a first signal. A logic gate(300) performs an AND operation of the first signal and the output of the first latch part. A second latch part(400) latches the output of the logic gate and determines to disable the output of the logic gate by a second signal. A signal generation circuit(100) generates the first signal and the second signal synchronized with an external clock.

Description

Data Masking Circuit

1 illustrates a semiconductor memory device that generally masks data.

2 is a block diagram of a data masking circuit according to the present invention.

3 is an embodiment of a data masking circuit according to the present invention.

4 is a timing diagram for a data masking circuit according to the present invention.

* Explanation of symbols for main parts of drawings *

P1, P2, P3, P4: PMOS transistor

N1, N2, N3, N4: NMOS transistor

INV_S, INV1, INV2: Inverter

NOR1, NOR2: Noah gate AND: And gate

100: signal generating circuit

The present invention relates to a semiconductor memory device, and more particularly, to a data masking circuit of a semiconductor memory device.

A semiconductor memory device is a memory device that stores data and can be read out when needed. The semiconductor memory device may be largely divided into a random access memory (RAM) and a read only memory (ROM). RAM is a volatile memory device in which stored data is lost when power is lost. A ROM is a nonvolatile memory device in which stored data is not destroyed even when power is cut off. RAM includes Dynamic RAM (DRAM), Static RAM (SRAM), and the like. The ROM includes a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a flash memory device, and the like.

In general, semiconductor memory devices have a matrix array of memory cells. Here, the memory cell array reads or writes data according to a read or write command when a row address and a column address are input.

The operating speed of such a semiconductor memory device is a factor that limits the performance of the system as the system becomes faster. Recently, high performance DRAMs such as synchronous DRAM (SDRAM), double data SDRAM (DDR SDRAM), and fast cycle RAM (FCRAM) have been developed to solve these limitations.

The SDRAM can input and output data only at the rising edge or the falling edge of the clock. DDR SDRAM, on the other hand, has twice the data transfer rate as SDRAM because data is inputted and outputted at the rising edge of the clock as well as the falling edge. DDR SDRAM also includes a data input / output masking pin (DQM Pin) to mask data that you do not want to write when a data write command occurs. When the data masking signal is activated, input / output of data is disabled according to a predetermined latency.

1 illustrates a semiconductor memory device that generally masks data. The semiconductor memory device includes a command decoder 12, an address buffer 14, a control signal generation circuit 16, a memory cell array 22, a row decoder 24, a column decoder 26, a sense amplifier 28, and input / output. A control circuit 32, a data input buffer 34, a data output buffer 36, and a DM circuit (Data Masking Circuit) 40 are included.

The command decoder 12 outputs a plurality of commands including a write command WRITE in response to control signals / CS, / RAS, / CAS and / WE input from the outside through the control pin.

The address buffer 14 transfers the row address and the column address input from the outside through the address pin to the row decoder 24 and the column decoder 26, respectively.

The control signal generation circuit 16 enables the control signal CTL in response to the write command WRITE. The control circuit CTL controls the core circuits of the DRAM, for example, the loop decoder 24, the column decoder 26, the input / output control circuit 32, the data input buffer 34 and the data output buffer 36. .

The row decoder 24 decodes the row address to enable the corresponding word line of the memory cell array 22. The column decoder 26 decodes the column address to enable the corresponding column select line of the memory cell array 22. The sense amplifier 28 senses and outputs data read from the selected memory cell.

The input / output control circuit 32 transfers the data amplified by the sense amplifier 28 to the data output buffer 36 and the data input to the data input buffer 34 to the memory cell array 22.

The data input buffer 34 receives data to be written through the data input / output pins. The data output buffer 36 outputs data to be read through the data input / output pins.

The DM circuit 40 enables the write control signal DM_P in response to the write prohibition signal DM_D input from the outside through the DM pin. The DM pin allows you to mask data that you do not want to write.

The data masking circuit (DM) includes a domain crossing circuit and a clock inverter. Domain Crossing converts from the receiver domain to the transmitter domain and in the area where the read command is recognized, to the area for exporting output data (DQ, DQS, DQSB) in synchronization with the external clock. Transition and transition from the internal clock to the delay locked loop clock. Accordingly, in the data masking circuit, the domain crossing circuit is a circuit that changes the data masking data (DM data), which has been transitioned to a bidirectional data strobe (DQS) domain, to transition to an external clock. The clocked inverter is latched to an external clock.

In general, for the DM data to pass through the clock inverter in the domain crossing circuit, the reset signal RESET and the external clock signal PCLKWC must be simultaneously 'low'. The external clock signal PCLKWC is generated in synchronization with the clock to which the write command Write CMD enters. The reset signal RESET is generated by receiving the next clock of the write command Write CMD. However, the problem is that the section in which the external clock signal PCLKWC and the reset signal RESET become low at the same time varies depending on the frequency according to the external clock CLK. The greater the frequency, the shorter the interval between the two signals goes low. It even goes away. Therefore, the conventional DM circuit has a problem that can not accept the DM data at a high frequency.

The present invention has been proposed to solve the above problems, and an object of the present invention is to propose a data masking circuit that accepts DM data even at high frequencies.

A data masking circuit of a semiconductor memory device according to the present invention includes a first latch unit for latching input data in response to a first signal; A logic gate for performing an AND operation on the first signal and an output of the first latch unit; A second latch unit for latching an output of the logic gate and determining disable for an output of the logic gate by a second signal; And a signal generator circuit for generating the first and second signals in synchronization with an external clock.

In the present exemplary embodiment, the first latch part may serve as a buffer for the data in the first signal state in which the data is not latched.

In this embodiment, the logic gate is characterized in that the AND gate.

In this embodiment, the second latch portion is an RS latch.

In this embodiment, the second latch unit is characterized in that the output of the logic gate is disabled when the second signal is in a high state.

In this embodiment, the semiconductor memory device is characterized in that the DRAM.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

2 is a block diagram of a data masking circuit according to the present invention. The data masking circuit includes a signal generation circuit 100, a first latch unit 200, a second latch unit, and a logic gate.

The signal generation circuit 100 generates an external clock signal PCLKWC and a reset signal RESET necessary for controlling the data masking circuit in synchronization with the external clock CLK. The external clock signal PCLKWC is generated in synchronization with the clock to which the write command Write CMD enters. The external clock signal PCLKWC is input to the first latch unit 200 and the logic gate 300. The reset signal RESET is generated by receiving the next clock of the write command Write CMD. The reset signal RESET is input to the second latch unit 400. The first latch unit 200 latches the input DM data DM_D in response to the external clock signal PCLKWC. The logic gate 300 performs an AND operation on the output of the first latch unit 200 and the external clock signal PCLKWC. The latch unit 400 latches the output of the logic gate and determines the disable timing of the latched output in response to the reset signal RESET to generate the data masking pulse DM_P.

3 is an embodiment of a data masking circuit according to the present invention. The data masking circuit includes a first latch unit 200, a logic gate 300, and a second latch unit 400.

The first latch unit 200 includes PMOS transistors P1 to P4, NMOS transistors N1 to 4, and inverters INV_S and INV1. The source terminal of the first PMOS transistor P1 is connected to the power supply voltage VDD. The source terminal of the second PMOS transistor P2 is connected to the drain terminal of the first PMOS transistor P1. The drain terminal of the first NMOS transistor N1 is connected to the drain terminal of the second PMOS transistor P2. The second NMOS transistor N2 has a drain terminal connected to a source terminal of the first NMOS transistor N1 and a source terminal connected to ground. The source terminal of the third PMOS transistor P3 is connected to the power supply voltage VDD. The fourth PMOS transistor P4 has a source terminal connected to the drain terminal of the third PMOS transistor P3. The drain end of the third NMOS transistor N3 is connected to the drain end of the fourth PMOS transistor P4. The fourth NMOS transistor N4 has a drain terminal connected to the source terminal of the third NMOS transistor N3 and the source terminal connected to the ground. The drain terminal of the second PMOS transistor P2 and the drain terminal of the fourth PMOS transistor P4 are connected.

The first latch unit 200 receives DM data DM_D and an external clock signal PCLKWC as inputs. DM data is input to the gate terminals of the first PMOS transistor P1 and the second NMOS transistor N2. The external clock signal PCLKWC is input to the gate terminal of the second PMOS transistor P2 and the fourth NMOS transistor N4. The signal PCLKWCB in which the external clock signal PCLKWC is inverted by the inverter INV_S is input to the gate terminals of the first NMOS transistor N1 and the third PMOS transistor P3. The first inverter INV1 receives the output value of the drain terminal node of the fourth PMOS transistor P4 and inverts it. The inverted output is input to the gate terminal of the fourth PMOS transistor P4 and the gate terminal of the third NMOS transistor N3.

The logic gate 300 performs an AND operation on the first latch unit output and the external clock signal PCLKWC. Here, the AND gate AND is simply used.

The second latch unit 400 forms a latch circuit including NOR gates NOR1 and NOR2 and an inverter INV2. The first NOR gate NOR1 receives the output of the AND gate AND and the output of the second NOR gate NOR2 as inputs. The second NOR gate NOR2 receives an output of the first NOR gate NOR1 and a reset signal RESET as an input. The second inverter INV2 receives the output of the first NOR gate NOR2 and outputs the inverted signal DM_P. The inverted signal DM_P is the final output value of the data masking circuit.

Referring to FIG. 3, the data masking circuit operates according to the external clock signal PCLKWC and the reset signal RESET as follows.

Assume when the external clock signal PCLKWC is 'high'. Therefore, the second PMOS transistor P2 and the first NMOS transistor N1 are turned off. The third PMOS transistor P3 and the fourth NMOS transistor N4 are turned on. The node NOD is a contact of the drain terminal of the fourth PMOS transistor P4 and the third NMOS transistor N3. The value of the node NOD is inverted to the first inverter INV1. The inverted value is again input to the gate terminal of the fourth PMOS transistor P4 and the gate terminal of the third NMOS transistor N3. Thus, the value of node NOD is latched.

Assume that the external clock signal PCLKWC is 'low'. Therefore, the second PMOS transistor P2 and the first NMOS transistor N1 are turned on. The third PMOS transistor P3 and the fourth NMOS transistor N4 are turned off. When the DM data DM_D is high, the first PMOS transistor P1 is turned off and the second NMOS transistor N2 is turned on. Therefore, the node NOD goes low. Therefore, the first inverter INV1 outputs a high value inverting the node value. Therefore, the one latch unit 100 outputs the value of the DM data DM_D as it is.

The operation of the logic gate 300 is as follows. The AND gate AND performs an AND operation on the output of the first latch unit 100 and the external clock signal PCLKWC, and outputs the result. When the clock signal PCLKWC is high and the latched data value is high, the output of the AND gate AND is high. In other states, the output of the AND gate AND is low.

The operation of the second latch unit 400 is as follows. For convenience of explanation, they are divided according to the AND gate (AND) output value.

When the output of the AND gate AND is in a low state, the first NOR gate NOR1 outputs a high state. Accordingly, the second inverter INV2 outputs a low state in which the output of the first NOR gate NOR1 is inverted.

When the output of the AND gate AND is in the high state, the second latch unit 400 performs two operations according to the reset signal RESET.

First, it is assumed that the reset signal RESET is low. At this time, the output of the second NOR gate NOR2 becomes a high state. Therefore, the first NOR gate NOR1 receives the output (high state) of the AND gate AND and the output (high state) of the second NOR gate NOR2 and outputs a low state. Therefore, the second inverter INV2 outputs a signal high state inverting the output of the second NOR gate NOR2. Therefore, when the reset signal RESET is in the low state, the second latch unit 400 latches the output (high state) of the AND gate AND.

Next, assume that the reset signal RESET is high. At this time, the output of the second NOR gate NOR2 goes low. The first NOR gate NOR1 receives the output of the AND gate AND (high state) and the output of the first NOR gate NOR2 (low state) and outputs a high state. The second inverter INV2 outputs a signal low state inverting the output value of the first NOR gate NOR2. Therefore, the second latch unit 400 outputs a low state.

Therefore, when the reset signal RESET transitions from the high state to the low state, the second latch unit 400 determines the disable timing of the output (high state) of the AND gate AND.

The signal generation circuit 100 receives an external clock CLK and generates an external clock signal PCLKWC and a reset signal RESET that are synchronized.

4 is a timing diagram of a data masking circuit according to the present invention. Referring to FIG. 3, the external clock CLK has two write commands Write CMD.

The external clock signal PCLKWC is enabled after a predetermined time in synchronization with the first write command clock. The enable time point of the external clock signal PCLKWC is synchronized with the rising edge of the write command clock. The disable time point of the external clock signal PCLKWC is synchronized with the falling edge of the write command clock. The signal generation circuit 100 receives a second write command clock after two clocks after the first write command clock. Therefore, the second external clock signal PCLKWC is enabled in the same manner as above.

The reset signal RESET is enabled by the rising edges of the clocks following the first write command clock and the second write command clock to generate a signal disabled by the falling edge.

Referring to FIG. 4, the DM data DM_D is latched in the high state of the external clock signal PCLKWC. When the external clock signal PCLKWC transitions from a low state to a high state, the data masking pulse DM_P is enabled. When the reset signal RESET is in the low state, the data masking pulse DM_P is latched. Then, when the reset signal RESET transitions from the low state to the high state, the data masking pulse DM_P is disabled.

The data masking circuit according to the present invention can generate the data masking pulse DM_P even if the external clock CLK is shortened. The data masking pulse DM_P is stably provided even in high frequency operation.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications may be made without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the equivalents of the claims of the present invention as well as the following claims.

As described above, the data masking circuit according to the present invention enables the DM data by the external clock signal PCLKWC and disables the DM data enabled by the reset signal RESET. It becomes acceptable.

Claims (6)

In a data masking circuit of a semiconductor memory device: A first latch unit for latching input data in response to the first signal; A logic gate for performing an AND operation on the first signal and an output of the first latch unit; A second latch unit for latching an output of the logic gate and determining disable for an output of the logic gate by a second signal; And And a signal generation circuit configured to generate the first and second signals in synchronization with an external clock. The method of claim 1, And the first latch portion serves as a buffer for the data in the first signal state not latching the data. The method of claim 1, And the logic gate is an AND gate. The method of claim 1, And said second latch portion is an RS latch. The method of claim 1, And the output of the logic gate is disabled when the second signal is in a high state. The method of claim 1, And said semiconductor memory device is a DRAM.

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