KR20070062149A - Method for fabricating of multi-layer transistor using laser induced epitaxial growth and cmp - Google Patents

Abstract

A method for fabricating a multi-layer transistor using a laser induced epitaxial growth and CMP is provided to remove efficiently a protrusion from a single crystal silicon layer by performing a CMP process at a low removal speed by using high-flatness slurry. A first active layer(110) is formed on a semiconductor substrate(100). A first transistor(130) is formed on the first active layer. A first insulating layer(140) is formed on the semiconductor substrate. A first epitaxial silicon contact is formed on the first insulating layer. An amorphous silicon layer is formed on the first insulating layer. A single crystal silicon layer(160') is formed by single-crystallizing the amorphous silicon layer. The single crystal silicon layer is planarized by performing a CMP process for removing a protrusion of the single crystal silicon layer. A second active layer is formed by patterning the single crystal silicon layer. A second transistor is formed on the second active layer.

Description

Method for fabricating of multi-layer transistor using laser induced epitaxial growth and CMP

1 is a cross-sectional view of a transistor formed of two layers.

2A through 2F are cross-sectional views illustrating a method of forming a multilayer transistor according to an exemplary embodiment of the present invention in a process sequence.

3 is a cross-sectional SEM photograph after single crystallization by scanning a laser beam over an amorphous silicon film.

Figure 4 is a graph showing the removal rate of the polysilicon film measured along the X-axis of the wafer in the CMP using a silica-based high flatness slurry for each process condition.

FIG. 5 is a SEM photograph showing the thickness of a single crystal silicon film of single crystal CMP using a high flatness slurry at the center and edge of a cell.

Fig. 6 is an AFM image of a single crystal silicon film before (a) CMP, (b) CMP and after cleaning, (c) CMP, after cleaning, after formation of oxide film and removal of oxide film.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 110 first active layer

120: device isolation layer 130: first transistor

140: first insulating film 145: seed contact hole

150: seed contact 160, 160 ': single crystal silicon film

160 ": second active layer 170: second transistor

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a transistor having a multilayer structure.

As the semiconductor device is highly integrated, the size of the active region is reduced, thereby reducing the channel length of the MOS transistor formed in the active region. As the channel length of the transistor decreases, short channel effects occur and leakage current increases. In addition, as the size of the transistor is reduced and the driving voltage is lowered, the output current of the transistor is lowered.

One way to cope with this has been to present a multilayer transistor. Multilayer transistors can solve problems such as short channel effects by dividing the transistor into two or more layers, thereby ensuring a horizontal space in one layer and maintaining a proper channel length.

1 is a cross-sectional view of a transistor formed of two layers. Referring to FIG. 1, an isolation layer 14 and a first active layer 12 are formed on a semiconductor substrate 10. The first active layer 12 including the source / drain (not shown) and the first gate electrode 20 formed thereon constitute a first transistor. An insulating layer 22 is formed on the first active layer 12, the device isolation layer 14, and the first gate electrode 20, and includes a second active layer including a source / drain (not shown) on the insulating layer 22 ( 32 and the second gate electrode 40 constitute a second transistor. The second active layer 32 is connected to the first active layer 12 by a seed contact 30 formed of epitaxial silicon in the insulating film 22.

In the silicon film of the second active layer 32, an amorphous silicon film is formed on the insulating film 22, and then a laser beam is injected on the surface of the amorphous silicon film to instantly melt the amorphous silicon film and crystallize the laser induced epitaxial growth method. It can be switched to a single crystal silicon film by Laser Induced Epitaxial Growth.

However, at the point where the amorphous silicon is melted by scanning the laser beam and then crystallized again, protrusions are generated on the silicon surface due to the difference in the crystallization rate. After the silicon on the seed contact 30 is melted by the heat generated by the laser beam, the heat is easily released through the seed contact 30 and crystallization occurs quickly, but the silicon between the seed contacts 30 is easily released. As crystallization occurs more slowly than exiting, single crystal silicon protrudes into protrusions.

Such protrusions can cause defects in subsequent processes such as gate formation and can degrade the electrical characteristics of the transistor.

The technical problem of the present invention is to provide a method of forming a multilayer transistor having an active layer free of defects due to protrusion shapes.

In order to achieve the above technical problem, a method of forming a multilayer transistor according to the present invention comprises the steps of forming a first active layer on a semiconductor substrate; Forming a first transistor in the first active layer; Forming a first insulating film on the semiconductor substrate on which the first transistor is formed; Forming a first epitaxial silicon contact penetrating the first insulating layer; Forming an amorphous silicon film on the first insulating film on which the first epitaxial silicon contact is formed; Scanning a surface of the amorphous silicon film to form a single crystal silicon film by monocrystallizing the amorphous silicon film by using epitaxial silicon as a seed in the first epitaxial silicon contact; CMPing the single crystal silicon film having the projection shape formed in the single crystallization step to planarize the single crystal silicon film while removing the projection shape; Patterning the planarized single crystal silicon film to form a second active layer; And forming a second transistor in the second active layer.

The forming of the first epitaxial silicon contact may include forming a first contact hole penetrating the first insulating layer to expose the first active layer; Growing an epitaxial silicon film from the first active layer, the epitaxial silicon film covering a part or all of the top surface of the first insulating film while filling the first contact hole; And removing the epitaxial silicon film formed on the upper surface of the first insulating film by using CMP to fill the epitaxial silicon film only in the first contact hole.

Preferably, the amorphous silicon film is formed to a thickness of about 500 mW to about 1000 mW.

The CMP of the single crystal silicon film is preferably CMP at a rate of about 50 kW / sec to about 300 kW / sec.

CMP planarizing the single crystal silicon film may include oxidizing a surface of the CMP single crystal silicon film; And stripping the oxidized portion.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

2A through 2F are cross-sectional views illustrating a method of forming a multilayer transistor according to an exemplary embodiment of the present invention in a process sequence. The transistor includes a gate electrode, a source / drain, and a channel formed in the active layer, but for convenience of description, the source / drain and the channel are omitted and only the gate electrode is represented as a transistor.

Referring to FIG. 2A, the first active layer 110 is defined by forming an isolation layer 120 on the semiconductor substrate 100, for example, a silicon substrate. The first transistor 130 is formed on the first active layer 110.

Referring to FIG. 2B, a seed contact hole 145 is formed to form a first insulating layer 140 covering the first transistor 130 and penetrate the first insulating layer 140 to expose the first active layer 110. do.

Referring to FIG. 2C, epitaxial silicon is selectively grown from the first active layer 110 in the seed contact hole 145. Next, the epitaxial silicon is filled by filling the seed contact hole 145 and out of the seed contact hole 145 to the first insulating layer 140 by CMP, and epitaxial silicon is left only in the seed contact hole 145. 150).

Referring to FIG. 2D, an amorphous silicon film is formed to a thickness of about 500 μm to 1000 μm on the first insulating layer 140 on which the seed contact 150 is formed, and then a pulse laser beam is scanned on the surface of the amorphous silicon film. Then, the amorphous silicon film is instantaneously melted by the energy of the laser beam, and is converted into the single crystal silicon film 160 while crystallizing epitaxial silicon in the seed contact 150 as a seed.

However, as mentioned above, when the amorphous silicon is melted by scanning the laser and then crystallized again, a protrusion shape 160a is generated on the surface of the single crystal silicon film 160 due to the difference in crystallization rate.

3 is a cross-sectional SEM photograph after single crystallization by scanning a pulsed laser beam onto an amorphous silicon film having a thickness of 500 Hz. Referring to FIG. 3, after the laser beam scanning, the single crystal silicon film 160b on the seed contact 150 is formed to have a thickness of about 350 GPa, but the single crystal silicon film 160a between the seed contacts 150 is about to have a thickness. It reaches a height of 1000Å and has a projection shape. The presence of such protrusions on the second active layer provides a cause of defects in subsequent transistor formation processes.

Referring to FIG. 2E, the single crystal silicon film 160 having the projection shape on the surface thereof is CMP to planarize while completely removing the projection shape. In the case of forming an active layer made of a flat single crystal silicon film 160 ′ having a thickness of about 300 GPa, an important factor to be considered in CMP is planarization characteristics and uniformity according to the silicon removal rate and the step height. Since the thickness of the silicon to be removed to form the active layer is only about a few hundred micrometers, if the silicon removal rate is fast, it is difficult to remove only the desired amount of silicon. Therefore, it is necessary to keep the silicon removal rate low. On the other hand, because of the projection shape, a step of about 650 Å is formed in the single crystal silicon film 160 '. In the CMP of the single crystal silicon film 160, this step should be able to be eliminated.

Figure 4 is a graph showing the removal rate of the polysilicon film measured along the X-axis of the wafer by the process conditions in the CMP using a silica-based high flatness slurry having a very low removal rate (removal rate). In the legend of FIG. 4, D represents down pressure and P represents rpm. Referring to Figure 4, it can be seen that the removal rate is very low, such as 100 Hz at 2psi and 120rpm conditions. The characteristic of the slurry having a low removal rate is that the removal rate of polysilicon does not increase significantly even if the lower pressure increases. On the other hand, from Figure 4 shows that the removal rate of the polysilicon in the wafer at 2psi and 120rpm conditions are uniform.

FIG. 5 is a SEM photograph showing the results of CMP of the single crystal silicon film 160 using the high flatness slurry having the low removal rate, compared with the center and the edge of the cells in the chip. Referring to FIG. 5, it can be seen that the protrusion shape is completely removed and that the thickness of the single crystal silicon film 160 at the center and the edge of the cell in the chip is almost the same. In other words, it can be seen that a result with high flatness and high uniformity can be obtained while removing a small amount of silicon film.

Table 1 is a table in which the thickness of the single crystal silicon film before and after CMP was measured at the center and the edge of the chip. In the single crystal silicon film, the high portion was raised from about 940 to 1060 Hz and the lower part was from about 315 to 325 Hz, but after removing the projection by CMP, the thickness was flattened to about 270 to 280 Hz. That is, the CMP according to the present invention effectively removes a step (about 615 to 745 ms) in a narrow pattern.

At this time, in order to remove the damage of the surface of the single crystal silicon film 160 'generated by CMP, the surface of the single crystal silicon film 160' is oxidized to form a thin oxide film (not shown), and then the oxide film (not shown) is removed. The process can be carried out.

Fig. 6 is an AFM image of a single crystal silicon film before (a) CMP, (b) CMP and after cleaning, (c) CMP, after cleaning, after formation of oxide film and removal of oxide film. The RMS value of the height before CMP of (a) was 140 Hz, the CMP of (b) and the RMS value after cleaning were 9.9 Hz, and the RMS value after CMP, cleaning, oxide film formation and oxide removal of (c) was 10.4 Hz. The height of the projection in the AFM image appears lower than the height of the projection taken from the cross-sectional SEM, which appears to be the effect of the probe. Referring to FIG. 6, it can be seen that the fine step due to the protrusion shape is removed by CMP, and that the oxide film can be generated and removed without significantly deteriorating the roughness of the surface of the single crystal silicon film.

2F, the second active layer 160 ″ is formed by patterning the single crystal silicon film 160 ′ planarized by CMP.

Referring to FIG. 2G, the second transistor 170 is formed on the patterned second active layer 160 ″.

As mentioned above, although this invention was demonstrated in detail through the specific Example, this invention is not limited to this, A deformation | transformation and improvement are possible by the person skilled in the art within the technical idea of this invention.

As described above, CMP of a single crystal silicon film formed from amorphous silicon by scanning a laser beam at a low removal rate using a high flatness slurry is used to efficiently remove the projection shape generated in the single crystal silicon film while simultaneously reducing the active region thickness of the single crystal silicon film. It can be adjusted to a thickness suitable for forming.

Claims (7)

Forming a first active layer on the semiconductor substrate; Forming a first transistor in the first active layer; Forming a first insulating film on the semiconductor substrate on which the first transistor is formed; Forming a first epitaxial silicon contact penetrating the first insulating layer; Forming an amorphous silicon film on the first insulating film on which the first epitaxial silicon contact is formed; Scanning a surface of the amorphous silicon film to form a single crystal silicon film by monocrystallizing the amorphous silicon film by using epitaxial silicon as a seed in the first epitaxial silicon contact; CMPing the single crystal silicon film having the projection shape formed in the single crystallization step to planarize the single crystal silicon film while removing the projection shape; Patterning the planarized single crystal silicon film to form a second active layer; And Forming a second transistor in the second active layer. The method of claim 1, wherein the forming of the first epitaxial silicon contact comprises: forming a first contact hole through the first insulating layer to expose the first active layer; Growing an epitaxial silicon film from the first active layer to fill a portion of the upper surface of the first insulating layer while filling the first contact hole; And removing the epitaxial silicon film formed on the upper surface of the first insulating film using CMP to fill the epitaxial silicon film only in the first contact hole. The method of claim 1, wherein the forming of the amorphous silicon film comprises forming the amorphous silicon film in a thickness of about 500 kV to about 1000 kW. The method of claim 1, wherein CMPing the single crystal silicon film comprises CMPing the single crystal silicon film at a rate of about 50 mW / sec to about 300 mW / sec. 2. The method of claim 1, wherein the step of planarizing the single crystal silicon film by CMP planarizes the single crystal silicon film to a thickness of about 200 to 500 kHz. The method of claim 1, wherein the planarization of the single crystal silicon film by CMP comprises: oxidizing a surface of the CMP single crystal silicon film; And And stripping the oxidized portion. The method of claim 1, wherein forming the transistor comprises: forming a gate electrode; And forming a source / drain in the active layer.

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