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KR20070062084A - Bump reverse stitch bonding method, chip stack structure and method using the same - Google Patents

Bump reverse stitch bonding method, chip stack structure and method using the same Download PDF

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Publication number
KR20070062084A
KR20070062084A KR1020050121790A KR20050121790A KR20070062084A KR 20070062084 A KR20070062084 A KR 20070062084A KR 1020050121790 A KR1020050121790 A KR 1020050121790A KR 20050121790 A KR20050121790 A KR 20050121790A KR 20070062084 A KR20070062084 A KR 20070062084A
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South Korea
Prior art keywords
bonding
chip
wire
stitch
capillary
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Application number
KR1020050121790A
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Korean (ko)
Inventor
김병주
김상영
문태호
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삼성전자주식회사
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Priority to KR1020050121790A priority Critical patent/KR20070062084A/en
Publication of KR20070062084A publication Critical patent/KR20070062084A/en

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A bump reverse stitch bonding method, a chip stacked structure using the same and a chip stacking method are provided to secure the reliability of bonding between a lead of a circuit board and a bonding wire and to prevent generation of short between adjacent bonding wires. A circuit board(110) is provided. A semiconductor chip with chip pads is mounted on the circuit board. The circuit board has a lead adjacent to the chip. A ball bump(152) is formed on the chip pad of the chip by using a capillary loaded with a bonding wire. The capillary cuts the bonding wire at the ball bump. A bonding wire(154) is drawn as much as a predetermined length from the capillary downward. A first bonding portion is formed on the lead of the circuit board by performing a first stitch bonding process using the capillary. A wire loop portion(150) is formed from the first bonding portion to the ball bump of the chip by raising vertically the bonding wire as much as the chip height or more and moving the bonding wire. A second bonding portion(158) is formed on the ball bump of the chip by performing a second stitch bonding process using the capillary. The capillary cuts the bonding wire at the second bonding portion.

Description

범프 리버스 스티치 본딩 방법, 그를 이용한 칩 적층 구조와 칩 적층 방법{Bump reverse stitch bonding method, chip stack structure and method using the same}Bump reverse stitch bonding method, chip stack structure and method using the same}

도 1은 종래기술의 따른 범프 포워드 스티치 본딩으로 구현된 칩 적층 구조를 보여주는 단면도이다.1 is a cross-sectional view illustrating a chip stack structure implemented by bump forward stitch bonding according to the related art.

도 2는 본 발명의 실시예에 따른 범프 리버스 스티치 본딩으로 구현된 칩 적층 구조를 보여주는 단면도이다.2 is a cross-sectional view illustrating a chip stack structure implemented with bump reverse stitch bonding according to an embodiment of the present invention.

도 3a 내지 도 3h는 도 2의 칩 적층 구조를 형성하는 방법에 따른 각 단계를 보여주는 도면들이다.3A to 3H are diagrams illustrating each step according to the method of forming the chip stack structure of FIG. 2.

* 도면의 주요 부분에 대한 설명 *Description of the main parts of the drawing

110 : 배선기판 112 : 리드110: wiring board 112: lead

114 : 칩 실장 영역 120 : 제 1 칩114: chip mounting area 120: first chip

122 : 제 1 칩 패드 130 : 제 1 본딩 와이어122: first chip pad 130: first bonding wire

140 : 제 2 칩 142 : 제 2 칩 패드140: second chip 142: second chip pad

150 : 제 2 본딩 와이어 151 : 볼150: second bonding wire 151: ball

152 : 볼 범프 153 : 와이어 꼬리152: ball bump 153: wire tail

154 : 제 1 본딩부 156 : 와이어 루프부154: first bonding portion 156: wire loop portion

158 : 제 2 본딩부 172 : 캐필러리158: second bonding portion 172: capillary

174 : 클램프 200 : 칩 적층 구조174: clamp 200: chip stack structure

본 발명은 반도체 패키지 제조 기술에 관한 것으로, 보다 상세하게는 반도체 칩의 칩 패드와 배선기판의 리드를 전기적으로 연결하는 범프 리버스 스티치 본딩 방법, 그를 이용한 칩 적층 구조와 방법에 관한 것이다.The present invention relates to a semiconductor package manufacturing technology, and more particularly, to a bump reverse stitch bonding method for electrically connecting a chip pad of a semiconductor chip and a lead of a wiring board, and a chip stack structure and method using the same.

반도체 패키지의 제조 공정에 있어서 와이어 본딩이란 반도체 칩(또는 다이)과 배선기판을 본딩 와이어로 연결하는 것을 의미한다. 이때 사용되는 본딩 와이어로는 금(Au)이나 알루미늄(Al)을 주로 사용하고 구리(Cu)를 사용하는 경우도 있다. 배선기판은 리드 프레임을 비롯하여 인쇄회로기판, 세라믹 기판, 테이프 배선기판 등을 포함한다.In the manufacturing process of a semiconductor package, wire bonding means connecting a semiconductor chip (or die) and a wiring board with a bonding wire. In this case, as the bonding wire used, gold (Au) or aluminum (Al) may be mainly used, and copper (Cu) may be used. The wiring board includes a lead frame, a printed circuit board, a ceramic board, a tape wiring board, and the like.

반도체 칩과 배선기판을 본딩 와이어로 연결해 주는 장비를 와이어 본더(wire bonder)라 하며, 와이어 본더는 실질적인 와이어 본딩 공정을 진행하는 캐필러리(capillary)를 포함한다.The equipment that connects the semiconductor chip and the wiring board with the bonding wire is called a wire bonder, and the wire bonder includes a capillary that performs a substantial wire bonding process.

와이어 본딩법 중에서 일반적으로 사용되는 볼 본딩(ball bonding)은 본딩 와이어의 끝단에 볼을 형성하여 반도체 칩의 칩 패드에 본딩한 후, 일정한 궤적의 루프(loop)를 만들어 배선기판의 리드에 스티치 본딩(stitch bonding)으로 마무리한다. 그런데 본딩 와이어의 루프를 형성하고 유지하기 위해서 반도체 칩의 상부면 에 대한 본딩 와이어의 최고점의 높이를-본딩 와이어의 직경에 따라서 차이는 있겠지만 100㎛ 내지 200㎛로 유지해야 하기 때문에, 본딩 와이어의 루프 높이를 낮추는 데는 한계가 있다. 따라서 기존의 와이어 본딩법은 반도체 패키지의 박형화의 장애요인으로 작용하고 있다.Ball bonding, which is generally used in the wire bonding method, forms a ball at the end of the bonding wire and bonds it to the chip pad of the semiconductor chip, and then creates a loop of a constant trajectory to stitch bond the lead of the wiring board. Finish with (stitch bonding). However, in order to form and maintain the loop of the bonding wire, the height of the highest point of the bonding wire with respect to the upper surface of the semiconductor chip-the thickness of the bonding wire must be maintained between 100 µm and 200 µm, although it may vary depending on the diameter of the bonding wire. There is a limit to lowering the height. Therefore, the existing wire bonding method acts as a barrier to thinning of the semiconductor package.

특히 반도체 패키지의 크기가 점차 작아지고 그 두께가 박형화됨에 따라서 와이어 본딩 공정에서는 칩 패드와 칩 패드의 간격, 리드와 리드 사이의 간격이 미세한 반도체 패키지에 대하여 와이어 본딩을 가능하게 하고, 낮은 루프 하이트(loop height)를 실현하고, 루프의 길이가 긴 와이어 본딩을 실현하기 위해 많은 노력이 경주되고 있다. 예컨대, 미국특허공보 제5,328,079호(1994.07.12), 미국특허공보 제5,735,030호(1998.04.07) 그리고 대한민국 등록특허공보 제0350084호(2002.08.13)호 개시된 바와 같이, 반도체 칩의 칩 패드에 범프를 형성한 다음, 배선기판의 리드에 볼 본딩 후 범프에 스티치 본딩으로 마무리하는 범프 리버스 본딩(bump reverse bonding)이 사용되고 있다.In particular, as the size of the semiconductor package gradually decreases and the thickness thereof becomes thinner, in the wire bonding process, wire bonding is possible for a semiconductor package having a small spacing between the chip pad and the chip pad and a gap between the lead and the lead, and the low loop height ( Many efforts have been made to realize wire heights and wire bonding with long loops. For example, as disclosed in U.S. Patent Nos. 5,328,079 (1994.07.12), U.S. Patent Nos. 5,735,030 (1998.04.07) and Republic of Korea Patent Publication No. 0350084 (2002.08.13), bumps on chip pads of semiconductor chips After bump formation, bump reverse bonding (bump reverse bonding) is used, in which a ball bonding is performed on the lead of the wiring board and then the stitch bonding is completed on the bumps.

그런데 범프 리버스 본딩으로 형성된 본딩 와이어는 리드와의 접합성이 떨어지기 때문에, 본딩 와이어의 볼 부분이 리드에서 들뜨는 불량이 발생된다.However, since the bonding wire formed by bump reverse bonding is inferior in the bonding property with a lead, the defect which a ball part of a bonding wire floats in a lead generate | occur | produces.

이와 같은 문제점을 해결하기 위해서, 도 1에 도시된 바와 같이, 리드(12)에 스티치 본딩 방법으로 본딩 와이어(30, 50)를 본딩하는 방법이 사용되고 있다. 도 1은 배선 기판(10)의 상부면에 두 개의 반도체 칩(20, 40)이 적층된 칩 적층 구조(100)가 개시되어 있다. 반도체 칩(20, 40)들과 연결되는 본딩 와이어(30, 50)들은 배선기판(10)의 리드(12)에 스티치 본딩된다.In order to solve such a problem, as shown in FIG. 1, a method of bonding the bonding wires 30 and 50 to the lead 12 by a stitch bonding method is used. 1 shows a chip stack structure 100 in which two semiconductor chips 20 and 40 are stacked on an upper surface of a wiring board 10. The bonding wires 30 and 50, which are connected to the semiconductor chips 20 and 40, are stitch bonded to the leads 12 of the wiring board 10.

즉 반도체 칩(20, 40)의 볼 범프(32, 52) 위에 본딩 와이어(30, 50)의 일단을 1차 스티치 본딩한 후 배선기판(10)의 리드(12)를 향하여 직선에 가깝게 루프를 형성한 다음 본딩 와이어(30, 50)의 타단을 배선기판(10)의 리드(12)에 2차 스티치 본딩으로 마무리한다. 이하의 설명에 있어서, 이와 같은 스티치 본딩 방법을 범프 포워드 스티치 본딩(bump forward stitch bonding) 방법이라 한다.That is, after first stitch bonding one end of the bonding wires 30 and 50 on the ball bumps 32 and 52 of the semiconductor chips 20 and 40, the loop is made close to the straight line toward the lead 12 of the wiring board 10. After forming, the other ends of the bonding wires 30 and 50 are finished by the secondary stitch bonding to the leads 12 of the wiring board 10. In the following description, such a stitch bonding method is referred to as a bump forward stitch bonding method.

이때 배선기판(10)의 리드(12) 중 본딩 와이어(30, 50)가 함께 스티치 본딩되는 리드(12)들이 존재할 수 있다. 이와 같이 하나의 리드(12)에 본딩 와이어(30, 50)가 함께 스티치 본딩될 경우, 본딩 와이어(30, 50) 사이의 간격을 확보하는 것이 쉽지 않다. 즉 적층된 반도체 칩(20, 40)의 볼 범프(32, 52)에 본딩되어 인출된 본딩 와이어(30, 50)는 직선에 가깝게 리드(12)를 향하여 루프를 형성하기 때문에, 본딩 와이어(30, 50) 사이의 간격을 확보하는 것이 쉽지 않다.At this time, among the leads 12 of the wiring board 10, there may be leads 12 in which the bonding wires 30 and 50 are stitch bonded together. As such, when the bonding wires 30 and 50 are stitch bonded together to one lead 12, it is not easy to secure the gap between the bonding wires 30 and 50. That is, since the bonding wires 30 and 50 bonded and drawn to the ball bumps 32 and 52 of the stacked semiconductor chips 20 and 40 form a loop toward the lead 12 close to the straight line, the bonding wire 30 , It is not easy to secure the gap between 50).

그리고 본딩 와이어(30, 50)들 사이의 간격이 좁기 때문에, 와이어 쇼트(60; wire short)가 발생될 수 있다.And since the gap between the bonding wires 30 and 50 is narrow, a wire short 60 may be generated.

따라서, 본 발명의 목적은 리드와 본딩 와이어 사이의 접합 신뢰성을 확보하면서, 다층으로 적층된 반도체 칩에서 인출된 본딩 와이어 사이의 간격을 충분히 확보하여 와이어 쇼트가 발생되는 것을 방지할 수 있도록 하는 데 있다.Accordingly, an object of the present invention is to ensure the bonding reliability between the lead and the bonding wire, and to sufficiently secure the gap between the bonding wires drawn from the multilayered semiconductor chip to prevent the occurrence of wire short. .

상기 목적을 달성하기 위하여, 본 발명은 (a) 칩 패드들을 갖는 반도체 칩이 실장되어 있으며, 반도체 칩에 근접하게 리드가 형성된 배선기판을 제공하는 단계 와, (b) 본딩 와이어가 장착된 캐필러리가 반도체 칩의 칩 패드에 볼 범프를 형성하는 단계와, (c) 캐필러리가 볼 범프에서 본딩 와이어를 끊고, 캐필러리 아래로 일정 길이의 본딩 와이어를 인출시키는 단계와, (d) 캐필러리가 인출된 본딩 와이어를 배선기판의 리드에 1차 스티치 본딩하여 제 1 본딩부를 형성하는 단계와, (e) 캐필러리가 제 1 본딩부에서 반도체 칩의 상부면보다는 적어도 높게 수직에 가깝게 상승한 후 반도체 칩의 볼 범프를 향하여 이동하여 와이어 루프부를 형성하는 단계와, (f) 캐필러리가 반도체 칩의 볼 범프 위에 본딩 와이어를 2차 스티치 본딩하여 제 2 본딩부를 형성하는 단계 및 (g) 캐필러리가 반도체 칩의 볼 범프 위의 제 2 본딩부에서 본딩 와이어를 끊는 단계를 포함하는 범프 리버스 스티치 본딩 방법을 제공한다.In order to achieve the above object, the present invention provides a step of (a) providing a wiring board in which a semiconductor chip having chip pads is mounted, the lead is formed in proximity to the semiconductor chip, and (b) a capillary with a bonding wire Forming a ball bump on the chip pad of the Liga semiconductor chip, (c) the capillary breaking the bonding wire at the ball bump, drawing a length of bonding wire under the capillary, and (d) the capillary Forming the first bonding portion by first stitch bonding the lead-out bonding wire to the lead of the wiring board, and (e) the capillary rises vertically at least higher than the upper surface of the semiconductor chip at the first bonding portion and rises vertically. Moving toward the ball bumps of the chip to form a wire loop portion; and (f) the capillary second stitch-bonds the bonding wires on the ball bumps of the semiconductor chip to form a second bonding portion. System and (g) capping provides a bump reverse stitch-bonding method of Lee filler includes a first step to break the bonding wires in the second bonding portion of the upper ball bumps of the semiconductor chip.

본 발명에 따른 본딩 방법에 있어서, (d) 단계에서 제 1 본딩부 뒤쪽으로 일정 길이의 와이어 꼬리가 형성된다. 본딩 와이어로는 금선이 사용된다.In the bonding method according to the present invention, a wire tail of a predetermined length is formed behind the first bonding portion in step (d). Gold wire is used as a bonding wire.

본 발명은 또한 전술된 범프 리버스 스티치 본딩 방법을 이용한 칩 적층 방법을 제공한다. 즉, (a) 상부면에 칩 실장 영역이 형성되어 있으며, 칩 실장 영역에 근접하게 리드들이 형성된 배선기판을 준비하는 단계와, (b) 상부면에 제 1 칩 패드가 형성된 제 1 칩을 칩 실장 영역에 부착하는 단계와, (c) 제 1 칩 패드와 배선기판의 리드를 제 1 본딩 와이어로 연결하는 단계와, (d) 상부면에 제 2 칩 패드가 형성된 제 2 칩을 제 1 칩 위에 부착하는 단계 및 (f) 제 2 칩 패드와 배선기판의 리드를 제 2 본딩 와이어로 연결하는 단계를 포함하는 칩 적층 방법을 제공한다. 이때 (f) 단계는 제 2 칩 패드에 볼 범프를 형성하는 단계와, 제 2 본딩 와이 어의 일단부를 리드에 1차 스티치 본딩하여 제 1 본딩부를 형성하는 단계와, 제 1 본딩부에서 제 2 칩의 상부면보다는 적어도 높게 수직에 가깝게 상승시킨 후 볼 범프를 향하여 이동하여 제 1 본딩 와이어의 상부에 와이어 루프부를 형성하는 단계 및 볼 범프 위에 제 2 본딩 와이어의 타단을 2차 스티치 본딩하여 제 2 본딩부를 형성하는 단계를 포함한다.The present invention also provides a chip stacking method using the bump reverse stitch bonding method described above. That is, (a) preparing a wiring board having a chip mounting region formed on an upper surface thereof and having leads formed close to the chip mounting region, and (b) chipping a first chip having a first chip pad formed on the upper surface thereof. Attaching to the mounting area, (c) connecting the first chip pad and the leads of the wiring board with the first bonding wires, and (d) the second chip having the second chip pad formed on the upper surface of the first chip. And attaching the lead of the second chip pad and the wiring board to the second bonding wire. In this case, step (f) includes forming a ball bump on the second chip pad, first stitch bonding one end of the second bonding wire to the lead, and forming a first bonding part, and forming a second bonding part in the first bonding part. At least higher than the upper surface of the chip to rise vertically and then move toward the ball bump to form a wire loop on top of the first bonding wire and second stitch bonding the other end of the second bonding wire on the ball bump to form a second loop. Forming a bonding portion.

제 1 본딩부를 형성하는 단계에 있어서, 제 1 본딩부 뒤쪽으로 일정 길이의 와이어 꼬리가 형성된다.In forming the first bonding portion, a wire tail of a predetermined length is formed behind the first bonding portion.

본 발명은 또한 범프 리버스 스티치 본딩 방법을 이용한 칩 적층를 제공한다. 즉, 본 발명은 상부면에 칩 실장 영역이 형성되어 있으며, 칩 실장 영역에 근접하게 리드들이 형성된 배선기판을 포함한다. 제 1 칩은 칩 실장 영역에 부착되며, 상부면에 복수의 제 1 칩 패드가 형성되어 있다. 제 1 본딩 와이어는 제 1 칩 패드와 리드를 전기적으로 연결한다. 제 2 칩은 제 1 칩 위에 부착되며, 상부면에 복수의 제 2 칩 패드가 형성되어 있다. 그리고 제 2 칩 패드와 리드를 전기적으로 연결하는 제 2 본딩 와이어를 포함한다.The present invention also provides chip stack using a bump reverse stitch bonding method. That is, the present invention includes a wiring board having a chip mounting region formed on an upper surface thereof and having leads formed near the chip mounting region. The first chip is attached to the chip mounting region, and a plurality of first chip pads are formed on the upper surface. The first bonding wire electrically connects the first chip pad and the lead. The second chip is attached to the first chip, and a plurality of second chip pads are formed on the upper surface. And a second bonding wire electrically connecting the second chip pad and the lead.

이때 제 2 본딩 와이어는 볼 범프, 제 1 본딩부, 와이어 루프부 및 제 2 본딩부로 이루어진다. 볼 범프는 제 2 칩 패드들 위에 각각 형성된다. 제 1 본딩부는 기판 패드에 1차 스티치 본딩된다. 제 2 본딩부는 제 1 본딩부에서 연장되어 제 1 본딩 와이어의 상부에 형성되며, 제 1 본딩부에서 볼 범프보다는 적어도 높게 수직에 가깝게 상승한 후 볼 범프를 향하여 뻗어 있다. 그리고 제 2 본딩부는 와이어 루프부와 연결되어 있으며, 볼 범프 위에 2차 스티치 본딩된다.In this case, the second bonding wire includes a ball bump, a first bonding part, a wire loop part, and a second bonding part. Ball bumps are formed on the second chip pads, respectively. The first bonding portion is first stitch bonded to the substrate pad. The second bonding portion extends from the first bonding portion and is formed on top of the first bonding wire, and rises closer to the vertical at least higher than the ball bump in the first bonding portion and then extends toward the ball bump. The second bonding part is connected to the wire loop part, and the second stitch bonding is performed on the ball bumps.

이하, 첨부 도면을 참조하여 본 발명의 실시예를 보다 상세하게 설명하고자 한다.Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

칩 적층 구조Chip stack structure

도 2는 본 발명의 실시예에 따른 범프 리버스 스티치 본딩으로 구현된 칩 적층 구조(200)를 보여주는 단면도이다.2 is a cross-sectional view illustrating a chip stack structure 200 implemented with bump reverse stitch bonding according to an embodiment of the present invention.

도 2를 참조하면, 본 발명의 실시예에 따른 칩 적층 구조(200)는 배선기판(110)의 상부면에 반도체 칩(120, 140)들이 적층되고, 반도체 칩(120, 140)은 배선기판(110)과 본딩 와이어(130, 150)에 의해 전기적으로 연결된 구조를 갖는다. 이때 반도체 칩(120, 140)은 배선기판(110)의 상부면에 부착되는 제 1 칩(120)과, 제 1 칩(120) 위에 부착되는 제 2 칩(140)을 포함한다. 본딩 와이어(130, 150)는 제 1 칩(120)과 배선기판(110)을 연결하는 제 1 본딩 와이어(130)와, 제 2 칩(140)과 배선기판(110)을 연결하는 제 2 본딩 와이어(150)를 포함한다.Referring to FIG. 2, in the chip stack structure 200 according to an exemplary embodiment of the present invention, semiconductor chips 120 and 140 are stacked on an upper surface of the wiring board 110, and the semiconductor chips 120 and 140 are wiring boards. It has a structure electrically connected by the 110 and the bonding wires (130, 150). In this case, the semiconductor chips 120 and 140 include a first chip 120 attached to the upper surface of the wiring board 110 and a second chip 140 attached to the first chip 120. The bonding wires 130 and 150 may include a first bonding wire 130 connecting the first chip 120 and the wiring board 110 and a second bonding connecting the second chip 140 and the wiring board 110. Wire 150.

배선기판(110)은 상부면의 중심 부분에 칩 실장 영역(114)이 형성되어 있으며, 칩 실장 영역(114)에 근접하게 리드(112)들이 형성되어 있다. 배선기판(110)으로는 리드 프레임을 비롯하여 인쇄회로기판, 세라믹 기판, 테이프 배선기판 등이 사용될 수 있다.In the wiring board 110, a chip mounting region 114 is formed at a center portion of an upper surface thereof, and leads 112 are formed to be close to the chip mounting region 114. The wiring board 110 may include a lead frame, a printed circuit board, a ceramic board, a tape wiring board, or the like.

제 1 칩(120)은 칩 실장 영역(114)에 부착되며, 상부면에 복수개의 제 1 칩 패드(122)가 형성되어 있다. 제 1 칩(120)의 상부면에 제 2 칩(140)이 직접 부착될 수 있도록 제 1 칩 패드(122)는 가장자리 부분에 형성되어 있다.The first chip 120 is attached to the chip mounting region 114, and a plurality of first chip pads 122 are formed on an upper surface thereof. The first chip pad 122 is formed at an edge portion so that the second chip 140 may be directly attached to the upper surface of the first chip 120.

제 1 본딩 와이어(130)는 제 1 칩(120)의 제 1 칩 패드(122)와 배선기판(110)의 리드(112)를 각각 전기적으로 연결한다. 제 1 본딩 와이어(130)는 일반적인 볼 본딩 방법, 스티치 본딩 방법 또는 범프 포워드 스티치 본딩 방법으로 형성될 수 있다. 또는 후술되는 제 2 본딩 와이어(150)를 형성하는 방법으로 형성할 수도 있다. 본 실시예에서는 제 1 본딩 와이어(130)가 범프 포워드 스티치 본딩 방법으로 형성된 예를 개시하였다.The first bonding wire 130 electrically connects the first chip pad 122 of the first chip 120 and the lead 112 of the wiring board 110, respectively. The first bonding wire 130 may be formed by a general ball bonding method, a stitch bonding method, or a bump forward stitch bonding method. Alternatively, the method may be formed by a method of forming the second bonding wire 150 to be described later. In the present embodiment, an example in which the first bonding wire 130 is formed by the bump forward stitch bonding method is disclosed.

제 2 칩(140)은 제 1 칩(120) 위에 적층되며, 상부면에 복수개의 제 2 칩 패드(142)가 형성되어 있다. The second chip 140 is stacked on the first chip 120, and a plurality of second chip pads 142 is formed on an upper surface thereof.

제 2 본딩 와이어(150)는 제 2 칩(140)의 제 2 칩 패드(142)와 배선기판(110)의 리드(112)를 각각 전기적으로 연결한다. 제 2 본딩 와이어(150)는 볼 범프(152), 제 1 본딩부(154), 와이어 루프부(156) 및 제 2 본딩부(158)로 구성된다. 볼 범프(152)는 제 2 칩 패드(142)들 위에 각각 형성된다. 볼 범프(152)는 볼 본딩 방법으로 형성될 수 있다. 제 1 본딩부(154)는 배선기판(110)의 리드(112)에 1차 스티치 본딩되어 형성된다. 와이어 루프부(156)는 제 1 본딩부(154)에서 연장되어 제 1 본딩 와이어(130)의 상부에 형성된다. 그리고 제 2 본딩부(158)는 와이어 루프부(156)와 연결되어 있으며, 제 2 칩(140)의 볼 범프(152) 위에 2차 스티치 본딩되어 형성된다.The second bonding wire 150 electrically connects the second chip pad 142 of the second chip 140 and the lead 112 of the wiring board 110, respectively. The second bonding wire 150 includes a ball bump 152, a first bonding part 154, a wire loop part 156, and a second bonding part 158. The ball bumps 152 are formed on the second chip pads 142, respectively. The ball bump 152 may be formed by a ball bonding method. The first bonding part 154 is formed by first stitch bonding to the lead 112 of the wiring board 110. The wire loop part 156 extends from the first bonding part 154 and is formed on the first bonding wire 130. The second bonding part 158 is connected to the wire loop part 156, and is formed by secondary stitch bonding on the ball bump 152 of the second chip 140.

특히 와이어 루프부(156)는 제 1 본딩부(154)의 1차 스티치 본딩 지점에서 제 2 칩(140)의 볼 범프(152)보다는 적어도 높게 수직에 가깝게 상승한 후 볼 범프(152)를 향하여 이동하여 제 1 본딩 와이어(130)의 상부에 와이어 루프를 형성하는 부분이다. 이때 1차 스티치 본딩 지점에서 수직에 가깝게 와이어 루프부(156)를 형성할 수 있도록 제 1 본딩부(154)는 1차 스티치 본딩 지점에서 뒤쪽으로 일정 길이의 와이어 꼬리(153)가 형성되어 있다. 제 1 본딩부(154)의 와이어 꼬리(153)는 위쪽을 향하고 있다. 이와 같은 본 발명의 실시예에 따른 스티치 본딩 방법을 범프 리버스 스티치 본딩(bump reverse stitch bonding) 방법이라 한다.In particular, the wire loop portion 156 ascends closer to the vertical at least higher than the ball bump 152 of the second chip 140 at the first stitch bonding point of the first bonding portion 154 and then moves toward the ball bump 152. To form a wire loop on the first bonding wire 130. At this time, the first bonding portion 154 has a predetermined length of the wire tail 153 to the rear at the first stitch bonding point so as to form the wire loop portion 156 close to the vertical at the first stitch bonding point. The wire tail 153 of the first bonding portion 154 faces upward. Such a stitch bonding method according to an embodiment of the present invention is referred to as a bump reverse stitch bonding method.

즉 제 2 본딩 와이어(150)는 양단이 배선기판(110)의 리드(112)와 제 2 칩(140)의 볼 범프(152)에 스티치 본딩되고, 와이어 루프부(156)은 종래의 범프 리버스 본딩으로 형성된 와이어 루프와 유사한 형태로 형성할 수 있다.In other words, both ends of the second bonding wire 150 are stitch bonded to the lead 112 of the wiring board 110 and the ball bump 152 of the second chip 140, and the wire loop part 156 is a conventional bump reverse. It can be formed in a form similar to the wire loop formed by bonding.

따라서 제 1 및 제 2 본딩 와이어(130, 150)가 배선기판(110)의 리드(112)에 모두 스티치 본딩 방법으로 본딩되기 때문에, 제 1 및 제 2 본딩 와이어(130, 150)와 리드(112) 사이의 접합 선뢰성을 확보할 수 있다. 그리고 리드(112) 하나에 제 1 및 제 2 본딩 와이어(130, 150)가 스티치 본딩되더라도, 제 1 본딩 와이어(130)의 뒤쪽에 스티치 본딩되는 제 2 본딩 와이어(150)의 와이어 루프부(156)를 수직에 가깝게 형성할 수 있기 때문에, 제 1 본딩 와이어(130)와 제 2 본딩 와이어(150) 사이의 간격을 충분히 확보할 수 있다.Therefore, since the first and second bonding wires 130 and 150 are all bonded to the leads 112 of the wiring board 110 by the stitch bonding method, the first and second bonding wires 130 and 150 and the leads 112 are formed. ) Can secure the joint fastness. And even if the first and second bonding wires 130 and 150 are stitch bonded to one lead 112, the wire loop portion 156 of the second bonding wire 150 stitch bonded to the rear of the first bonding wire 130. ) Can be formed close to the vertical, it is possible to ensure a sufficient gap between the first bonding wire 130 and the second bonding wire 150.

한편 본 실시예에서는 제 2 본딩 와이어(150)의 와이어 루프부(156)를 "??" 형태에 가깝게 형성된 예를 개시하였지만 이에 한정되는 것은 아니며, 제 1 본딩 와이어(130)의 간격을 유지할 수 있는 범위내에서 경사지게 형성할 수도 있다. 즉 제 2 본딩 와이어의 제 1 본딩부는 와이어 꼬리를 갖기 때문에, 와이어 루프부의 경사도를 용이하게 조절할 수 있다. 이로 인해 제 2 본딩 와이어를 로프부를 제 1 본딩 와이어와 이격되면서 일정 각도록 형성하지 형성할 수 있다.In the present embodiment, the wire loop portion 156 of the second bonding wire 150 is referred to as "??" An example formed close to the shape is disclosed, but is not limited thereto, and may be formed to be inclined within a range capable of maintaining a distance between the first bonding wires 130. That is, since the first bonding portion of the second bonding wire has a wire tail, the inclination of the wire loop portion can be easily adjusted. For this reason, the second bonding wire may be formed not to be formed at a predetermined angle while being spaced apart from the first bonding wire.

범프 리버스 스티치 본딩 방법을 이용한 칩 적층 방법Chip stacking method using bump reverse stitch bonding method

이와 같은 본 발명의 실시예에 따른 칩 적층 구조를 형성하는 방법에 대해서 도 3a 내지 도 3h를 참조하여 설명하면 다음과 같다.A method of forming a chip stack structure according to an exemplary embodiment of the present invention will be described with reference to FIGS. 3A to 3H as follows.

칩 적층 구조를 형성하는 방법은, 도 3a에 도시된 바와 같이, 칩 실장 영역(114)에 제 1 및 제 2 칩(120, 140)이 차례로 적층된 배선기판(110)을 준비하는 단계로부터 출발한다. 배선기판(110)의 칩 실장 영역(114)에 제 1 칩(120)이 부착된다. 제 1 칩(120)의 제 1 칩 패드(122)와 배선기판(110)의 리드(112)는 제 1 본딩 와이어(130)에 의해 전기적으로 연결된다. 그리고 제 1 칩(120) 위에 제 2 칩(120)이 적층된다.As shown in FIG. 3A, a method of forming a chip stack structure starts from preparing a wiring board 110 in which first and second chips 120 and 140 are sequentially stacked in a chip mounting region 114. do. The first chip 120 is attached to the chip mounting region 114 of the wiring board 110. The first chip pad 122 of the first chip 120 and the lead 112 of the wiring board 110 are electrically connected by the first bonding wire 130. The second chip 120 is stacked on the first chip 120.

본 실시예에서는 제 1 칩(120) 보다 작은 제 2 칩(140)이 제 1 칩(120) 위에 적층된 예를 개시하였지만 이에 한정되는 것은 아니며, 제 2 칩으로 제 1 칩과 동일하거나 큰 반도체 칩이 사용될 수 있다. 이 경우 제 1 칩과 제 2 칩 사이에는 스페이서(spacer)가 개재된다.In the present exemplary embodiment, an example in which a second chip 140 smaller than the first chip 120 is stacked on the first chip 120 is disclosed, but is not limited thereto. The second chip may be the same as or larger than the first chip. Chips can be used. In this case, a spacer is interposed between the first chip and the second chip.

다음으로 도 3b 및 도 3c에 도시된 바와 같이, 볼 범프(152)를 형성하는 단계가 진행된다. 즉 와이어 본딩을 수행하는 와이어 본더에서, 제 2 본딩 와이어(150)가 장착된 캐필러리(172)가 제 2 칩(140)의 제 2 칩 패드(142) 위에 볼 범프(152)를 형성한다. 예컨대, EPO(Electric Frame Off) 방전을 통해 캐필러리(172)의 끝단으로 돌출된 본딩 와이어(150) 끝단에 볼(151)을 형성한 다음 제 2 칩 패드 (142)에 소정의 하중과 초음파 에너지를 캐필러리(172)의 하단에 전달하면, 볼(151)이 눌리면서 제 2 칩 패드(142)에 접합된다. 이어서 볼 범프(152)를 형성한 캐필러리(172)가 볼 범프(151) 위의 제 2 본딩 와이어(150)를 와이어 클램프(174)를 이용하여 끊는다. 제 2 본딩 와이어(150)를 끊는 방법은, 캐필러리(172)의 상단에 위치한 와이어 클램프(174)가 제 2 본딩 와이어(150)를 고정한 상태에서 와이어 클램프(174)와 함께 캐필러리(172)가 윗방향으로 올라감으로써 절단이 이루어진다. 제 2 본딩 와이어(150)로는 금선(gold wire)이 사용된다.Next, as shown in FIGS. 3B and 3C, the step of forming the ball bumps 152 proceeds. That is, in the wire bonder that performs wire bonding, the capillary 172 on which the second bonding wire 150 is mounted forms the ball bump 152 on the second chip pad 142 of the second chip 140. . For example, the ball 151 is formed at the end of the bonding wire 150 protruding to the end of the capillary 172 through the electric frame off (EPO) discharge, and then a predetermined load and ultrasonic waves are applied to the second chip pad 142. When energy is transferred to the lower end of the capillary 172, the ball 151 is pressed and bonded to the second chip pad 142. Subsequently, the capillary 172 forming the ball bump 152 breaks the second bonding wire 150 on the ball bump 151 using the wire clamp 174. The method of disconnecting the second bonding wire 150 may include a capillary with the wire clamp 174 while the wire clamp 174 positioned at the top of the capillary 172 fixes the second bonding wire 150. The cutting is made by 172 rising upwards. A gold wire is used as the second bonding wire 150.

다음으로 도 3d에 도시된 바와 같이, 캐필러리(172) 하단으로 제 2 본딩 와이어(150)를 일정 길이 인출시켜 와이어 꼬리(153)를 형성한다. 이때 캐필러리(172) 하단으로 일정 길이의 와이어 꼬리(153)를 인출시키는 방법은 와이어 클램프(174)를 일정 시간 개폐하는 방법이 사용될 수 있다. 또는 전술된 볼 범프를 형성하는 단계에서, 캐필러리 하단으로 일정 길이의 제 2 본딩 와이어가 남도록 볼 범프에서 끊어 와이어 꼬리를 형성할 수도 있다.Next, as illustrated in FIG. 3D, the second bonding wire 150 is drawn out to a lower end of the capillary 172 to form a wire tail 153. In this case, a method of drawing the wire tail 153 of a predetermined length to the bottom of the capillary 172 may be used to open and close the wire clamp 174 for a predetermined time. Alternatively, in the forming of the ball bump described above, the wire tail may be cut off from the ball bump such that a second bonding wire of a predetermined length remains at the bottom of the capillary.

다음으로 도 3e에 도시된 바와 같이, 배선기판(110)의 리드(112)에 1차 스티치 본딩하는 단계가 진행된다. 즉 캐필러리(172)가 배선기판(110)의 리드(112)로 이동한 상태에서, 인출된 와이어 꼬리(153)의 일단부에 소정의 하중과 초음파 에너지를 전달하여 리드(112)에 1차 스티치 본딩하여 제 1 본딩부(154)를 형성한다. 이때 제 1 본딩부(154)는 제 1 본딩 와이어(130)의 제 1 본딩부(134)보다는 뒤쪽에 형성된다.Next, as shown in FIG. 3E, the first stitch bonding process is performed on the lead 112 of the wiring board 110. That is, in a state where the capillary 172 moves to the lead 112 of the wiring board 110, a predetermined load and ultrasonic energy are transferred to one end of the drawn wire tail 153 to the lead 112. Different stitch bonding forms the first bonding portion 154. In this case, the first bonding portion 154 is formed behind the first bonding portion 134 of the first bonding wire 130.

제 1 본딩부(154)는 1차 스티치 본딩 지점에서 뒤쪽으로 일정 길이의 와이어 꼬리(153)가 위치한다. 제 1 본딩부(154)의 와이어 꼬리(153)는 위쪽을 향하고 있다.The first bonding portion 154 has a wire tail 153 of a predetermined length rearward from the first stitch bonding point. The wire tail 153 of the first bonding portion 154 faces upward.

계속해서 도 3f에 도시된 바와 같이, 와이어 루프부(156)를 형성하는 단계가 진행된다. 즉 캐필러리(172)가 제 1 본딩부(154)에서 제 2 칩(140)의 볼 범프(152)의 상부면보다는 적어도 높게 수직에 가깝게 상승한 후 반도체 칩(140)의 볼 범프(152)를 향하여 이동하여 "??"자 형태의 와이어 루프부(156)를 형성한다.Subsequently, as shown in FIG. 3F, the step of forming the wire loop portion 156 is performed. That is, after the capillary 172 rises closer to the vertical at least higher than the upper surface of the ball bump 152 of the second chip 140 in the first bonding part 154, the ball bump 152 of the semiconductor chip 140 is formed. To move toward to form a wire loop portion 156 of the "??" shape.

이때 제 2 본딩 와이어(150)는 제 1 본딩부(154)에서 수직에 가깝게 상승하여 와이어 루프부(156)를 형성하기 때문에, 리드(112)에 스티치 본딩된 제 1 본딩 와이어(130)와 충분한 간격을 유지하면서 와이어 루프부(156)를 형성할 수 있다.At this time, since the second bonding wire 150 rises close to the vertical in the first bonding portion 154 to form the wire loop portion 156, the second bonding wire 150 is sufficiently formed with the first bonding wire 130 stitch-bonded to the lid 112. The wire loop portion 156 may be formed while maintaining the gap.

다음으로 도 3g에 도시된 바와 같이, 제 2 칩(140)의 볼 범프(152) 위에 제 2 본딩 와이어(150)의 타단을 2차 스티치 본딩으로 마무리하여 제 2 본딩부(158)를 형성한다. 즉 캐필러리(172)가 제 2 칩(140)의 볼 범프(152) 위로 이동한 제 2 본딩 와이어(150)의 타단에 소정의 하중과 초음파 에너지를 전달하여 2차 스티치 본딩하여 제 2 본딩부(158)를 형성한다.Next, as shown in FIG. 3G, the second end of the second bonding wire 150 is finished by the second stitch bonding on the ball bump 152 of the second chip 140 to form the second bonding part 158. . That is, the capillary 172 transfers a predetermined load and ultrasonic energy to the other end of the second bonding wire 150 moved over the ball bump 152 of the second chip 140 to bond the second stitch to the second bonding. Form part 158.

마지막으로 도 3h에 도시된 바와 같이, 와이어 클램프(174)로 제 2 본딩 와이어(150)를 제 2 본딩부(158)에서 끊음으로써 제 2 칩(140)과 배선기판(110)을 전기적으로 연결하는 와이어 본딩 공정이 완료된다.Finally, as shown in FIG. 3H, the second chip 140 and the wiring board 110 are electrically connected by disconnecting the second bonding wire 150 from the second bonding part 158 by the wire clamp 174. The wire bonding process is completed.

그리고 이후에 일반적인 반도체 패키지 제조 공정이 진행될 수 있다. 즉 배선기판(110)의 상부면에 적층된 제 1 칩(120)과 제 2 칩(140), 제 1 본딩 와이어(130)와 제 2 본딩 와이어(150) 및 리드(112)를 봉합하는 수지 봉합부를 형성하는 공정과, 외부접속단자를 형성하는 공정이 순차적으로 진행될 수 있다.Thereafter, a general semiconductor package manufacturing process may be performed. That is, the resin sealing the first chip 120 and the second chip 140, the first bonding wire 130, the second bonding wire 150, and the lead 112 stacked on the upper surface of the wiring board 110. The process of forming the sealing portion and the process of forming the external connection terminal may be performed sequentially.

한편, 본 명세서와 도면에 개시된 본 발명의 실시예들은 이해를 돕기 위해 특정 예를 제시한 것에 지나지 않으며, 본 발명의 범위를 한정하고자 하는 것은 아니다. 여기에 개시된 실시예들 이외에도 본 발명의 기술적 사상에 바탕을 둔 다른 변형예들이 실시 가능하다는 것은, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 자명한 것이다. 예컨대 본 실시예에서는 배선기판 위에 두 개의 반도체 칩 적층된 예를 개시하였지만, 세 개 이상의 반도체 칩을 적층할 수 있음은 물론이며, 본 실시예에 따른 범프 리버스 스티치 본딩 방법으로 제 3 본딩 와이어를 형성하여 제 3 칩과 배선기판을 연결할 수 있다. 이때 제 3 본딩 와이어는 제 2 본딩 와이어와의 간격을 충분히 확보하면서 형성할 수 있다.On the other hand, the embodiments of the present invention disclosed in the specification and drawings are merely presented specific examples to aid understanding, and are not intended to limit the scope of the present invention. In addition to the embodiments disclosed herein, it is apparent to those skilled in the art that other modifications based on the technical idea of the present invention may be implemented. For example, in the present embodiment, an example in which two semiconductor chips are stacked on a wiring board is disclosed, but three or more semiconductor chips may be stacked, and a third bonding wire may be formed by the bump reverse stitch bonding method according to the present embodiment. The third chip and the wiring board can be connected to each other. In this case, the third bonding wire may be formed while sufficiently securing the gap with the second bonding wire.

따라서, 본 발명에 따른 범프 리버스 스티치 본딩 방법에 따르면, 리드에 제 1 및 제 2 본딩 와이어가 모두 스티치 본딩 방법으로 본딩되기 때문에, 배선기판의 리드와 본딩 와이어 사이의 접합 선뢰성을 확보할 수 있다. Therefore, according to the bump reverse stitch bonding method according to the present invention, since both the first and second bonding wires are bonded to the leads by the stitch bonding method, the joint fastness between the leads of the wiring board and the bonding wires can be secured. .

그리고 배선기판의 리드에 와이어 꼬리를 갖는 제 1 본딩부를 스티치 본딩함으로써, 제 1 본딩부의 1차 스티치 본딩 지점에서 수직에 가깝게 와이어 루프부를 형성할 수 있기 때문에, 제 1 및 제 2 본딩 와이어가 하나의 리드에 스티치 본딩되더라도 제 1 본딩 와이어와 제 2 본딩 와이어 사이의 간격을 충분히 확보할 수 있다.Further, by stitch bonding the first bonding portion having the wire tail to the lead of the wiring board, the wire loop portion can be formed close to the vertical at the first stitch bonding point of the first bonding portion. Even if the stitch is bonded to the lead, the gap between the first bonding wire and the second bonding wire can be sufficiently secured.

Claims (9)

(a) 칩 패드들을 갖는 반도체 칩이 실장되어 있으며, 상기 반도체 칩에 근접하게 리드가 형성된 배선기판을 제공하는 단계와;(a) providing a wiring board having a semiconductor chip having chip pads mounted thereon and having a lead proximate the semiconductor chip; (b) 본딩 와이어가 장착된 캐필러리가 상기 반도체 칩의 칩 패드에 볼 범프를 형성하는 단계와;(b) forming a ball bump on a chip pad of the semiconductor chip by a capillary having a bonding wire; (c) 상기 캐필러리가 상기 볼 범프에서 상기 본딩 와이어를 끊고, 상기 캐필러리 아래로 일정 길이의 본딩 와이어를 인출시키는 단계와;(c) the capillary breaking the bonding wire at the ball bumps, and drawing a length of bonding wire under the capillary; (d) 상기 캐필러리가 상기 인출된 본딩 와이어를 상기 배선기판의 리드에 1차 스티치 본딩하여 제 1 본딩부를 형성하는 단계와;(d) forming a first bonding portion by primary stitch bonding the drawn bonding wire to the lead of the wiring board by the capillary; (e) 상기 캐필러리가 상기 제 1 본딩부에서 상기 반도체 칩의 상부면보다는 적어도 높게 수직에 가깝게 상승한 후 상기 반도체 칩의 볼 범프를 향하여 이동하여 와이어 루프부를 형성하는 단계와;(e) forming a wire loop portion by moving the capillary toward the ball bump of the semiconductor chip after the capillary rises closer to the vertical at least higher than the upper surface of the semiconductor chip in the first bonding portion; (f) 상기 캐필러리가 상기 반도체 칩의 볼 범프 위에 상기 본딩 와이어를 2차 스티치 본딩하여 제 2 본딩부를 형성하는 단계; 및(f) the capillary forming a second bonding portion by second stitch bonding the bonding wire on the ball bumps of the semiconductor chip; And (g) 상기 캐필러리가 상기 반도체 칩의 볼 범프 위의 제 2 본딩부에서 상기 본딩 와이어를 끊는 단계;를 포함하는 것을 특징으로 하는 범프 리버스 스티치 본딩 방법.and (g) the capillary breaking the bonding wire at the second bonding portion on the ball bump of the semiconductor chip. 제 1항에 있어서, 상기 (d) 단계에서 상기 제 1 본딩부 뒤쪽으로 일정 길이 의 와이어 꼬리가 형성되는 것을 특징으로 하는 범프 리버스 스티치 본딩 방법.The method of claim 1, wherein a wire tail of a predetermined length is formed behind the first bonding part in the step (d). 제 1항 또는 제 2항에 있어서, 상기 본딩 와이어는 금선인 것을 특징으로 하는 범프 리버스 스티치 본딩 방법.The bump reverse stitch bonding method according to claim 1 or 2, wherein the bonding wire is a gold wire. (a) 상부면에 칩 실장 영역이 형성되어 있으며, 상기 칩 실장 영역에 근접하게 리드들이 형성된 배선기판을 준비하는 단계와;(a) preparing a wiring board having a chip mounting region formed on an upper surface thereof, the wiring substrate having leads formed adjacent to the chip mounting region; (b) 상부면에 제 1 칩 패드가 형성된 제 1 칩을 상기 칩 실장 영역에 부착하는 단계와;(b) attaching a first chip having a first chip pad formed on an upper surface thereof to the chip mounting region; (c) 상기 제 1 칩 패드와 상기 배선기판의 리드를 제 1 본딩 와이어로 연결하는 단계와;(c) connecting the first chip pad and the leads of the wiring board with a first bonding wire; (d) 상부면에 제 2 칩 패드가 형성된 제 2 칩을 상기 제 1 칩 위에 부착하는 단계; 및(d) attaching a second chip having a second chip pad formed on an upper surface thereof to the first chip; And (f) 상기 제 2 칩 패드와 상기 배선기판의 리드를 제 2 본딩 와이어로 연결하는 단계;를 포함하며,(f) connecting the second chip pad and the lead of the wiring board with a second bonding wire; 상기 (f) 단계는,Step (f), (f1) 상기 제 2 칩 패드에 볼 범프를 형성하는 단계와;(f1) forming a ball bump on the second chip pad; (f2) 상기 제 2 본딩 와이어의 일단부를 상기 리드에 1차 스티치 본딩하여 제 1 본딩부를 형성하는 단계와;(f2) forming a first bonding portion by first stitch bonding one end of the second bonding wire to the lead; (f3) 상기 제 1 본딩부에서 상기 제 2 칩의 상부면보다는 적어도 높게 수직 에 가깝게 상승시킨 후 상기 볼 범프를 향하여 이동하여 상기 제 1 본딩 와이어의 상부에 와이어 루프부를 형성하는 단계; 및(f3) forming a wire loop portion on the first bonding wire by raising toward the ball bumps at a height higher than the upper surface of the second chip at least higher than the upper surface of the second chip; And (f4) 상기 볼 범프 위에 상기 제 2 본딩 와이어의 타단을 2차 스티치 본딩하여 제 2 본딩부를 형성하는 단계;를 포함하는 것을 특징으로 하는 범프 리버스 스티치 본딩 방법을 이용한 칩 적층 방법.(f4) forming a second bonding portion by secondary stitch bonding the other end of the second bonding wire on the ball bumps; and stacking a chip using the bump reverse stitch bonding method. 제 4항에 있어서, 상기 (f2) 단계에서 상기 제 1 본딩부 뒤쪽으로 일정 길이의 와이어 꼬리가 형성되는 것을 특징으로 하는 범프 리버스 스티치 본딩 방법을 이용한 칩 적층 방법.5. The chip stacking method of claim 4, wherein a wire tail having a predetermined length is formed behind the first bonding unit in the step (f2). 6. 제 4항 또는 제 5항에 있어서, 상기 제 2 본딩 와이어는 금선인 것을 특징으로 하는 범프 리버스 스티치 본딩 방법을 이용한 칩 적층 방법.The chip stacking method using the bump reverse stitch bonding method according to claim 4 or 5, wherein the second bonding wire is a gold wire. 상부면에 칩 실장 영역이 형성되어 있으며, 상기 칩 실장 영역에 근접하게 리드들이 형성된 배선기판과;A wiring board having a chip mounting region formed on an upper surface thereof and having leads formed adjacent to the chip mounting region; 상기 칩 실장 영역에 부착되며, 상부면에 복수의 제 1 칩 패드가 형성된 제 1 칩과;A first chip attached to the chip mounting area and having a plurality of first chip pads formed on an upper surface thereof; 상기 제 1 칩 패드와 상기 리드를 전기적으로 연결하는 제 1 본딩 와이어와;A first bonding wire electrically connecting the first chip pad and the lead; 상기 제 1 칩 위에 부착되며, 상부면에 복수의 제 2 칩 패드가 형성된 제 2 칩; 및A second chip attached to the first chip and having a plurality of second chip pads formed on an upper surface thereof; And 상기 제 2 칩 패드와 상기 리드를 전기적으로 연결하는 제 2 본딩 와이어;를 포함하며,And a second bonding wire electrically connecting the second chip pad and the lead. 상기 제 2 본딩 와이어는,The second bonding wire, 상기 제 2 칩 패드들 위에 각각 형성된 볼 범프와;Ball bumps formed on the second chip pads, respectively; 상기 기판 패드에 1차 스티치 본딩되는 제 1 본딩부와;A first bonding part which is first stitch bonded to the substrate pad; 상기 제 1 본딩부에서 연장되어 상기 제 1 본딩 와이어의 상부에 형성되며, 상기 제 1 본딩부에서 상기 볼 범프보다는 적어도 높게 수직에 가깝게 상승한 후 상기 볼 범프를 향하여 뻗어 있는 와이어 루프부; 및A wire loop part extending from the first bonding part and formed on an upper portion of the first bonding wire, and extending toward the ball bump after being raised closer to the vertical at least higher than the ball bump in the first bonding part; And 상기 와이어 루프부와 연결되어 있으며, 상기 볼 범프 위에 2차 스티치 본딩되는 제 2 본딩부;를 포함하는 것을 특징으로 하는 범프 리버스 스티치 본딩 방법을 이용한 칩 적층 구조.And a second bonding portion connected to the wire loop portion and having a second stitch bonding on the ball bump. 2. 제 7항에 있어서, 상기 제 1 본딩부 뒤쪽으로 일정 길이의 와이어 꼬리가 형성된 것을 특징으로 하는 범프 리버스 스티치 본딩 방법을 이용한 칩 적층 구조.8. The chip stack structure of claim 7, wherein a wire tail having a predetermined length is formed behind the first bonding portion. 9. 제 7항 또는 제 8항에 있어서, 상기 제 2 본딩 와이어는 금선인 것을 특징으로 하는 범프 리버스 스티치 본딩 방법을 이용한 칩 적층 구조.The chip stack structure according to claim 7 or 8, wherein the second bonding wire is a gold wire.
KR1020050121790A 2005-12-12 2005-12-12 Bump reverse stitch bonding method, chip stack structure and method using the same KR20070062084A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013103962A1 (en) * 2012-01-06 2013-07-11 Texas Instruments Incorporated Integrated circuit device with wire bond connections

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013103962A1 (en) * 2012-01-06 2013-07-11 Texas Instruments Incorporated Integrated circuit device with wire bond connections

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