KR20070037272A - Plasma display apparatus and driving method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device and a driving method thereof, and more particularly, to a plasma display device and a method of driving the same, which ensure stable driving by preventing high temperature misdischarge.

The plasma display device according to the present invention includes a plasma display panel including scan electrodes divided into upper and lower scan electrode groups in a scan order, and an upper scan to apply a first scan bias voltage to the upper scan electrode group during an address period. And a lower scan driver configured to apply a second scan bias voltage smaller than the first scan bias voltage to the driver and the lower scan electrode group.

In addition, the driving method of the plasma display device according to the present invention is a method of driving a plasma display device in which a plurality of subfields are divided into a reset period, an address period, and a sustain period, respectively, and display an image in units of frames in which the subfields are combined. Applying a first scan bias voltage to the upper scan electrode group of the plasma display panel including the scan electrodes divided into the upper and lower scan electrode groups according to the scanning order during the address period and the first scan bias voltage to the lower scan electrode group And applying a smaller second scan bias voltage.

Description

Plasma Display Apparatus and Driving Method

1 is a perspective view showing the structure of a typical plasma display panel.

2 is a diagram illustrating a method of implementing image gradation of a conventional plasma display panel.

3 is a view showing a drive waveform of a conventional plasma display panel.

Fig. 4 is a diagram showing a high temperature misdischarge region in the driving process of the plasma display panel.

5 illustrates a plasma display device according to a first embodiment of the present invention.

6 illustrates a driving waveform of the plasma display device according to the first embodiment of the present invention.

7 illustrates a plasma display device according to a second embodiment of the present invention.

8 illustrates a driving waveform of a plasma display device according to a second embodiment of the present invention.

9 illustrates a plasma display device according to a third embodiment of the present invention.

FIG. 10 illustrates driving waveforms of a plasma display device according to a third exemplary embodiment of the present invention. FIG.

11 illustrates a plasma display device according to a fourth embodiment of the present invention.

12 illustrates driving waveforms of a plasma display device according to a fourth exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device and a driving method thereof, and more particularly, to a plasma display device and a method of driving the same, which ensure stable driving by preventing high temperature misdischarge.

In general, a plasma display panel forms a unit cell with a space between partition walls formed between a front substrate and a rear substrate, and each cell includes neon (Ne), helium (He), or a mixture of neon and helium (Ne +). A main discharge gas such as He) and an inert gas containing a small amount of xenon (Xe) are filled. When discharged by a high frequency voltage, the inert gas generates vacuum ultraviolet rays and emits phosphors formed between the partition walls to realize an image. Plasma display devices employing such plasma display panels have been spotlighted as next generation display devices because they can be made thin and light.

1 is a perspective view showing the structure of a typical plasma display panel.

As shown in FIG. 1, the plasma display panel is coupled in parallel with a front substrate 100, which is a display surface on which an image is displayed, and a rear substrate 110, which forms a rear surface, with a predetermined distance therebetween.

The front substrate 100 is based on the front glass 101, and scan electrodes 102 (Y electrodes) and sustain electrodes 103 (Z electrodes), that is, mutually discharged in one discharge cell and maintain light emission of the cells. The scan electrode 102 and the sustain electrode 103 formed of a transparent electrode a made of a transparent ITO material and a bus electrode b made of a metal material are formed in pairs. Scan electrode 102 and sustain electrode 103 are covered by one or more dielectric layers 104 that limit the discharge current and insulate the electrode pairs, and on top of dielectric layer 104 to facilitate discharge conditions. A protective layer 105 on which magnesium oxide (MgO) is deposited is formed.

The rear substrate 110 is arranged with the stripe-type (or well-type) partition walls 112 to form a plurality of discharge spaces, that is, discharge cells, based on the rear glass 111. In addition, a plurality of address electrodes 113 (X electrodes) for performing address discharge to generate vacuum ultraviolet rays are disposed in parallel with the partition wall 112. The upper surface of the rear substrate 110 is coated with R, G, B phosphors 114 that emit visible light for image display during address discharge. A white dielectric 115 is formed between the address electrode 113 and the phosphor 114 to protect the address electrode 113 and reflect the visible light emitted from the phosphor 114 to the front substrate 100.

A method of implementing gray levels of an image in such a plasma display panel will now be described with reference to FIG. 2.

2 is a diagram illustrating a method of implementing image grayscale of a conventional plasma display panel.

As shown in FIG. 2, the conventional plasma display panel performs time division driving by dividing one frame into several subfields having different number of emission times in order to realize gray level of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a discharge cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period RP, an address period AP, and a sustain period SP as described above. In this case, while the reset period RP and the address period AP of each subfield are the same for each subfield, the sustain period and the number of sustain pulses allocated thereto are 2 ⁿ (n = 0,1,2) in each subfield. 3,4,5,6,7).

3 is a diagram illustrating a driving waveform of a conventional plasma display panel.

Referring to FIG. 3, each of the subfields SF has a reset period RP for initializing the discharge cells of the entire screen, an address period AP for selecting the discharge cells, and a sustain for maintaining the discharge of the selected discharge cells. It includes a period SP.

In the reset period RP, the rising ramp waveform PR is simultaneously applied to all the scan electrodes Y in the setup period SU. The rising ramp waveform PR causes a weak discharge (setup discharge) to occur in the cells of the entire screen, thereby generating wall charges in the cells. After the rising ramp waveform PR is applied in the set down period SD, a predetermined period is applied from the positive sustain voltage Vs lower than the peak voltage of the rising ramp waveform PR to the negative scan voltage (-Vy). The falling ramp waveform NR falling to the slope is simultaneously applied to the scan electrodes Y. The falling ramp waveform NR generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, thereby uniformly retaining wall charges required for address discharges in the cells of the entire screen. .

In the address period AP, the negative scan pulse SCNP is sequentially applied to the scan electrodes Y, and the positive data pulse DP is applied to the address electrodes. As the voltage difference between the scan pulse SCNP and the data pulse DP and the wall voltage generated in the reset period RP are added, an address discharge is generated in the cell to which the data pulse DP is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, a positive bias voltage Vzb is applied to the sustain electrodes Z during the set down period SD and the address period AP.

In the sustain period SP, the sustain pulse SUSP is applied to the scan electrodes Y and the sustain electrodes Z alternately. Then, the cell selected by the address discharge is in the form of surface discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse SUSP is applied while the wall voltage and the sustain pulse SSUS in the cell are added. Sustain discharge, that is, display discharge for displaying an image, occurs.

In this way, the driving process of the plasma display panel in one subfield is completed.

4 is a diagram showing a high temperature mis-discharge region in the driving process of the plasma display panel.

As shown in FIG. 4, when the temperature of the surrounding environment is higher than room temperature, for example, 50 ° C. to 70 ° C. in the driving process of the plasma display panel, a high temperature misdischarge phenomenon in which the discharge cell is turned off at the center portion 400 of the screen is performed. appear. The high temperature mis-discharge phenomenon is particularly generated in the central portion 400 when the dual display type plasma display panel scans toward the center of the screen.

This mis-discharge due to high temperature is generally caused by wall charge loss during the address period.

In particular, the mis-discharge phenomenon due to the high temperature is caused by the leakage current caused by the temperature characteristic change of the protective layer or the dielectric layer. That is, the insulation characteristics of the dielectric are weakened as the internal and external temperatures of the discharge cells increase, and leakage of wall charges of the scan electrode and the sustain electrode occurs, thereby preventing sufficient discharge from occurring during the address period. In addition, at high temperature, since the movement of the space charge in the cell becomes active, recombination easily occurs, resulting in loss of wall charges, thereby causing mis-discharge.

Such high temperature mis-discharge phenomena act as a major factor to degrade the image display quality of the plasma display device.

An object of the present invention to solve this problem is to provide a plasma display device and a method of driving the same to ensure stable driving by preventing high-temperature mis-discharge.

According to an aspect of the present invention, there is provided a plasma display device including a plasma display panel including scan electrodes divided into upper and lower scan electrode groups according to a scanning order, and an upper scan electrode during an address period. And an upper scan driver for applying a first scan bias voltage to the group and a lower scan driver for applying a second scan bias voltage smaller than the first scan bias voltage to the lower scan electrode group.

The first scan bias voltage and the second scan bias voltage may be positive.

The minimum voltages of the pulses applied to the upper and lower scan electrode groups during the reset period are the same.

The magnitude of the first scan pulse applied to the upper scan electrode group during the address period may be equal to the magnitude of the second scan pulse applied to the lower scan electrode group.

The lowest voltage of the first scan pulse may be the same as the lowest voltage of the pulse applied to the upper scan electrode group during the reset period.

A plasma display device according to a second embodiment of the present invention includes a plasma display panel including scan electrodes divided into upper and lower scan electrode groups in a scan order, and a first scan bias voltage to the upper scan electrode group during an address period. And a lower scan driver configured to apply a second scan bias voltage greater than the first scan bias voltage to the upper scan driver and the lower scan electrode group to be applied.

The first scan bias voltage and the second scan bias voltage may be positive.

The minimum voltages of the pulses applied to the upper and lower scan electrode groups during the reset period are the same.

The magnitude of the first scan pulse applied to the upper scan electrode group during the address period may be equal to the magnitude of the second scan pulse applied to the lower scan electrode group.

The lowest voltage of the first scan pulse may be the same as the lowest voltage of the pulse applied to the upper scan electrode group during the reset period.

The plasma display device according to the third exemplary embodiment of the present invention applies a first scan bias voltage to the plasma display panel including the scan electrode and the scan electrode during the first half of the address period and then the first scan bias voltage during the second half of the address period. And a scan driver for applying a smaller second scan bias voltage.

The first scan bias voltage and the second scan bias voltage may be positive.

The magnitude of the first scan pulse applied to the scan electrode during the first half period of the address period is equal to the magnitude of the second scan pulse applied during the second half period of the address period.

The lowest voltage of the first scan pulse is characterized by the same as the lowest voltage of the pulse applied to the scan electrode during the reset period.

The plasma display device according to the fourth exemplary embodiment of the present invention applies a first scan bias voltage to the plasma display panel including the scan electrode and the scan electrode during the first half of the address period and then the first scan bias voltage during the second half of the address period. And a scan driver for applying a larger second scan bias voltage.

The first scan bias voltage and the second scan bias voltage may be positive.

The magnitude of the first scan pulse applied to the scan electrode during the first half period of the address period is equal to the magnitude of the second scan pulse applied during the second half period of the address period.

The lowest voltage of the first scan pulse is characterized by the same as the lowest voltage of the pulse applied to the scan electrode during the reset period.

In a driving method of a plasma display device according to a first embodiment of the present invention, a driving of a plasma display device in which a plurality of subfields is divided into a reset period, an address period, and a sustain period, respectively, and displays an image in frame units in which the subfields are combined. A method, comprising: applying a first scan bias voltage to an upper scan electrode group of a plasma display panel comprising scan electrodes divided into upper and lower scan electrode groups in a scan order during an address period; And applying a second scan bias voltage that is less than one scan bias voltage.

The first scan bias voltage and the second scan bias voltage may be positive.

The minimum voltages of the pulses applied to the upper and lower scan electrode groups during the reset period are the same.

The magnitude of the first scan pulse applied to the upper scan electrode group during the address period may be equal to the magnitude of the second scan pulse applied to the lower scan electrode group.

The lowest voltage of the first scan pulse may be the same as the lowest voltage of the pulse applied to the upper scan electrode group during the reset period.

In the driving method of the plasma display device according to the second embodiment of the present invention, a driving of the plasma display device in which a plurality of subfields are divided into a reset period, an address period, and a sustain period, respectively, and displays an image in frame units in which the subfields are combined. A method, comprising: applying a first scan bias voltage to an upper scan electrode group of a plasma display panel comprising scan electrodes divided into upper and lower scan electrode groups in a scan order during an address period; And applying a second scan bias voltage greater than one scan bias voltage.

The first scan bias voltage and the second scan bias voltage may be positive.

The minimum voltages of the pulses applied to the upper and lower scan electrode groups during the reset period are the same.

The magnitude of the first scan pulse applied to the upper scan electrode group during the address period may be equal to the magnitude of the second scan pulse applied to the lower scan electrode group.

The lowest voltage of the first scan pulse is the same as the lowest voltage of the pulse applied to the upper scan electrode group during the reset period.

A driving method of a plasma display device according to a third embodiment of the present invention is a method of driving a plasma display device, in which a plurality of subfields are divided into a reset period, an address period, and a sustain period, respectively, and display an image in frame units in which the subfields are combined. A method comprising: applying a first scan bias voltage to a scan electrode during a first half period of an address period and applying a second scan bias voltage less than the first scan bias voltage during a second half period of an address period. do.

The first scan bias voltage and the second scan bias voltage may be positive.

The magnitude of the first scan pulse applied to the scan electrode during the first half period of the address period is equal to the magnitude of the second scan pulse applied during the second half period of the address period.

The lowest voltage of the first scan pulse is characterized by the same as the lowest voltage of the pulse applied to the scan electrode during the reset period.

A driving method of a plasma display device according to a fourth embodiment of the present invention is a method of driving a plasma display device in which a plurality of subfields are divided into a reset period, an address period, and a sustain period, respectively, and display an image in frame units in which the subfields are combined. A method comprising: applying a first scan bias voltage to a scan electrode during a first half of an address period and applying a second scan bias voltage greater than the first scan bias voltage during a second half of an address period. do.

The first scan bias voltage and the second scan bias voltage may be positive.

The magnitude of the first scan pulse applied to the scan electrode during the first half period of the address period is equal to the magnitude of the second scan pulse applied during the second half period of the address period.

The lowest voltage of the first scan pulse is characterized by the same as the lowest voltage of the pulse applied to the scan electrode during the reset period.

Hereinafter, exemplary embodiments of a plasma display device and a driving method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

5 is a diagram illustrating a plasma display device according to a first embodiment of the present invention.

As shown in FIG. 5, in the plasma display device according to the first exemplary embodiment, the address electrodes X1 to Xm and the upper scan electrode group Y ₁ according to the scanning order in the reset period, the address period, and the sustain period. To Y _{n / 2} ) and the lower scan electrode group Y _{N / 2 + 1} to Y _N , and a predetermined driving pulse is applied to the scan electrodes Y1 to Yn and the sustain electrode Z connected in common. Plasma display panel 500 for generating gas discharge in space to represent an image, data driver 53 for supplying data to address electrodes X1 to Xm formed on a rear panel (not shown), and upper scan electrode Upper scan driver 54A for driving groups Y ₁ to Y _{n / 2} , Lower scan driver 54B for driving lower scan electrode groups Y _{N / 2 + 1} to Y _N , and a sustain electrode ( A sustain driver 55 for driving Z) and the respective drive parts 53, 54A, 54B, and 55; And a timing controller 56, and a driving voltage generator 57 for supplying a driving voltage to each drive unit (53,54A, 54B, 55) for controlling.

Hereinafter, functions and operations of the components of the plasma display device according to the first embodiment of the present invention will be described in detail.

First, although not shown, the plasma display panel 500 is bonded to the front panel (not shown) and the rear panel (not shown) spaced at regular intervals with a discharge space including an inert gas therebetween. For example, scan electrodes Y1 to Yn and sustain electrode Z are formed in pairs. In this case, the scan electrodes Y1 to Yn are divided into the upper scan electrode group Y ₁ to Y _{n / 2} and the lower scan electrode group Y _{N / 2 + 1} to Y _N according to the scanning order, respectively. It is driven by the scan driver 54A and the lower scan driver 54B. Meanwhile, the rear panel has address electrodes X1 to Xm to intersect the upper scan electrode group Y ₁ to Y _{n / 2} , the lower scan electrode group Y _{N / 2 + 1} to Y _N , and the sustain electrode Z. ) Is formed.

The data driver 53 is inversely gamma corrected and error spread by an inverse gamma correction circuit, an error diffusion circuit, or the like, and then data mapped to a subfield pattern preset by the subfield mapping circuit is supplied. The data driver 53 samples and latches data under the control of the timing controller 56, and then supplies the data to the address electrodes X1 to Xm.

The upper scan driver 54A and the lower scan driver 54B are each of the upper scan electrode group Y ₁ to Y _{n / 2} and the lower scan electrode group to initialize the entire screen during the reset period under the control of the timing controller 56. A reset waveform including a gradually rising set-up waveform and a gradually falling set-down waveform is simultaneously applied to (Y _{N / 2 + 1} to Y _N ).

In addition, the upper scan driver 54A includes the upper scan electrode groups Y ₁ to Y _{n / 2} to select a scan line during the address period after the reset waveform is supplied to the upper scan electrode groups Y ₁ to Y _{n / 2.} ) Sequentially applies a first scan pulse that falls from the first scan bias voltage V _SC1 and the first scan bias voltage V _SC1 to the negative first scan voltage -V _y1 .

The lower scan driver 54B also supplies the lower scan electrode group Y _{N / 2 +} to select the scan line during the address period after the reset waveform is supplied to the lower scan electrode groups Y _{N / 2 + 1} to Y _{N. 1} to Y _N) a first scan bias voltage (V _SC1) small second scan bias voltage (V _SC2) and the second scan voltage (-V _y2) of a negative polarity from the second scan bias voltage (V _SC2) than the Second scan pulses are sequentially applied.

In addition, the upper scan driver (54A) and the lower scan driver (54B) are each of the upper scan electrode group of a sustain pulse that allows occur a sustain discharge in cells selected in the address period during the sustain period (Y ₁ to Y _{n / 2)} and a lower It is supplied to the scan electrodes (Y _{N / 2 + 1} to Y _N).

The sustain driver 55 supplies a bias voltage having a sustain voltage V _S level to the sustain electrode Z during at least a portion of the reset period and an address period under the control of the timing controller 56, and then the upper portion during the sustain period. operating in the scan driver (54A) and the lower scan driver (54B) and alternately supplies a sustain pulse having a sustain voltage (V _S) level to the sustain electrode (Z).

The timing controller 56 receives the vertical / horizontal synchronization signals and generates timing control signals CTRX, CTRYT, CTRYB, and CTRZ required for each of the driving units 53, 54A, 54B, and 55, and the timing control signals CTRX, CTRYT. Each of the driving units 53, 54A, 54B, 55 is controlled by supplying the, CTRYB, CTRZ to the corresponding driving units 53, 54A, 54B, 55. The timing control signal CTRX applied to the data driver 53 includes a sampling clock for sampling data, a latch control signal, an energy recovery circuit, and a switch control signal for controlling on / off time of the driving switch element. The timing control signals CTRYT and CTRYB applied to the upper scan driver 54A and the lower scan driver 54B turn on / off the energy recovery circuit and the driving switch element in the upper scan driver 54A and the lower scan driver 54B. A switch control signal for controlling the off time is included. The timing control signal CTRZ applied to the sustain driver 55 includes a switch control signal for controlling the on / off time of the energy recovery circuit and the drive switch element in the sustain driver 55.

The driving voltage generator 57 includes a sustain voltage V _S , a setup ramp voltage V _ST , a first scan bias voltage V _SC1 , a second scan bias voltage V _SC2 , a data voltage Va, Various driving voltages required by each of the driving units 53, 54A, 54B, and 55 are generated, including one scan voltage (-V _y1 ), the second scan voltage (-V _y2 ), and the like. These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

Hereinafter, the operation principle of the plasma display device according to the first embodiment of the present invention will be described in detail with reference to FIG. 6.

6 illustrates a driving waveform of the plasma display device according to the first embodiment of the present invention.

As shown in FIG. 6, in the plasma display device according to the first exemplary embodiment, a reset period RP for initializing all cells, an address period AP for selecting a cell to be discharged, and a discharge of a selected cell are shown. It is driven by being divided into the sustain period SP for maintaining.

Hereinafter, the voltage applied to each period and its function will be described in detail.

First, in the reset period RP, in the setup period SU, all scan electrodes Y ₁ to Y _n divided into the upper scan electrode group YT and the lower scan electrode group YB according to the scanning order are positively defined. The setup ramp pulse PR of the polarity slope is applied simultaneously. The setup ramp pulse PR is an example of a setup waveform and may adopt various waveforms in a rising shape. This setup ramp pulse PR causes a weak dark discharge in the discharge cells of the entire screen. Due to this setup discharge, positive wall charges are accumulated on the address electrodes X1 to Xm and the sustain electrode Z, and negative wall charges are accumulated on the scan electrodes Y ₁ to Y _n .

Subsequently, in the set down period SD, all of the scan electrodes Y ₁ to Y _n are simultaneously applied with a set down ramp pulse NR having a negative slope, while a positive sustain voltage Vs is applied to the sustain electrode Z. When a bias voltage having a level is applied, the positive wall charges of the address electrodes X1 to Xm are maintained, but the sustain electrode Z is discharged through the discharge between the sustain electrode Z and the scan electrodes Y ₁ to Y _n . to define at the same time, the scan electrode to a predetermined amount canceling the negative wall charges (Y ₁ to Y _n) has sustain a large amount of negative charges into the electrode (Z) and the scan electrodes (Y ₁ to Y _n) accumulated on.

By this set down discharge, the wall charges such that the address discharge can stably occur remain uniformly in the cells.

The set down ramp pulse NR is an example of a set down waveform and may adopt various waveforms in a descending form.

Next, in the first half of the address period AP, the first scan pulse SCNP1 and the address electrode fall from the first scan bias voltage V _SC1 to the first scan voltage -V _y1 in the upper scan electrode group YT. When the data pulse DP1 rising from the ground GND to the positive data voltage Va is synchronously applied to the fields X1 to Xm, the voltage between the address electrodes X1 to Xm and the upper scan electrode group YT is synchronized. The address discharge occurs as the wall voltage between the address electrodes X1 to Xm and the upper scan electrode group YT due to the wall charges formed during the difference and the reset period RP is added.

In the second half of the address period AP, the second scan bias voltage V _SC2 smaller than the first scan bias voltage V _SC1 is lower than the first scan voltage −V _y1 in the lower scan electrode group YB. The second scan pulse SCNP2 falling to the scan voltage -V _y2 and the data pulse DP2 rising from the ground GND to the positive data voltage Va are synchronized with the address electrodes X1 to Xm. When applied, a wall between the address electrodes X1 to Xm and the lower scan electrode group YB due to the voltage difference between the address electrodes X1 to Xm and the lower scan electrode group YB and the wall charge formed during the reset period RP. As the voltage is added, an address discharge occurs.

In this way, the second scan bias voltage V _SC2 in the second half of the address period AP is set lower than the first scan bias voltage V _SC1 in the first half of the address period AP, and the second scan voltage ( By setting -V _y2 to be lower than the first scan voltage -V _y1 , the voltage difference between the address electrodes X1 to Xm and the lower scan electrode group YB in the second half of the address period AP is determined by the address period. (AP) The voltage difference between the address electrodes X1 to Xm and the upper scan electrode group YT in the first half is greater than that to generate a stronger address discharge, and thus an address period (AP) due to wall charge loss in a high temperature environment. ) The instability of the address discharge in the latter half is blocked in advance.

On the other hand, in the sustain electrode Z, the voltage difference between the scan electrodes Y1 to Yn is reduced during the address period AP so that mis-discharge with the scan electrodes Y1 to Yn does not occur, so that the sustain voltage Vs level is positive. A bias voltage with

Preferably, the first scan bias voltage V _SC1 and the second scan bias voltage V _SC2 are adjusted to have a positive polarity. As described above, the first scan bias voltage V _SC1 and the second scan bias voltage V _SC2 are adjusted to the positive polarity, thereby providing the upper scan electrode group YT and the lower scan electrode group YB during the set down period SD. The formed negative wall charge is more efficiently maintained in a high temperature environment to prepare for address discharge.

During the reset period RP, the minimum voltage (-V _y1 ) of the pulses applied to the upper scan electrode group YT and the lower scan electrode group YB is preferably adjusted in the same manner. Thus, by identically adjusting the minimum voltage (-V _y1) of the pulse it is applied to the upper scanning electrodes (YT) and the lower scan electrode group (YB) is supplied during the reset period (RP), for supplying a lowest voltage of the pulse The voltage source can be made common, thereby reducing the manufacturing cost of the plasma display device.

The magnitude V _SC1 + V _y1 of the first scan pulse SCNP1 applied to the upper scan electrode group YT during the address period AP is the second scan pulse SCNP2 applied to the lower scan electrode group YB. It is preferable to adjust the size of V _SC2 + V _y2 . In this manner, by adjusting the magnitude of the first scan pulse SCNP1 (V _SC1 + V _y1 ) and the magnitude of the second scan pulse SCNP2 (V _SC2 + V _y2 ), the scan driver IC is applied to the scan driver IC during the address period AP. By keeping the level of the scan pulse voltage applied constant, heat generation of the scan driver IC is suppressed, thereby ensuring stable driving.

The minimum voltage (-V _y1 ) of the first scan pulse SCNP1 is preferably adjusted to be equal to the minimum voltage (-V _y1 ) of the pulse applied to the upper scan electrode group YT during the reset period RP. By adjusting to equal this way the first scan pulse minimum voltage (-V _y1) to the minimum voltage (-V _y1) of the pulse is applied to the upper scanning electrodes (YT) during the reset period (RP) of (SCNP1), the The manufacturing cost of the plasma display device is reduced by using a common voltage source for supplying the lowest voltage of the pulse applied to the upper scan electrode group YT during one scan pulse SCNP1 and the reset period RP.

Next, in the sustain period SP, a sustain pulse rising from the ground GND to the sustain voltage Vs is alternately applied to the upper scan electrode group YT, the lower scan electrode group YB, and the sustain electrode Z. SUSP) is applied. The cell selected by the address discharge is added between the upper and lower scan electrode groups YT and YB and the sustain electrode Z every time the sustain pulse SSUS is applied as the wall voltage and the sustain pulse SSUS in the cell are added. Sustain discharge, that is, display discharge, occurs.

In this way, the driving process of the plasma display device according to the first embodiment of the present invention in one subfield is completed.

As described in detail above, the plasma display device according to the first exemplary embodiment of the present invention divides the scan electrodes into upper and lower scan electrode groups according to the scanning order, and applies the scan bias voltage applied to the upper scan electrode group during the address period. By lowering the level of the scan bias voltage applied to the lower scan electrode group, instability of the address discharge in the latter part of the address period AP due to the wall charge loss in the high temperature environment is blocked in advance to improve the driving efficiency.

7 is a diagram illustrating a plasma display device according to a second embodiment of the present invention.

As shown in FIG. 7, in the plasma display device according to the second exemplary embodiment, the address electrodes X1 to Xm and the upper scan electrode group Y ₁ according to the scanning order in the reset period, the address period, and the sustain period. To Y _{n / 2} ) and the lower scan electrode group Y _{N / 2 + 1} to Y _N , and a predetermined driving pulse is applied to the scan electrodes Y1 to Yn and the sustain electrode Z connected in common. Plasma display panel 700 for generating gas discharge in space to represent an image, data driver 73 for supplying data to address electrodes X1 to Xm formed on a rear panel (not shown), and upper scan electrode Upper scan driver 74A for driving groups Y ₁ to Y _{n / 2} , Lower scan driver 74B for driving lower scan electrode groups Y _{N / 2 + 1} to Y _N , and a sustain electrode ( A sustain driver 75 for driving Z), and each driver 73, 74A, 74B, 75; And a timing controller 76, and a driving voltage generator 77 for supplying a driving voltage to each drive unit (73,74A, 74B, 75) for controlling.

Hereinafter, functions and operations of each component of the plasma display device according to the second embodiment of the present invention will be described in detail.

Although not shown, the plasma display panel 700 is bonded to the front panel (not shown) and the rear panel (not shown) by being spaced apart at regular intervals with a discharge space including an inert gas therebetween. For example, scan electrodes Y1 to Yn and sustain electrode Z are formed in pairs. In this case, the scan electrodes Y1 to Yn are divided into the upper scan electrode group Y ₁ to Y _{n / 2} and the lower scan electrode group Y _{N / 2 + 1} to Y _N according to the scanning order, respectively. It is driven by the scan driver 74A and the lower scan driver 74B. Meanwhile, the rear panel has address electrodes X1 to Xm to intersect the upper scan electrode group Y ₁ to Y _{n / 2} , the lower scan electrode group Y _{N / 2 + 1} to Y _N , and the sustain electrode Z. ) Is formed.

The data driver 73 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like not shown, and then data mapped to a subfield pattern preset by the subfield mapping circuit is supplied. The data driver 73 samples and latches data under the control of the timing controller 76, and then supplies the data to the address electrodes X1 to Xm.

The upper scan driver 74A and the lower scan driver 74B are each of the upper scan electrode group Y ₁ to Y _{n / 2} and the lower scan electrode group to initialize the whole screen during the reset period under the control of the timing controller 76. A reset waveform including a gradually rising set-up waveform and a gradually falling set-down waveform is simultaneously applied to (Y _{N / 2 + 1} to Y _N ).

In addition, the upper scan driver 74A includes the upper scan electrode groups Y ₁ to Y _{n / 2} to select a scan line during the address period after the reset waveform is supplied to the upper scan electrode groups Y ₁ to Y _{n / 2.} ) Is sequentially applied a first scan pulse that falls from the first scan bias voltage V _2SC1 and the first scan bias voltage V _2SC1 to the negative first scan voltage -V _2y1 .

The lower scan driver 74B also supplies the lower scan electrode group Y _{N / 2 +} to select the scan line during the address period after the reset waveform is supplied to the lower scan electrode groups Y _{N / 2 + 1} to Y _{N. 1} to Y _N) a first scan bias voltage (V _2SC1) larger second scan bias voltage (V _2SC2) and the second scan voltage (-V _2y2) of negative polarity from the second scan bias voltage (V _2SC2) than in the The falling second scan pulse is sequentially applied.

In addition, the upper scan driver (74A) and the lower scan driver (74B) are each of the upper scan electrode group of a sustain pulse that allows occur a sustain discharge in cells selected in the address period during the sustain period (Y ₁ to Y _{n / 2)} and a lower It is supplied to the scan electrodes (Y _{N / 2 + 1} to Y _N).

The sustain driver 75 supplies a bias voltage having a sustain voltage V _S level to the sustain electrode Z during at least a portion of the reset period and an address period under the control of the timing controller 76, and then the upper portion during the sustain period. operating in the scan driver (74A) and the lower scan driver (74B) and alternately supplies a sustain pulse having a sustain voltage (V _S) level to the sustain electrode (Z).

The timing controller 76 receives the vertical / horizontal synchronization signal and generates timing control signals CTRX, CTRYT, CTRYB, and CTRZ required for the respective driving units 73, 74A, 74B, and 75, and the timing control signals CTRX, CTRYT. Each of the driving units 73, 74A, 74B, 75 is controlled by supplying CTRYB, CTRZ to the corresponding driving units 73, 74A, 74B, 75. The timing control signal CTRX applied to the data driver 73 includes a sampling clock for sampling data, a latch control signal, an energy recovery circuit, and a switch control signal for controlling on / off time of the driving switch element. The timing control signals CTRYT and CTRYB applied to the upper scan driver 74A and the lower scan driver 74B turn on / off the energy recovery circuit and the driving switch elements in the upper scan driver 74A and the lower scan driver 74B. A switch control signal for controlling the time is included. The timing control signal CTRZ applied to the sustain driver 75 includes a switch control signal for controlling the on / off time of the energy recovery circuit and the drive switch element in the sustain driver 75.

The driving voltage generator 77 includes a sustain voltage V _S , a setup ramp voltage V _ST , a first scan bias voltage V _2SC1 , a second scan bias voltage V _2SC2 , a data voltage Va, Various driving voltages required by each of the driving units 73, 74A, 74B, and 75 are generated including one scan voltage (-V _2y1 ), a second scan voltage (-V _2y2 ), and the like. These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

Hereinafter, the operation principle of the plasma display device according to the second embodiment of the present invention will be described in detail with reference to FIG. 8.

8 illustrates a driving waveform of the plasma display device according to the second embodiment of the present invention.

As shown in FIG. 8, in the plasma display device according to the second exemplary embodiment, a reset period RP for initializing all cells, an address period AP for selecting a cell to be discharged, and discharge of a selected cell are shown. It is driven by being divided into the sustain period SP for maintaining.

Hereinafter, the voltage applied to each period and its function will be described in detail.

First, in the reset period RP, in the setup period SU, the scan period Y ₁ to Y _n is divided into the upper scan electrode group YT and the lower scan electrode group YB in the scanning order. The setup ramp pulse PR of the polarity slope is applied simultaneously. The setup ramp pulse PR is an example of a setup waveform and may adopt various waveforms in a rising shape. This setup ramp pulse PR causes a weak dark discharge in the discharge cells of the entire screen. Due to this setup discharge, positive wall charges are accumulated on the address electrodes X1 to Xm and the sustain electrode Z, and negative wall charges are accumulated on the scan electrodes Y ₁ to Y _n .

Subsequently, in the set down period SD, all of the scan electrodes Y ₁ to Y _n are simultaneously applied with a set down ramp pulse NR having a negative slope, while a positive sustain voltage Vs is applied to the sustain electrode Z. When a bias voltage having a level is applied, the positive wall charges of the address electrodes X1 to Xm are maintained, but the sustain electrode Z is discharged through the discharge between the sustain electrode Z and the scan electrodes Y ₁ to Y _n . to define at the same time, the scan electrode to a predetermined amount canceling the negative wall charges (Y ₁ to Y _n) has sustain a large amount of negative charges into the electrode (Z) and the scan electrodes (Y ₁ to Y _n) accumulated on.

By this set down discharge, the wall charges such that the address discharge can stably occur remain uniformly in the cells.

The set down ramp pulse NR is an example of a set down waveform and may adopt various waveforms in a descending form.

Next, in the first half of the address period AP, the first scan pulse SCNP1 and the address electrode fall from the first scan bias voltage V _2SC1 to the first scan voltage -V _2y1 in the upper scan electrode group YT. When the data pulse DP1 rising from the ground GND to the positive data voltage Va is synchronously applied to the fields X1 to Xm, the voltage between the address electrodes X1 to Xm and the upper scan electrode group YT is synchronized. The address discharge occurs as the wall voltage between the address electrodes X1 to Xm and the upper scan electrode group YT due to the wall charges formed during the difference and the reset period RP is added.

In the second half of the address period (AP) greater than the first scan voltage (-V _2y1) from a first scan bias voltage (V _2SC1) larger second scan bias voltage (V _2SC2) than in the lower scan electrode group (YB) 2 The second scan pulse SCNP2 falling to the scan voltage (-V _2y2 ) and the data pulse DP2 rising from the ground GND to the positive data voltage Va are synchronized with the address electrodes X1 to Xm. When applied, a wall between the address electrodes X1 to Xm and the lower scan electrode group YB due to the voltage difference between the address electrodes X1 to Xm and the lower scan electrode group YB and the wall charge formed during the reset period RP. As the voltage is added, an address discharge occurs.

In this way, the second scan bias voltage V _2SC2 in the second half of the address period AP is set higher than the first scan bias voltage V _2SC1 in the first half of the address period AP, thereby providing the reset period RP. ), The negative charges formed on the lower scan electrode group YB are kept stronger using electrostatic attraction than the negative charges formed on the upper scan electrode group YT, and thus The instability of the address discharge in the second half of the address period AP due to the wall charge loss is prevented in advance.

On the other hand, in the sustain electrode Z, the voltage difference between the scan electrodes Y1 to Yn is reduced during the address period AP so that mis-discharge with the scan electrodes Y1 to Yn does not occur, so that the sustain voltage Vs level is positive. A bias voltage with

_Preferably , the first scan bias voltage V _2SC1 and the second scan bias voltage V _2SC2 are adjusted to have a positive polarity. As such, by adjusting the first scan bias voltage V _2SC1 and the second scan bias voltage V _2SC2 to the positive polarity, the upper scan electrode group YT and the lower scan electrode group YB during the set-down period SD. The formed negative wall charge is maintained more efficiently in a high temperature environment by utilizing electrostatic attraction to prepare for address discharge.

The minimum voltage (-V _2y1 ) of the pulses applied to the upper scan electrode group YT and the lower scan electrode group YB during the reset period RP is preferably adjusted in the same manner. As described above, the minimum voltage (-V _2y1 ) of the pulses applied to the upper scan electrode group YT and the lower scan electrode group YB is adjusted and supplied during the reset period RP, thereby supplying the lowest voltage of the pulse. The voltage source can be made common, thereby reducing the manufacturing cost of the plasma display device.

The magnitude (V _2SC1 + V _2y1 ) of the first scan pulse SCNP1 applied to the upper scan electrode group YT during the address period AP is the second scan pulse SCNP2 applied to the lower scan electrode group YB. It is preferable to adjust the size of V 2 _SC2 + V _{2y 2} . Thus, by adjusting the magnitude of the first scan pulse SCNP1 (V _2SC1 + V _2y1 ) and the _magnitude of the second scan pulse SCNP2 (V _2SC2 + V _2y2 ) to the scan driver IC during the address period AP. By keeping the level of the scan pulse voltage applied constant, heat generation of the scan driver IC is suppressed, thereby ensuring stable driving.

The minimum voltage (-V _2y1 ) of the first scan pulse SCNP1 is preferably adjusted to be equal to the minimum voltage (-V _2y1 ) of the pulse applied to the upper scan electrode group YT during the reset period RP. By adjusting to equal this way the first scan pulse minimum voltage (-V _2y1) a minimum voltage (-V _2y1) of the pulse is applied to the upper scanning electrodes (YT) during the reset period (RP) of (SCNP1), the The manufacturing cost of the plasma display device is reduced by using a common voltage source for supplying the lowest voltage of the pulse applied to the upper scan electrode group YT during one scan pulse SCNP1 and the reset period RP.

Next, in the sustain period SP, the sustain pulse SSUS rising from the ground GND to the sustain voltage Vs alternately to the upper scan electrode group YT, the lower scan electrode group YB, and the sustain electrode Z. ) Is applied. The cell selected by the address discharge is added between the upper and lower scan electrode groups YT and YB and the sustain electrode Z every time the sustain pulse SSUS is applied as the wall voltage and the sustain pulse SSUS in the cell are added. Sustain discharge, that is, display discharge, occurs.

In this way, the driving process of the plasma display device according to the second embodiment of the present invention in one subfield is completed.

As described in detail above, the plasma display device according to the second exemplary embodiment of the present invention divides the scan electrodes into upper and lower scan electrode groups according to the scanning order, and applies a scan bias voltage applied to the upper scan electrode group during the address period. By increasing the level of the scan bias voltage applied to the lower scan electrode group, the driving efficiency is improved by blocking the instability of the address discharge in the latter part of the address period AP due to the wall charge loss in the high temperature environment in advance.

9 is a diagram illustrating a plasma display device according to a third embodiment of the present invention.

As shown in FIG. 9, the plasma display device according to the third exemplary embodiment of the present invention is connected to the address electrodes X1 to Xm, the scan electrodes Y1 to Yn, and are commonly connected in the reset period, the address period, and the sustain period. A predetermined driving pulse is applied to the sustain electrode Z to generate a gas discharge in the discharge space, thereby expressing an image, and to the address electrodes X1 to Xm formed on the rear panel (not shown). A data driver 91 for supplying data, a scan driver 92 for driving the scan electrodes Y1 to Yn, a sustain driver 93 for driving the sustain electrode Z, and respective drivers 91,92. And a timing controller 94 for controlling 93 and a driving voltage generator 95 for supplying a driving voltage to each of the driving units 91, 92, and 93.

Hereinafter, functions and operations of the components of the plasma display device according to the third embodiment of the present invention will be described in detail.

First, although not shown, the plasma display panel 900 is bonded to the front panel (not shown) and the rear panel (not shown) by being spaced apart at regular intervals with a discharge space including an inert gas therebetween. For example, scan electrodes Y1 to Yn and sustain electrode Z are formed in pairs. Meanwhile, address electrodes X1 to Xm are formed on the rear panel to intersect the scan electrodes Y1 to Yn and the sustain electrode Z.

The data driver 91 is subjected to inverse gamma correction and error diffusion by an inverse gamma correction circuit, an error diffusion circuit, and the like not shown, and then data mapped to a subfield pattern preset by the subfield mapping circuit is supplied. The data driver 91 samples and latches data under the control of the timing controller 94 and then supplies the data to the address electrodes X1 to Xm.

The scan driver 92 includes a set-up waveform that gradually rises and a set-down waveform that gradually rises to the scan electrodes Y1 to Yn to initialize the entire screen during the reset period under the control of the timing controller 94. Apply the reset waveform simultaneously.

In addition, during the address period after the reset waveform is supplied to the scan electrodes Y1 to Yn, the scan driver 92 includes a first period during the first half period of the air dress period to select the scan line. The first scan bias voltage during the second half of the address period and the first scan pulse that falls from the scan bias voltage V _3SC1 and the first scan bias voltage V _3SC1 to the negative first scan voltage -V _3y1 a second scan pulse which falls to a second scan voltage (-V _3y2) the negative than V _3SC1) from a smaller second scan bias voltage (V _3SC2) are applied sequentially.

In addition, the scan driver 92 supplies a sustain pulse to the scan electrodes Y1 to Yn to allow sustain discharge to occur in the selected cell in the address period during the sustain period.

The sustain driver 93 supplies a bias voltage having a sustain voltage V _S level to the sustain electrode Z during at least a part of the reset period and an address period under the control of the timing controller 94, and then scans the sustain period Z during the sustain period. It operates to drive 92 and alternately supplies a sustain pulse having a sustain voltage (V _S) level to the sustain electrode (Z).

The timing controller 94 receives the vertical / horizontal synchronization signals, generates timing control signals CTRX, CTRY, and CTRZ required for each of the driving units 91, 92, and 93, and generates the timing control signals CTRX, CTRY, and CTRZ. Each of the driving units 91, 92, 93 is controlled by supplying the driving units 91, 92, 93. The timing control signal CTRX applied to the data driver 91 includes a sampling clock for sampling data, a latch control signal, an energy recovery circuit, and a switch control signal for controlling on / off time of the driving switch element. The timing control signal CTRY applied to the scan driver 92 includes an energy recovery circuit in the scan driver 92 and a switch control signal for controlling on / off time of the driving switch element. The timing control signal CTRZ applied to the sustain driver 93 includes a switch control signal for controlling the on / off time of the energy recovery circuit and the drive switch element in the sustain driver 93.

The driving voltage generator 95 includes a sustain voltage V _S , a setup ramp voltage V _ST , a first scan bias voltage V _3SC1 , a second scan bias voltage V _3SC2 , a data voltage Va, Various driving voltages required by each of the driving units ₉₁ , ₉₂ , and 93 are generated, including one scan voltage (-V _3y1 ) and the second scan voltage (-V _3y2 ). These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

Hereinafter, the operation principle of the plasma display device according to the third embodiment of the present invention will be described in detail with reference to FIG. 10.

10 illustrates a driving waveform of the plasma display device according to the third embodiment of the present invention.

As shown in FIG. 10, in the plasma display device according to the third exemplary embodiment, a reset period RP for initializing all cells, an address period AP for selecting a cell to be discharged, and a discharge of a selected cell are shown. It is driven by being divided into the sustain period SP for maintaining.

Hereinafter, the voltage applied to each period and its function will be described in detail.

First, in the reset period RP, the setup ramp pulse PR of the positive slope is simultaneously applied to all the scan electrodes Y ₁ to Y _{n in the} setup period SU. The setup ramp pulse PR is an example of a setup waveform and may adopt various waveforms in a rising shape. This setup ramp pulse PR causes a weak dark discharge in the discharge cells of the entire screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

Subsequently, in the set down period SD, all of the scan electrodes Y ₁ to Y _n are simultaneously applied with a set down ramp pulse NR having a negative slope, while a positive sustain voltage Vs is applied to the sustain electrode Z. When a bias voltage having a level is applied, the positive wall charge of the address electrode X is maintained but the positive wall charge of the sustain electrode Z is erased by a discharge between the sustain electrode Z and the scan electrode Y. At the same time, the sustain electrode Z and the scan electrode Y divide a large amount of the negative charge accumulated in the scan electrode Y.

By this set down discharge, the wall charges such that the address discharge can stably occur remain uniformly in the cells.

The set down ramp pulse NR is an example of a set down waveform and may adopt various waveforms in a descending form.

Next, the first scan pulse SCNP1 falls from the first scan bias voltage V _3SC1 to the first scan voltage −V _3y1 to the scan electrode Y during the first half period 1st AP of the address period AP. When the data pulse DP1 rising from the ground GND to the positive data voltage Va is synchronously applied to the address electrodes X1 to Xm, between the address electrodes X1 to Xm and the scan electrode Y The address discharge occurs as the wall voltage between the address electrodes X1 to Xm and the scan electrode Y due to the voltage difference and the wall charges formed during the reset period RP is added.

Than that of the first scan voltage (-V _3y1) from the address period (AP) the second half period (2nd AP) scan electrodes (Y) a first scan bias voltage (V _3SC1) small second scan bias voltage (V _3SC2) than during the The second scan pulse SCNP2 falling to the small second scan voltage (-V _3y2 ) and the data pulse DP2 rising from the ground GND to the positive data voltage Va at the address electrodes X1 to Xm. When is applied in synchronization, the wall between the address electrodes (X1 to Xm) and the scan electrode group (Y) due to the wall difference formed during the reset period RP and the voltage difference between the address electrodes (X1 to Xm) and the scan electrode (Y) As the voltage is added, an address discharge occurs.

As such, the level of the second scan bias voltage V _3SC2 during the second half period 2nd AP of the address period AP is higher than the first scan bias voltage V _3SC1 during the first half period 1st AP of the address period AP. By setting it low and _supplying the second scan voltage (-V _3y2 ) lower than the first scan voltage (-V _3y1 ), the address electrodes (X1 to Xm) during the second half period (2nd AP) of the address period AP are provided. And the voltage difference between the scan electrode Y and the scan electrode Y is greater than the voltage difference between the address electrodes X1 to Xm and the scan electrode Y during the first half period 1st AP of the address period AP to generate a stronger address discharge. Therefore, instability of the address discharge during the second half period (2nd AP) of the address period AP due to the wall charge loss in the high temperature environment is prevented in advance.

On the other hand, a bias voltage having a positive sustain voltage (Vs) level is supplied to the sustain electrode Z so as to reduce the voltage difference with the scan electrode Y during the address period AP so as to prevent erroneous discharge from the scan electrode Y. do.

_Preferably , the first scan bias voltage V _3SC1 and the second scan bias voltage V _3SC2 are adjusted to have a positive polarity. As such, by adjusting the first scan bias voltage V _3SC1 and the second scan bias voltage V _3SC2 to the positive polarity, the negative wall charges formed on the scan electrode Y during the set-down period SD are _discharged . It can be used more efficiently in high temperature environment to prepare for address discharge.

The magnitude V _3SC1 + V _3y1 of the first scan pulse SCNP1 applied to the scan electrode Y during the first half period 1st AP of the address period AP is the second half period 2nd AP of the address period AP. It is preferable to adjust the size of the second scan pulse SCNP2 applied to the scan electrode Y to be equal to (V 3 _SC2 + V _3y2 ). As such, the scan driver IC is controlled during the address period AP by adjusting the magnitude of the first scan pulse SCNP1 (V _3SC1 + V _3y1 ) and the _magnitude of the second scan pulse SCNP2 (V _3SC2 + V _3y2 ) to be the same. By keeping the level of the scan pulse voltage at a constant level, the heat generation of the scan driver IC is suppressed, thereby ensuring stable driving.

The minimum voltage (-V _3y1 ) of the first scan pulse SCNP1 is preferably adjusted to be equal to the minimum voltage (-V _3y1 ) of the pulse applied to the scan electrode Y during the reset period RP. By adjusting the first scan to be the same and thus the minimum voltage (-V _3y1) a minimum voltage (-V _3y1) of the pulse applied to the scan electrode (Y) during the reset period (RP) of the pulses (SCNP1), the first scan The manufacturing cost of the plasma display device is reduced by using a common voltage source for supplying the lowest voltage of the pulse applied to the scan electrode Y during the pulse SCNP1 and the reset period RP.

Next, in the sustain period SP, a sustain pulse SUSP rising from the ground GND to the sustain voltage Vs is applied to the scan electrode Y and the sustain electrode Z alternately. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse SUSP is applied as the wall voltage and the sustain pulse SSUS in the cell are added. This will happen.

In this way, the driving process of the plasma display device according to the third exemplary embodiment of the present invention in one subfield is completed.

As described in detail above, the plasma display device according to the third exemplary embodiment of the present invention has a scan bias voltage applied to the scan electrode during the latter half of the address period rather than a scan bias voltage applied to the scan electrode during the first half of the address period. By lowering the level, the driving efficiency is improved by blocking the instability of the address discharge in the latter part of the address period AP due to the wall charge loss in the high temperature environment in advance.

11 is a diagram illustrating a plasma display device according to a fourth embodiment of the present invention.

As shown in FIG. 11, the plasma display device according to the fourth embodiment of the present invention is connected to the address electrodes X1 to Xm, the scan electrodes Y1 to Yn, and the common electrode in the reset period, the address period, and the sustain period. The plasma display panel 1100 expresses an image by applying a predetermined driving pulse to the sustain electrode Z to generate a gas discharge in the discharge space, and the address electrodes X1 to Xm formed on the rear panel (not shown). A data driver 1101 for supplying data, a scan driver 1102 for driving the scan electrodes Y1 to Yn, a sustain driver 1103 for driving the sustain electrode Z, and respective drivers 1101 and 1102. And a timing controller 1104 for controlling the 1103 and a driving voltage generator 1105 for supplying a driving voltage to each of the driving units 1101, 1102, and 1103.

Hereinafter, functions and operations of each component of the plasma display device according to the fourth embodiment of the present invention will be described in detail.

Although not shown, the plasma display panel 1100 is bonded to the front panel (not shown) and the rear panel (not shown) by being spaced apart at regular intervals with a discharge space including an inert gas therebetween. For example, scan electrodes Y1 to Yn and sustain electrode Z are formed in pairs. Meanwhile, address electrodes X1 to Xm are formed on the rear panel to intersect the scan electrodes Y1 to Yn and the sustain electrode Z.

The data driver 1101 is inversely gamma corrected and error spread by an inverse gamma correction circuit, an error diffusion circuit, or the like, and then data mapped to a subfield pattern preset by the subfield mapping circuit is supplied. The data driver 1101 samples and latches data under the control of the timing controller 1104, and then supplies the data to the address electrodes X1 to Xm.

The scan driver 1102 includes a setup waveform that gradually rises to the scan electrodes Y1 to Yn and a setdown waveform that gradually descends to initialize the entire screen during the reset period under the control of the timing controller 1104. Apply the reset waveform simultaneously.

The scan driver 1102 also scans the first period during the first half of the address period to the scan electrodes Y1 to Yn to select the scan line during the address period after the reset waveform is supplied to the scan electrodes Y1 to Yn. The first scan bias voltage V during the second half of the address period and the first scan pulse that falls from the bias voltage V _4SC1 and the first scan bias voltage V _4SC1 to the negative first scan voltage -V _4y1 . a second scan pulse which falls to a second scan voltage (-V _4y2) of negative polarity from the small second scan bias voltage (V _4SC2) than _4SC1) are applied sequentially.

The scan driver 1102 also supplies a sustain pulse to the scan electrodes Y1 to Yn to enable sustain discharge to occur in the selected cell in the address period during the sustain period.

A sustain driving unit 1103 then supplies a bias voltage having at least some period and the address period, the sustain voltage (V _S) level while in the reset period under the control of the timing controller 1104, to the sustain electrode (Z), scanned during the sustain period, It operates to drive 1102 and alternately supplies a sustain pulse having a sustain voltage (V _S) level to the sustain electrode (Z).

The timing controller 1104 receives the vertical / horizontal synchronization signal and generates timing control signals CTRX, CTRY, and CTRZ required for each of the driving units 1101, 1102, and 1103, and generates the timing control signals CTRX, CTRY, and CTRZ. Each of the driving units 1101, 1102, 1103 is controlled by supplying the driving units 1101, 1102, 1103. The timing control signal CTRX applied to the data driver 1101 includes a sampling clock for sampling data, a latch control signal, an energy recovery circuit, and a switch control signal for controlling on / off time of the driving switch element. The timing control signal CTRY applied to the scan driver 1102 includes an energy recovery circuit in the scan driver 1102 and a switch control signal for controlling the on / off time of the driving switch element. The timing control signal CTRZ applied to the sustain driver 1103 includes a switch control signal for controlling the on / off time of the energy recovery circuit and the driving switch element in the sustain driver 1103.

The driving voltage generator 1105 includes a sustain voltage V _S , a setup ramp voltage V _ST , a first scan bias voltage V _4SC1 , a second scan bias voltage V _4SC2 , a data voltage Va, Various driving voltages required by the driving units ₁₁₀₁ , ₁₁₀₂ and ₁₁₀₃ are generated, including the first scan voltage -V _4y1 and the second scan voltage -V _4y2 . These driving voltages may vary depending on the composition of the discharge gas or the structure of the discharge cell.

Hereinafter, the operation principle of the plasma display device according to the fourth embodiment of the present invention will be described in detail with reference to FIG. 12.

12 illustrates a driving waveform of the plasma display device according to the fourth embodiment of the present invention.

As shown in FIG. 12, in the plasma display device according to the fourth exemplary embodiment, a reset period RP for initializing all cells, an address period AP for selecting a cell to be discharged, and a discharge of a selected cell are shown. It is driven by being divided into the sustain period SP for maintaining.

Hereinafter, the voltage applied to each period and its function will be described in detail.

First, in the reset period RP, the setup ramp pulse PR of the positive slope is simultaneously applied to all the scan electrodes Y ₁ to Y _{n in the} setup period SU. The setup ramp pulse PR is an example of a setup waveform and may adopt various waveforms in a rising shape. This setup ramp pulse PR causes a weak dark discharge in the discharge cells of the entire screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y.

Subsequently, in the set down period SD, all of the scan electrodes Y ₁ to Y _n are simultaneously applied with a set down ramp pulse NR having a negative slope, while a positive sustain voltage Vs is applied to the sustain electrode Z. When a bias voltage having a level is applied, the positive wall charge of the address electrode X is maintained but the positive wall charge of the sustain electrode Z is erased by a discharge between the sustain electrode Z and the scan electrode Y. At the same time, the sustain electrode Z and the scan electrode Y divide a large amount of the negative charge accumulated in the scan electrode Y.

By this set down discharge, the wall charges such that the address discharge can stably occur remain uniformly in the cells.

The set down ramp pulse NR is an example of a set down waveform and may adopt various waveforms in a descending form.

Next, the first scan pulse SCNP1 falls from the first scan bias voltage V _4SC1 to the first scan voltage −V _4y1 to the scan electrode Y during the first half period 1st AP of the address period AP. When the data pulse DP1 rising from the ground GND to the positive data voltage Va is synchronously applied to the address electrodes X1 to Xm, between the address electrodes X1 to Xm and the scan electrode Y The address discharge occurs as the wall voltage between the address electrodes X1 to Xm and the scan electrode Y due to the voltage difference and the wall charges formed during the reset period RP is added.

Than that of the first scan voltage (-V _4y1) from the address period (AP) the second half period (2nd AP) scan electrodes (Y) a first scan bias voltage (V _4SC1) larger second scan bias voltage (V _4SC2) than during the The second scan pulse SCNP2 falling to the large second scan voltage (-V _4y2 ) and the data pulse DP2 rising from the ground GND to the positive data voltage Va to the address electrodes X1 to Xm. When is applied in synchronization, the wall between the address electrodes (X1 to Xm) and the scan electrode group (Y) due to the wall difference formed during the reset period RP and the voltage difference between the address electrodes (X1 to Xm) and the scan electrode (Y) As the voltage is added, an address discharge occurs.

In this manner, the second scan bias voltage V _4SC2 during the second half period 2nd AP of the address period AP is higher than the first scan bias voltage V _4SC1 during the first half period 1st AP of the address period AP. By supplying with a high setting, the negative charges formed on the scan electrode Y through the reset period RP are kept stronger by using electrostatic attraction, and thus an address period due to wall charge loss in a high temperature environment. (AP) The instability of the address discharge in the second half is blocked in advance.

On the other hand, a bias voltage having a positive sustain voltage (Vs) level is supplied to the sustain electrode Z so as to reduce the voltage difference with the scan electrode Y during the address period AP so as to prevent erroneous discharge from the scan electrode Y. do.

_Preferably , the first scan bias voltage V _4SC1 and the second scan bias voltage V _4SC2 are adjusted to have a positive polarity. As such, by _adjusting the first scan bias voltage V _4SC1 and the second scan bias voltage V _4SC2 to the positive polarity, the electrostatic attraction force is applied to the negative wall charges formed in the scan electrode Y during the set-down period SD. It can be used to maintain more efficient in high temperature environment and to prepare for address discharge.

The magnitude V _4SC1 + V _4y1 of the first scan pulse SCNP1 applied to the scan electrode Y during the first half period 1st AP of the address period AP is the second half period 2nd AP of the address period AP. It is preferable to adjust the size of the second scan pulse SCNP2 applied to the scan electrode Y to be equal to (V _4SC2 + V _4y2 ). Thus, by adjusting the magnitude of the first scan pulse SCNP1 (V _4SC1 + V _4y1 ) and the _magnitude of the second scan pulse SCNP2 (V _4SC2 + V _4y2 ) to the scan driver IC during the address period AP. By keeping the level of the scan pulse voltage applied constant, heat generation of the scan driver IC is suppressed, thereby ensuring stable driving.

The minimum voltage (-V _4y1 ) of the first scan pulse SCNP1 is preferably adjusted to be equal to the minimum voltage (-V _4y1 ) of the pulse applied to the scan electrode Y during the reset period RP. By adjusting the first scan to be the same and thus the minimum voltage (-V _4y1) a minimum voltage (-V _4y1) of the pulse applied to the scan electrode (Y) during the reset period (RP) of the pulses (SCNP1), the first scan The manufacturing cost of the plasma display device can be reduced by using a common voltage source for supplying the lowest voltage of the pulse applied to the scan electrode Y during the pulse SCNP1 and the reset period RP.

Next, in the sustain period SP, a sustain pulse SUSP rising from the ground GND to the sustain voltage Vs is applied to the scan electrode Y and the sustain electrode Z alternately. The cell selected by the address discharge has a sustain discharge, that is, a display discharge between the scan electrode Y and the sustain electrode Z whenever the sustain pulse SUSP is applied as the wall voltage and the sustain pulse SSUS in the cell are added. This will happen.

In this way, the driving process of the plasma display device according to the fourth embodiment of the present invention in one subfield is completed.

As described in detail above, the plasma display device according to the fourth embodiment of the present invention has a scan bias voltage applied to the scan electrode during the latter half of the address period rather than a scan bias voltage applied to the scan electrode during the first half of the address period. By raising the level, the driving efficiency is improved by blocking the instability of the address discharge in the latter part of the address period AP due to the wall charge loss in the high temperature environment in advance.

Since the driving method of the plasma display device according to the first to fourth embodiments of the present invention is driven under the same principle as the plasma display device according to the first to fourth embodiments of the present invention described above in detail, The description of the plasma display device according to the first to fourth embodiments is replaced.

As such, the technical configuration of the present invention described above can be understood by those skilled in the art that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention.

Therefore, the exemplary embodiments described above are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the following claims rather than the foregoing detailed description, and the meaning and scope of the claims are as follows. And all changes or modifications derived from the equivalent concept should be construed as being included in the scope of the present invention.

As described in detail above, the present invention provides a plasma display device and a method of driving the same, which prevent a high temperature misdischarge and ensure stable driving and reduce manufacturing costs.

Claims (36)

A plasma display panel including scan electrodes divided into upper and lower scan electrode groups in a scan order; An upper scan driver configured to apply a first scan bias voltage to the upper scan electrode group during an address period; And And a lower scan driver configured to apply a second scan bias voltage smaller than the first scan bias voltage to the lower scan electrode group during an address period. The method of claim 1, And the first scan bias voltage and the second scan bias voltage are positive polarities. The method of claim 2, And the lowest voltage of the pulses applied to the upper and lower scan electrode groups during the reset period is the same. The method of claim 3, wherein During the address period The magnitude of the first scan pulse applied to the upper scan electrode group is the same as the magnitude of the second scan pulse applied to the lower scan electrode group. The method of claim 4, wherein And the lowest voltage of the first scan pulse is equal to the lowest voltage of a pulse applied to the upper scan electrode group during the reset period. A plasma display panel including scan electrodes divided into upper and lower scan electrode groups in a scan order; An upper scan driver configured to apply a first scan bias voltage to the upper scan electrode group during an address period; And And a lower scan driver configured to apply a second scan bias voltage greater than the first scan bias voltage to the lower scan electrode group during an address period. The method of claim 6, And the first scan bias voltage and the second scan bias voltage are positive polarities. The method of claim 7, wherein And the lowest voltage of the pulses applied to the upper and lower scan electrode groups during the reset period is the same. The method of claim 8, During the address period The magnitude of the first scan pulse applied to the upper scan electrode group is the same as the magnitude of the second scan pulse applied to the lower scan electrode group. The method of claim 9, And the lowest voltage of the first scan pulse is equal to the lowest voltage of a pulse applied to the upper scan electrode group during the reset period. A plasma display panel including a scan electrode; And a scan driver configured to apply a first scan bias voltage to the scan electrode during the first half of the address period and then apply a second scan bias voltage less than the first scan bias voltage during the second half of the address period. Plasma Display. The method of claim 11, And the first scan bias voltage and the second scan bias voltage are positive polarities. The method of claim 12, And the magnitude of the first scan pulse applied to the scan electrode during the first half period of the address period is the same as the magnitude of the second scan pulse applied during the second half period of the address period. The method of claim 13, And the lowest voltage of the first scan pulse is equal to the lowest voltage of a pulse applied to the scan electrode during the reset period. A plasma display panel including a scan electrode; And a scan driver configured to apply a first scan bias voltage to the scan electrode during the first half of the address period and then apply a second scan bias voltage greater than the first scan bias voltage during the second half of the address period. Plasma Display. The method of claim 15, And the first scan bias voltage and the second scan bias voltage are positive polarities. The method of claim 16, And the magnitude of the first scan pulse applied to the scan electrode during the first half period of the address period is the same as the magnitude of the second scan pulse applied during the second half period of the address period. The method of claim 17, And the lowest voltage of the first scan pulse is equal to the lowest voltage of a pulse applied to the scan electrode during the reset period. A driving method of a plasma display device, wherein a plurality of subfields are divided into a reset period, an address period, and a sustain period, respectively, and display an image in units of frames in which the subfields are combined. During the address period Applying a first scan bias voltage to the upper scan electrode group of the plasma display panel including scan electrodes divided into upper and lower scan electrode groups in a scan order; And And applying a second scan bias voltage smaller than the first scan bias voltage to the lower scan electrode group. The method of claim 19, And the first scan bias voltage and the second scan bias voltage are positive polarities. The method of claim 20, And the lowest voltage of a pulse applied to the upper and lower scan electrode groups during the reset period is the same. The method of claim 21, During the address period The magnitude of the first scan pulse applied to the upper scan electrode group is the same as the magnitude of the second scan pulse applied to the lower scan electrode group. The method of claim 22, And the lowest voltage of the first scan pulse is equal to the lowest voltage of a pulse applied to the upper scan electrode group during the reset period. A driving method of a plasma display device, wherein a plurality of subfields are divided into a reset period, an address period, and a sustain period, respectively, and display an image in units of frames in which the subfields are combined. During the address period Applying a first scan bias voltage to the upper scan electrode group of the plasma display panel including scan electrodes divided into upper and lower scan electrode groups in a scan order; And And applying a second scan bias voltage greater than the first scan bias voltage to the lower scan electrode group. The method of claim 24, And the first scan bias voltage and the second scan bias voltage are positive polarities. The method of claim 25, And the lowest voltage of a pulse applied to the upper and lower scan electrode groups during the reset period is the same. The method of claim 26, During the address period The magnitude of the first scan pulse applied to the upper scan electrode group is the same as the magnitude of the second scan pulse applied to the lower scan electrode group. The method of claim 27, And the lowest voltage of the first scan pulse is equal to the lowest voltage of a pulse applied to the upper scan electrode group during the reset period. A driving method of a plasma display device, wherein a plurality of subfields are divided into a reset period, an address period, and a sustain period, respectively, and display an image in units of frames in which the subfields are combined. Applying a first scan bias voltage to a scan electrode during the first half of said address period; And And applying a second scan bias voltage that is less than the first scan bias voltage during the latter half of the address period. The method of claim 29, And the first scan bias voltage and the second scan bias voltage are positive polarities. The method of claim 30, And the magnitude of the first scan pulse applied to the scan electrode during the first half period of the address period is the same as the magnitude of the second scan pulse applied during the second half period of the address period. The method of claim 31, wherein And the lowest voltage of the first scan pulse is equal to the lowest voltage of a pulse applied to the scan electrode during the reset period. A driving method of a plasma display device, wherein a plurality of subfields are divided into a reset period, an address period, and a sustain period, respectively, and display an image in units of frames in which the subfields are combined. Applying a first scan bias voltage to a scan electrode during the first half of said address period; And And applying a second scan bias voltage greater than the first scan bias voltage during the latter half of the address period. The method of claim 33, wherein And the first scan bias voltage and the second scan bias voltage are positive polarities. The method of claim 34, wherein And the magnitude of the first scan pulse applied to the scan electrode during the first half period of the address period is the same as the magnitude of the second scan pulse applied during the second half period of the address period. 36. The method of claim 35 wherein And the lowest voltage of the first scan pulse is equal to the lowest voltage of a pulse applied to the scan electrode during the reset period.

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