KR20070028095A - Light emitting diode having low resistance - Google Patents

Abstract

A low resistance light emitting diode is provided to reduce contact resistance and power consumption of a light emitting diode by employing an InxAlyGazN(0<x<=1, 0<=y<=1, 0<=z<1) layer between a P-GaN layer and an ohmic contact layer. An N-GaN layer(11) is formed on a substrate(10). A part of the N-GaN layer is mesa-etched. An active layer(12) is formed on a non-etched upper surface of the N-GaN layer. A P-GaN layer(13) is formed on the active layer. An InxAlyGazN(0<x<=1, 0<=y<=1, 0<=z<1) layer(14) is formed on the P-GaN layer. An ohmic contact layer(15) is formed on the InxAlyGazNn layer. An N-electrode(16) is formed on an etched supper surface of the N-GaN layer. A P-electrode(17) is formed on the ohmic contact layer. An un-doped U-GaN layer is formed between the substrate and the N-GaN layer.

Description

Light Emitting Diode Having Low Resistance

1 is a cross-sectional view showing a schematic configuration of a light emitting diode according to the prior art;

2A to 2C are cross-sectional views illustrating a manufacturing procedure of an embodiment of a low resistance light emitting diode according to the present invention;

3A to 3D are cross-sectional views illustrating a manufacturing procedure of another embodiment of a low resistance light emitting diode according to the present invention;

4A to 4C are cross-sectional views illustrating a manufacturing procedure of still another embodiment of a low resistance light emitting diode according to the present invention.

*** Explanation of the Major Symbols in the Drawings ***

10 substrate 11 N-GaN layer

12 active layer 13 P-GaN layer

14: In _X Al _Y Ga _Z N (0 <x≤1, 0≤y≤1, 0≤z <1) layer

15, 31a, 31b: ohmic contact layer 16: N-electrode

17: P-electrode 18: U-GaN layer

19: metal support layer 30: submount substrate

32: base substrate 33: solder

The present invention relates to a low-resistance light-emitting diode, and more particularly, by forming an In _X Al _Y Ga _Z N (0 <x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z <1) layer on the P-GaN layer Provided is a low resistance light emitting diode that reduces power consumption of the light emitting diode by reducing contact resistance with the ohmic contact layer.

A light emitting diode is a light emitting device using a phenomenon that emits light when electrons are transitioned, the light emission of the light emitting diode occurs in the process of recombination of electrons in the semiconductor conduction band (hole) of the valence band (hole) .

The light emission wavelength of the light emitting diode depends on the type of impurities added to the semiconductor. For example, in the case of gallium phosphide, the light emission involving zinc and oxygen atoms is red (wavelength 700 nm), and the light emission involving nitrogen atoms is green (wavelength 550 nm).

Light emitting diodes are smaller than conventional light sources, have a long lifespan, and have low power and good efficiency because electrical energy is directly converted into light energy. In addition, it is used for display devices of automotive instrumentation, display lamps for various electronic devices such as optical communication light sources, numeric display devices, and card readers for calculators.

In recent years, light emitting diodes (LEDs) and laser diodes (LDs) using gallium nitride have applications such as large scale full color flat panel display devices, traffic lights, indoor lighting and high density light sources, high resolution output systems, and optical communications. As a result, many researchers are attracting attention, and attempts for commercialization are ongoing.

1 is a cross-sectional view of a general light emitting diode, in which an N-GaN layer 111, an active layer 112, and a P-GaN layer 113 are sequentially formed on a sapphire substrate 110; Mesa is etched from the P-GaN layer 113 to the N-GaN layer 111; An N-electrode 115 is formed on the mesa-etched N-GaN layer 111; The P-electrode 114 is formed on the P-GaN layer 113.

In this way, when the chip is loaded with a positive load on the P-electrode 114 and a negative load on the N-electrode 115, holes are formed from the P-GaN layer 113 and the N-GaN layer 111, respectively. And electrons gather in the active layer 112 and recombine to emit light in the active layer 112.

Magnesium or the like is used as a dopant for the P doping of the P-GaN layer, but the magnesium and the like do not function as a P dopant by combining with hydrogen and act as a defect. Therefore, in general, a heat treatment process is performed to remove defects of magnesium and hydrogen. However, even though the heat treatment process is performed, most of the dopants are present in combination with hydrogen, thereby increasing the resistance of the P-GaN layer and the contact resistance with the ohmic contact layer. It becomes a factor that becomes large.

Therefore, there is a need to develop a low-resistance light emitting diode that can solve this problem and reduce power consumption.

The present invention is to solve the above problems, by forming an In _X Al _Y Ga _Z N (0 <x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z <1) layer on the P-GaN layer ohmic contact layer It is to provide a low-resistance light emitting diode that reduces the contact resistance of the light emitting diode to reduce the power consumption.

The present invention provides an N-GaN layer formed on a substrate and partially mesa-etched, an active layer formed on an unetched upper surface of the N-GaN layer; A P-GaN layer formed on the active layer; An In _X Al _Y Ga _Z N (0 <x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z <1) layer formed on the P-GaN layer, an ohmic contact layer formed on the In _X Al _Y Ga _Z N layer, and A low resistance light emitting diode comprising an N-electrode formed on an etched top surface of the N-GaN layer and a P-electrode formed on an ohmic contact layer is provided.

In addition, an ohmic contact layer formed on the submount substrate, an In _X Al _Y Ga _Z N (0 <x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z <1) layer formed on the ohmic contact layer, and the In _X Al _Y layer It provides a low-resistance light emitting diode comprising a P-GaN layer formed on the Ga _Z N layer, an active layer formed on the P-GaN layer, an N-GaN layer formed on the active layer and an N-electrode formed on the N-GaN layer. do.

In addition, an ohmic contact layer formed on the metal support layer, an In _X Al _Y Ga _Z N (0 <x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z <1) layer formed on the ohmic contact layer, and the In _X Al _Y Ga _Z N P-GaN layer formed on the layer, and provides a low resistance light emitting diode comprising: a N- electrode formed on the N-GaN layer and the N-GaN layer formed of an active layer formed on the P-GaN layer, on the active layer .

Hereinafter, the technical features of the present invention will be described in detail through the manufacturing procedure of the low resistance light emitting diode according to the present invention. The invention can be better understood by the examples, the following examples are for illustrative purposes of the invention and are not intended to limit the scope of protection defined by the appended claims.

2A to 2C are cross-sectional views illustrating a fabrication procedure of an embodiment of a low resistance light emitting diode according to the present invention. The N-GaN layer 11, the active layer 12, the P-GaN layer 13, Sequentially forming an In _X Al _Y Ga _Z N (0 <x≤1, 0≤y≤1, 0≤z <1) layer 14 and an ohmic contact layer 15 to form a light emitting structure (FIG. 2a) mesa-etching the light emitting structure to expose a portion of the upper surface of the N-GaN layer (FIG. 2b); placing an N-electrode 16 on the upper surface of the exposed N-GaN layer and a P on the P-GaN layer. Forming an electrode 17 (FIG. 2C).

First, an N-GaN layer 11, an active layer 12, a P-GaN layer 13, In _X Al _Y Ga _Z N (0 <x≤1, 0≤y≤1, 0≤ on the substrate 10). The z <1) layer 14 and the ohmic contact layer 15 are sequentially stacked (FIG. 2A). The substrate may be any one of a sapphire substrate, a silicon (Si) substrate, a zinc oxide (ZnO) substrate, or a nitride semiconductor substrate, or a template in which at least one of GaN, InGaN, AlGaN, and AlInGaN is stacked on the substrate. Substrates can be used.

The method of forming the N-GaN layer, the active layer, the P-GaN layer, and the In _X Al _Y Ga _Z N layer may be used without limitation as long as it is capable of depositing a thin GaN layer. Is appropriate.

In order to form the N-GaN layer 11, doping with an appropriate dopant is performed during the formation of the GaN layer. As the dopant for N doping, silicon, germanium, selenium, tellurium, carbon, and the like may be used. When silicon is used, the doping concentration is generally about 10 ¹⁷ / cm ³ . The N-GaN layer may be formed in a double layer structure of N ⁺ and N ⁻ by varying the doping concentration.

In the present invention, an undoped U-GaN layer (not shown) may be first formed on a substrate, and then an N-GaN layer is formed thereon. This is to prevent the occurrence of defects due to the rapid change in the lattice period when the N-GaN layer is formed on the substrate to reduce the thin film characteristics.

The active layer 12 is a part emitting light in the light emitting diode. It can be represented by the general formula of Al _X Ga _Y In _{1 -XY} N ( _0≤x <1, 0 <y <1), binary system such as aluminum nitride, gallium nitride and indium nitride, gallium nitride-indium and gallium nitride Ternary systems such as aluminum. Group III elements may be partially substituted with boron, thallium, and the like, and nitrogen may be partially substituted with phosphorus, arsenic, antimony, and the like.

The active layer can adjust the wavelength of light emitted by changing the component composition. For example, about 22% of indium is included to emit blue light. In addition, about 40% of indium is included to emit green light.

As the dopant of the P-GaN layer 13, magnesium, zinc, beryllium, calcium, strontium, barium, or the like may be used. Like the N-GaN layer, the P-GaN layer can be formed in a two ^- layer structure of P ⁺ and P ⁻ .

The present invention is characterized in that an In _X Al _Y Ga _Z N (0 <x≤1, 0≤y≤1, 0≤z <1) layer 14 is formed between the P-GaN layer and the ohmic contact layer. Magnesium, which is used as a dopant for the P doping of the P-GaN layer, is mostly bonded with hydrogen and does not function as a P dopant, which acts as a defect, causing an increase in contact resistance. The contact resistance refers to a resistance higher than other parts generated in the contact surface when the current passing through the contact surface of the objects in contact with each other is an important cause of power loss. The In _X Al _Y Ga _Z N layer has a smaller band gap than the P-GaN layer. As a result, when the In _X Al _Y Ga _Z N layer is connected to the ohmic contact layer, the concentration of local current is reduced and the overall contact resistance is reduced when the P-GaN layer is connected to the ohmic contact layer. The thickness of the In _X Al _Y Ga _Z N layer is preferably smaller than 50 nm, and may be formed in various embodiments, as described below.

The band gap of the In _X Al _Y Ga _Z N layer may be formed to be smaller than the band gap of the P-GaN layer. Preferably, the Al composition may be reduced stepwise from an interface in contact with the P-GaN layer.

The In _X Al _Y Ga _Z N layer may be formed by N doping. The dopant used for N doping, unlike the dopant used for P doping, does not cause a decrease in carrier concentration due to bonding with hydrogen. Thus, the contact resistance is further reduced.

The N doping may be N delta doped such that a doped In _X Al _Y Ga _Z N layer and an undoped In _X Al _Y Ga _Z N layer are alternately stacked.

An N ⁺ doped N ⁺ -GaN layer may be formed between the In _X Al _Y Ga _Z N layer and the P-GaN layer.

In addition, the In _X Al _Y Ga _Z N layer may be formed of a super lattice layer of In _X Al _Y Ga _Z N and N ⁺ -GaN. The superlattice structure refers to a structure in which the spatial variation of the semiconductor band gap is one-dimensional or two-dimensionally larger than the lattice constant of the constituent material.

The superlattice structure is similar in structure to a multi-quantum well, but has a distinguishable characteristic from a multi-quantum well. If multiple quantum wells have the characteristics of an array-like structure of single quantum wells almost neglecting the interaction between wells, the superlattice structure is a structure in which the tunneling effect between the wells is important. It mainly determines the role of superlattice structure in semiconductor devices. The tunneling effect refers to a phenomenon in which electrons or holes that are separated and bound to adjacent wells have little interaction with each other, and these particles easily move to adjacent wells as the barrier becomes thinner.

Factors that can affect this tunneling effect in the superlattice structure affect not only the thickness of the barrier but also the thickness of the well and the difference in the composition ratio of the barrier. The Kronig-Penney model is a model that can physically explain the one-dimensional characteristics of these structures. According to the model, the superlattice structure has a quantum confinement effect of wells and the interaction between wells and holes They form a new band called subband or miniband, which is a low-dimensional feature of the superlattice structure.

In consideration of maximizing the tunneling effect of the superlattice layer, it is preferable to configure the short period superlattice having a period of 5 nm or less. The short-period superlattice layer forms an indirect band to increase the tunneling effect.

In this embodiment, the super lattice structure was formed by alternately stacking In _X Al _Y Ga _Z N and N-GaN, and in order to lower the contact resistance, the GaN layer was N-doped (silicon injection) concentration of 1 x 10 ¹⁸ /. N ⁺ doped to at least cm ³ .

The ohmic contact layer 15 is preferably a transparent conducting oxide. As the transparent conductive oxide, indium tin oxide (ITO) or indium zinc oxide (IZO) may be used. Since the transparent conductive oxide may serve as an ohmic contact layer, there is an advantage in that the ohmic contact layer does not need to be formed separately, and light transmission efficiency may be increased because the light transmittance is 90% or more.

When the low resistance light emitting diode according to the present invention is to be applied in the form of a flip chip, the light emitting structure may further include a reflective layer (not shown) between the ohmic contact layer 15 and the P-electrode 17. The reflective layer is to prevent the light amount of the light emitting diode from decreasing by attenuating the light emitted from the active layer.

As the reflective layer, metals such as aluminum, zinc, gold, platinum, titanium, palladium, germanium, copper, nickel, and strontium, and oxides or nitrides such as silicon oxide, silicon nitride, aluminum oxide, magnesium oxide, and titanium oxide may be used.

Instead of forming the reflective layer, the ohmic contact layer may be formed of a metal thin film of nickel (Ni) / gold (Au). Since the nickel-based metal thin film has a high reflectance, there is an advantage that a certain reflecting effect can be obtained without forming a separate reflecting film.

The light emitting structure may further include an undoped U-GaN layer (not shown) between the substrate and the N-GaN layer. The formation of the U-GaN layer is to prevent the deterioration of the physical properties of the GaN layer due to the difference in lattice period between the substrate and the GaN layer formed thereon.

In forming the light emitting structure, the P-GaN layer may be activated. Preferably, the light emitting structure is formed and then activated. The activation step is to discontinue the bonding of magnesium and hydrogen in order to prevent the dopant of the P-GaN layer, such as magnesium do not combine with hydrogen to act as a defect. More specifically, heat treatment is performed at 600 ° C. for about 20 minutes, and after forming a P-GaN layer, an In _X Al _Y Ga _Z N layer, an ohmic contact layer, or a reflective layer, depending on the top layer of the light emitting structure.

Next, the light emitting structure is mesa-etched to expose a portion of the N-GaN layer (FIG. 2B). The mesa etching step is to form a surface on which the N-electrode is formed. Mesa etching is an optional etch that projects from above adjacent areas leaving only a flat portion of the original surface and is used to prevent the electrically active material from expanding into the mesa area. Mesa etching is well known, detailed description thereof will be omitted.

Next, an N-electrode 16 is formed on the exposed N-GaN layer and a P-electrode 17 is formed on the P-GaN layer (FIG. 2C). The electrode is formed by depositing a resistive metal.

Hereinafter, the manufacturing procedure when the present invention is configured with a vertical light emitting diode will be described. Vertical light emitting diodes have a higher number of light emitting diodes produced on the same wafer than horizontal light emitting diodes, and thus have high yields and efficient current flow.

3A to 3D are cross-sectional views illustrating a fabrication procedure of another embodiment of a low resistance light emitting diode according to the present invention, wherein a U-GaN layer 18, an N-GaN layer 11, an active layer 12, P-GaN layer 13, In _X Al _Y Ga _Z N (0 <x≤1, 0≤y≤1, 0≤z <1) layer 14 and ohmic contact layer 15 are sequentially stacked Forming a light emitting structure (FIG. 3A), bonding a submount substrate 30 on the light emitting structure (FIG. 3B), and removing the substrate 10 and the U-GaN layer 18 (FIG. 3A). 3c), forming an N-electrode 17 on the surface of the N-GaN layer from which the U-GaN layer is removed (FIG. 3D).

First, the U-GaN layer 18, the N-GaN layer 11, the active layer 12, the P-GaN layer 13, In _X Al _Y Ga _Z N (0 <x≤1, A light emitting structure is formed by sequentially laminating layers 14 and ohmic contact layers 15 of 0 ≦ y ≦ 1 and 0 ≦ z <1 (FIG. 3A). Process of forming U-GaN layer, N-GaN layer, active layer, P-GaN layer, In _X Al _Y Ga _Z N (0 <x≤1, 0≤y≤1, 0≤z <1) layer on the substrate Is the same as the method of the above-described embodiment.

Next, the submount substrate 30 is bonded on the light emitting structure (FIG. 3B). In order to bond the submount substrate, first and second ohmic contact metal layers 31a and 31b are formed on upper and lower portions of the submount base substrate 32, and the solder 33 for light emitting diode chip attachment is formed. To form a submount substrate, and bond the ohmic contact layer of the manufactured light emitting structure to the solder of the manufactured submount substrate.

Next, the substrate 10 and the U-GaN layer 18 are removed (FIG. 3C). In this embodiment, a laser liftoff method is used to remove the substrate. More specifically, the UV-laser of 245 ~ 305nm is irradiated through the substrate. The irradiated laser penetrates the substrate and is absorbed at the interface between the substrate and the GaN layer, so that GaN is separated into Ga and N ₂ , and N ₂ escapes to the outside in a gaseous state, leaving only Ga at the interface. Since Ga has a melting point of about 30 ° C, it is easily melted by heat to remove the substrate.

Since the U-GaN layer in contact with the substrate is damaged by a laser, the N-GaN layer is exposed by removing the U-GaN layer to form an electrode. First, Ga formed in the process of removing the substrate is removed using a dilute hydrochloric acid solution to facilitate the subsequent etching process, and then the U-GaN layer is removed using dry etching. After removing the U-GaN layer, heat treatment is performed to recover crystals damaged during the etching process.

Next, an N-electrode 16 is formed on the surface of the N-GaN layer from which the U-GaN layer is removed (FIG. 3D). Preferably, it is preferable to form a cross shape so that the current is evenly distributed.

When the light emitting diode according to the present embodiment is to be used in the form of a flip chip, the light emitting structure may further include a reflective layer (not shown) between the ohmic contact layer 15 and the submount substrate 30.

4A to 4C are cross-sectional views illustrating a fabrication procedure of another embodiment of the low-resistance light emitting diode according to the present invention, in which a U-GaN layer 18, an N-GaN layer 11, and an active layer 12 are disposed on a substrate 10. , P-GaN layer 13, In _X Al _Y Ga _Z N (0 <x≤1, 0≤y≤1, 0≤z <1) layer 14, ohmic contact layer 15, metal support layer ( 19) sequentially stacking to form a light emitting structure (FIG. 4A), removing the substrate 10 and the U-GaN layer 18 (FIG. 4B), and removing the U-GaN layer N- And forming an N-electrode 16 on the surface of the GaN layer (FIG. 4C).

First, the U-GaN layer 18, the N-GaN layer 11, the active layer 12, the P-GaN layer 13, In _X Al _Y Ga _Z N (0 <x≤1, 0 ≦ y ≦ 1, 0 ≦ z <1) layer 14, ohmic contact layer 15, and metal support layer 19 are sequentially stacked to form a light emitting structure. U-GaN layer, N-GaN layer, active layer, P-GaN layer, In _X Al _Y Ga _Z N (0 <x≤1, 0≤y≤1, 0≤z <1) layer, ohmic contact layer on the substrate The process of forming is the same as the method of the above-described embodiment.

Although the metal support layer may be formed in various ways, in this embodiment, the upper part of the light emitting structure is immersed in a plating solution to form the metal support layer by an electroplating method.

Since the electroplating method does not require a high temperature process, it is possible to prevent stress generation between materials having different thermal expansion coefficients and lattice constants caused by the high temperature process, and has a good adhesion to the front surface regardless of the light emitting structure of the light emitting diode. Is formed. The plating liquid may use a plating liquid used in a general plating method.

The metal support layer may serve as a P-electrode. Therefore, it has to be excellent in electrical conductivity and able to dissipate heat that can be generated during device operation. Therefore, it is better to use metal with high thermal conductivity. However, due to process problems such as warpage of wafers, light metals are alloyed to provide mechanical strength. It is preferably configured to satisfy the thermal conductivity while having.

The soft metal is preferably selected from at least one of gold (Au), copper (Cu), silver (Ag), and aluminum (Al), which are metals having high thermal conductivity. The hard metal that can be alloyed with the soft metal has a crystal lattice constant similar to the crystal structure of the soft metal and similar to the crystal lattice constant of the soft metal to minimize the generation of internal stress during alloying or interface formation. In order to improve the mechanical strength and brittleness, the Young's modulus is higher than the Young's modulus, and the metal is higher than the melting point of the soft metal so as to withstand the heat treatment for device fabrication after forming the metal support film. desirable. As a metal approximating the above conditions, nickel (Ni), cobalt (Co), platinum (Pt) or palladium (Pd) may be selected.

Next, the substrate 10 and the U-GaN layer 18 are removed, and an N-electrode 16 is formed on the surface of the N-GaN layer from which the U-GaN layer is removed (FIGS. 4B and 4C).

When the light emitting diode according to the present embodiment is to be used in the form of a flip chip, the light emitting structure may further include a reflective layer (not shown) between the ohmic contact layer and the metal support layer.

When manufacturing a light emitting diode using the metal support layer as described above, it is possible not only to be electrically stable and efficient heat dissipation, but also to prevent the production yield from being lowered due to the mismatch of lattice defects with the substrate in a later step.

The present invention includes an In _X Al _Y Ga _Z N (0 <x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z <1) layer between the P-GaN layer and the ohmic contact layer to reduce the contact resistance to the light emitting diode Can reduce power consumption.

In addition, by using a transparent conductive oxide as an ohmic contact layer, it is possible to implement a high efficiency light emitting diode by increasing light extraction efficiency.

In addition, in forming the N-electrode, the current can be evenly distributed by forming a cross shape, thereby increasing the luminous efficiency.

In addition, by forming the In _X Al _Y Ga _Z N layer as a superlattice layer, the light emission efficiency is increased by the tunneling effect.

In addition, by providing a reflective layer, not only can be applied to a flip chip type light emitting diode, but also the light emitting efficiency is high.

Claims (18)

An N-GaN layer formed on the substrate and partially mesa-etched; An active layer formed on an unetched upper surface of the N-GaN layer; A P-GaN layer formed on the active layer; An In _X Al _Y Ga _Z N (0 <x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z <1) layer formed on the P-GaN layer; An ohmic contact layer formed on the In _X Al _Y Ga _Z N layer; And A low resistance light emitting diode comprising an N-electrode formed on an etched top surface of the N-GaN layer and a P-electrode formed on an ohmic contact layer. The method of claim 1, And a non-doped U-GaN layer between the substrate and the N-GaN layer. The method of claim 1, A low resistance light emitting diode, wherein a reflective layer is further interposed between the ohmic contact layer and the P-electrode. The method of claim 1, The substrate may be any one of a sapphire substrate, a silicon (Si) substrate, a zinc oxide (ZnO) substrate, or a nitride semiconductor substrate, or a template in which at least one of GaN, InGaN, AlGaN, and AlInGaN is stacked on the substrate. A low resistance light emitting diode, characterized in that the substrate. An ohmic contact layer formed on the submount substrate; An In _X Al _Y Ga _Z N (0 <x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z <1) layer formed on the ohmic contact layer; A P-GaN layer formed on the In _X Al _Y Ga _Z N layer; An active layer formed on the P-GaN layer; An N-GaN layer formed on the active layer; And A low resistance light emitting diode comprising an N-electrode formed on the N-GaN layer. The method of claim 5, A low resistance light emitting diode, wherein a reflection layer is further interposed between the submount substrate and the ohmic contact layer. An ohmic contact layer formed on the metal support layer; An In _X Al _Y Ga _Z N (0 <x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z <1) layer formed on the ohmic contact layer; A P-GaN layer formed on the In _X Al _Y Ga _Z N layer; An active layer formed on the P-GaN layer; An N-GaN layer formed on the active layer; And A low resistance light emitting diode comprising an N-electrode formed on the N-GaN layer. The method of claim 7, wherein A low resistance light emitting diode, wherein a reflective layer is further interposed between the metal support layer and the ohmic contact layer. The method according to any one of claims 1 to 8, The ohmic contact layer is a low resistance light emitting diode, characterized in that made of a transparent conductive oxide. The method according to any one of claims 1 to 8, The ohmic contact layer is a low resistance light emitting diode, characterized in that consisting of Ni / Au (nickel / gold) thin film. The method according to any one of claims 1 to 8, The In _X Al _Y Ga _Z N (0 <x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z <1) layer is formed of a low resistance light emitting diode, characterized in that the band gap is smaller than the P-GaN layer. The method according to any one of claims 1 to 8, The In _X Al _Y Ga _Z N (0 <x≤1, 0≤y≤1, 0≤z <1) layer is formed by a stepwise decrease in Al composition from an interface in contact with the P-GaN layer. Resistive light emitting diode. The method according to any one of claims 1 to 8, Low-resistance light emission characterized in that an N ⁺ -GaN layer is further formed between the In _X Al _Y Ga _Z N (0 <x ≤ 1, 0 ≤ y ≤ 1, 0 ≤ z <1) and the P-GaN layer diode. The method according to any one of claims 1 to 8, The In _X Al _Y Ga _Z N (0 <x≤1, 0≤y≤1, 0≤z <1) layer is formed of a superlattice layer of In _X Al _Y Ga _Z N and N ⁺ -GaN Low resistance light emitting diode made. The method of claim 13, The superlattice layer is a low resistance light emitting diode, characterized in that formed of a short-period superlattice layer having a period of less than 5nm. The method according to any one of claims 1 to 8, Wherein the In _X Al _Y Ga _Z N (0 <x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ z <1) layer is formed by N doping. The method of claim 15, The _{In X Al Y Ga Z N (} 0 <x≤1, 0≤y≤1, 0≤z <1) layer is undoped and doped In _X Al _Y Ga _Z N layer In _X Al _Y Ga _Z N A low resistance light emitting diode, which is formed by N delta doping so that layers are alternately stacked. The method according to any one of claims 4 to 8, The N-electrode is a low resistance light emitting diode, characterized in that formed in the cross shape.

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