KR20070025994A - A chip verifying and testing module and connecting apparatus for the same - Google Patents

Abstract

A chip verifying and testing module and a connecting device for the same are provided to test a chip with disposing the chip in the module and to easily connect the chip verifying and testing module with the inside of a computer by installing the chip verifying and testing module on the front side of the computer body. A chip verifying and testing module includes a first target board(41) having first connectors(43) and an interface board(60) comprising second connectors(44) coupled to the first connectors of the first target board, third connectors(45) coupled with a computer, and an interface unit connected between the second and third connectors to interface signals transmitted among the second and third connectors. The target board has a chip(47) coupled with the first connectors.

Description

Chip verifying and testing module and connecting apparatus for the same}

1 shows a schematic structure of a general computer main body.

2 illustrates a configuration of a chip verification and test module according to an embodiment of the present invention.

FIG. 3 shows an appearance of the package device of FIG. 2.

FIG. 4 shows the structure of a computer body on which the chip verification and test modules of FIG. 3 are mounted.

FIG. 5 is a diagram illustrating an embodiment of a connection board for connection with FIG. 4.

Figure 6 illustrates an embodiment of a structure for installing a plurality of chip verification and test modules outside the computer body and connected to the computer in accordance with the present invention.

Figure 7 shows an embodiment of a connection device for installing a plurality of chip verification and test modules outside the computer main body and connected to the computer in accordance with the present invention.

8 shows a configuration according to a preferred embodiment of the backplane of the connection device of FIG.

9A illustrates another embodiment of a connection device for installing a plurality of chip verification and test modules outside the computer main body and connecting the computer according to the present invention.

Figure 9b illustrates another embodiment of a connection device for installing a plurality of chip verification and test modules outside the computer main body and connecting to the computer in accordance with the present invention.

10 shows a schematic structure of a general notebook computer.

Figure 11 illustrates an embodiment of a chip verify and test module for connecting with a notebook computer in accordance with the present invention.

12 illustrates an embodiment of a connection board for connecting a chip verification and test module with a notebook computer in accordance with the present invention.

The present invention relates to a chip verification and test module. In particular, when the chip and the peripheral circuit of the chip is simple, the chip is mounted inside the module to perform the chip design verification and test as well as the chip and the chip peripheral. If the circuit is relatively large, it can be connected to an external board on which it is implemented to perform chip design verification and test, and to easily connect with the inside of the computer main body. It is about.

In general, a computer ROM includes a CD ROM drive, a floppy disk drive, a hard disk drive, a power button, and a reset button at a front side thereof, and a rear side of the computer body includes various slots including a PCI slot of a main board inside the computer body. Function boards are mounted and connectors are connected to external devices such as an external monitor, keyboard, and mouse.

1 shows a schematic structure of a general computer main body. The main body 1 includes a cover 10 and a CD ROM drive in the front portion, a portion for mounting a hard disk 12, and a portion for mounting a floppy disk drive 14. , The power button 16, the reset button 18, and the like, and the rear port slot ports 28, and the like.

The main board 2 includes a CPU slot 20, memory slots 22, PCI slots 24, PCI express slots 26, and the like.

In the conventional computer main body 1, the boards are mounted in the PCI slots 24 and the PCI Express slots 26 of the main board 2. If the boards mounted in the slots are abnormal, In case of repair, the cover 10 of the main body 1 needs to be opened, causing inconvenience to the user.

In addition, when connecting with external devices, it is impossible to arrange a large number of connectors because there is insufficient space at the portion where the slot ports 28 located at the rear of the conventional computer body are mounted. In particular, computer-based verification and test devices require the connection of a large number of input and output terminals. In this case, placing a connector with a large number of input and output terminals on the rear side may expand the input and output terminals due to space limitations. There was this difficult issue.

In addition, in the case of computer-based verification and test devices, it is necessary to easily connect or disconnect external devices. In the case of the conventional verification and test devices, connectors are disposed at the rear of the computer main body. Due to this, there was a problem that it is not easy in operability of such an operation.

Of course, having connectors for connecting to an external device in the rear of the computer main body is a matter of space and aesthetics, it is preferable to mount the connectors on the rear side, in general, the monitor connected to the computer main body through the connector of the rear, Since a keyboard, a mouse, and the like are devices that must always be used to handle a computer, the keyboard and the mouse should be connected to the main body, so it is preferable to mount the rear panel.

However, in the case of devices for verifying and testing the operation of an external designed chip or manufactured chip based on a computer, it is necessary to connect an external chip to the computer main body. By the way, the conventional computer-based verification and test device has a problem that the configuration is complicated because a separate module for connecting to the external chip on the outside of the main body is configured.

The object of the present invention is not only to mount the chip inside the module when the chip and the peripheral circuit of the chip is simple to perform the verification and test for the chip, but also to implement this when the chip and the peripheral circuit of the chip is relatively large. The present invention provides a chip verification and test module that can be connected to an external board to perform chip design verification and test, and can be easily connected to the inside of the computer main body.

Another object of the present invention is to provide a connection device that enables not only the chip verification and test module to be easily mounted but also increases the number of connectable chip verification and test modules.

The chip verification and test module of the present invention for achieving the above object is a first target board having first connectors, and second connectors connected to the first connectors of the first target board, connected to the computer And an interface board connected between the second connectors and the third connector, the interface unit having an interface for interfacing signals transmitted between the second connectors and the third connector. It is characterized by.

The first target board may further include a chip connected to the first connectors.

A second target further comprising fourth connectors connected with the first connectors, the module having fifth connectors connected with the fourth connectors, and sixth connectors connected with the fifth connectors The board is further provided, and the sixth connectors are connected to an external device.

The interface board further includes fourth connectors connected with the second connectors, the module includes fifth connectors connected with the fourth connectors, and sixth connectors connected with the fifth connectors. And a second target board, wherein the sixth connectors are connected to an external device.

The second target board is connected to the fifth connectors and the sixth connectors, and after converting signals transmitted through the fifth connectors into a signal that can be recognized by the external devices, the sixth connectors It further comprises a circuit element for transmitting to.

In addition, the first target board further includes a buffer means connected to the first connectors, the first target board is connected to the buffer means, and additionally fourth connectors for connection with external devices. And the buffer means buffers signals transmitted between the first connectors and the fourth connectors.

The first target board further includes fourth connectors connected with the first connectors, the module includes fifth connectors connected with the fourth connectors, and a sixth connector connected with the fifth connectors. And a second target board including the second target board, wherein the sixth connectors are connected to an external device, wherein the second target board is connected to the fifth connectors and the sixth connectors, And a circuit element for converting signals transmitted through the fifth connectors into signals that can be recognized by the external devices and transmitting the signals to the sixth connectors.

Another type of module for achieving the above object is a first board having first connectors for connecting with external devices, a second connector for connecting with a computer, and the first connectors and the second connector. And a second board connected to each other and having a signal processing unit for processing a signal transmitted between the first connectors and the second connector, wherein the second board is mounted on a front or side portion of the computer.

The module further includes a connection cable for connecting the second connector and the computer, and the module further includes a third board including a third connector connected to the second connector. And connecting the connection cable.

The signal processor may process the received audio and / or video signal and transmit the received audio and / or video signal to the second connector, or process and transmit the audio and / or video signal transmitted through the first connectors to the second connector. The first board further includes a receiver for receiving a remote control signal and transmitting the signal to the signal processor.

Another aspect of the present invention provides a module having a board having a first connector for connecting with a computer and a data storage unit for storing a signal transmitted through the first connector. It is characterized in that it can be mounted to the portion or side.

The module further includes a connection cable for connecting the first connector and the computer, and the module further includes a second board having a second connector connected to the first connector. And connecting the connection cable.

The data storage unit includes a plurality of DRAMs for storing a signal input through the first connector and outputting a stored signal through the first connector. The board may be configured to maintain data stored in the plurality of DRAMs. In order to supply the power required for the plurality of DRAMs characterized in that it further comprises a power supply connector.

A connecting device for the chip verification and test module of the present invention for achieving the above another object is a backplane equipped with a first connector and the predetermined number of second connectors commonly connected to the first connector, and the predetermined number of the backplane At least one housing having an upper board and a lower board having a predetermined number of second guides provided to face each other to facilitate coupling to the number of second connectors is provided.

The backplane further includes a predetermined number of power supply connectors to which external power sources having various voltage levels are commonly supplied, and a hole-array is formed on a surface of the housing, and the housing is a toroidal type. It characterized in that the cylindrical structure, characterized in that the plurality of housings are inserted into the case of the donut cylindrical structure when the housing is composed of a plurality.

Hereinafter, with reference to the accompanying drawings will be described the chip verification and test module of the present invention and a connection device for the same.

2 and 3 illustrate a configuration of a target chip verification and test module according to an embodiment of the present invention, wherein the chip verification and test module 30 is a lower board 40 positioned on a lower layer and an upper layer positioned on an upper layer. It consists of a board 50, an interface board 60, and a power supply device 72, and is packaged through a package device 74.

The target lower board 40 includes a board 41, a front plate 42 fixed to the front of the board 41, first connectors 43 located on the front plate 42, and a side of the board 41. The target chip (or target) located at the center of the second connectors 44, the third connectors 45 located at the rear of the board 41, the first power connector 46, and the board 41. A test socket equipped with a chip) 47. Of course, the target lower board 40 may further include a peripheral circuit unit (not shown) for supporting the operation of the target chip 55 in addition to the target chip 55.

The target upper board 50 includes a board 51, a front plate 52 fixed to the front surface of the board 51, fourth connectors 53 positioned on the front plate 52, and a lower board 40. The fifth connector 54 positioned on the side of the board 51 to be coupled to the second connector 44 and the peripheral circuit portion 55 of the target chip 55 positioned in the center of the board 51 are provided. In this case, the target upper board 50 expands the size of the board 51, and may further include a target chip in addition to the peripheral circuit part 55, thereby enabling mounting of a relatively large target chip and peripheral circuit part. .

The interface board 60 may include a board 61, an interface 62 positioned at the center of the board 61, a backplane 63 fixed to the rear of the board 61, and an interface located at the backplane 63. Board connector (64), seventh connector (65), DC input power connector (66), AC input power connector (67), DC power jack (68), the third connector (45) of the lower board (40) and An eighth connector 69, a second power connector 70, and a third power connector 71 located on the board 61 are provided to be coupled to each other. The interface unit 62 includes an interface controller 62-1, a large memory 62-2, and other peripheral circuits (not shown). However, in some cases, the first power connector 46 and the second power connector 70 are removed when the extra pins of the third connectors 45 and the eighth connectors 69 are used as power supply pins. The DC input power connector 66 may be divided into a portion for directly receiving power from a DC power supply of the computer main body and a portion for receiving power from an external source.

In this case, the interface board 60 may be positioned on the board 61 by arranging the seventh connector 65, the DC input power connector 66, the DC power jack 68, and the AC input power connector 67 as necessary. The back plate 63 may be removed.

Hereinafter, the function and operation of each component will be described.

The target lower board 40 transmits input / output signals of the interface board 60 and the chip 47 so that chip verification and test operations can be performed. In addition, if necessary, the first signal 43 of the target lower board 40 may be converted into a signal obtained by converting output signals of the chip 47 into monitoring signals through the chip peripheral circuit or final output signals directly output from the chip 47. ) To monitor the operating state of the chip through an external monitoring device connected to the first connector 43 protruding from the front plate 42, or to control signals of the interface board 60. By transmitting to the connector 43 to control the operation of the external control / measuring device connected to the target lower board 40, or output signals of the chip 47 through the second connector 44 Transfer to board 50.

Accordingly, the first connectors 43 located on the front plate 42 allow external control / measuring devices or monitoring devices to be connected, and the second connectors 44 are formed on the target upper board 50. The DC power is applied to the 5 connector 54 while simultaneously transmitting the output signals of the interface board 60 or the output signals of the chip 47, and the third connectors 45 are output signals of the chip 47. Signals from external control / measuring devices input through the first or second connectors 43 are transferred to the eighth connector 69 of the interface board 60 and the eighth connector 69 of the interface board 60. The signals of the interface board 60, which are input through the, are distributed to the chip 47, the first connectors 43, and the second connectors 44, and the first power connector 46 is connected to the interface board 60. DC power is applied from the second power connector 70 of 60 to allow DC power to be applied to the chip 47 and the second connectors 44.

The target upper board 50 converts the output signals of the chip 47 into monitoring signals and transmits them to an external monitoring device connected to the fourth connectors 53 of the target upper board 50 to operate the chip. The status can be monitored through an external monitoring device, or control signals of the interface board 60 can be transmitted to an external control / measuring device connected to the target upper board 50 to control the operation of the control / measuring device. Make sure

Accordingly, the fourth connectors 53 positioned on the front plate 52 allow external control / measuring devices or monitoring devices to be connected, and the fifth connectors 54 are formed on the target lower board 40. Output signals of the chip 47 and the DC power transmitted through the two connectors 44 are transmitted to the peripheral circuitry 55, and the interface is transmitted through the second connectors 44 of the target lower board 40. Control signals of the board 60 may be transmitted to the fourth connectors 53. The peripheral circuit unit 55 generates monitoring signals in response to the output signals of the chip 47 and transmits them to the fourth connector 53.

The interface board 60 performs signal interfacing between the chip 47 and the computer so as to perform verification and test operations of the chip. At this time, the interface board 60 performs an operation according to the storage means and the interface means of Korean Patent Application No. 2000-42575.

Accordingly, the interface unit 62 transmits the signal transmitted from the main board 2 to the chip 47, and transmits the signal transmitted from the chip 47 to the main board 2 to perform the verification and test operations of the chip. Perform. The interface board connection connector 64 electrically connects the interface board 60 and the backplane 63, and the seventh connector 65 allows the interface board 60 to have a slot 24 on the main board 2 of the computer body. , Or signals connected to the connection board 80 mounted in the slots 24 and 26 so that the signals of the interface 62 are transmitted to the main board 2 and transmitted from the main board 2. Are connected to the eighth connectors 69 through the interface unit 62, and the DC input power connector 66 is the same cable as the power supply of the computer main body or the DC input power connector 66. According to the shape and the number of pins to be connected through a separate cable, the DC power supply of the power supply (power supply) (power supply) (power supply) to be supplied to the interface board 60, the target upper and lower boards (40, 50). The DC input power jack 68 allows the chip verification and test module 30 to receive DC power from an external power adapter when the chip verification and test module 30 is used outside of the computer body, and the eighth connector 69 is provided with an interface 62 or an interface. Signals transmitted from the board connection connector 64 are transmitted to the third connectors 45 of the target lower board 40, and signals input from the third connectors 45 of the target lower board 40 are interfaced. The second power connector 70 is connected to the interface board connection connector 64 through the unit 62, and the second power connector 70 is a DC input power connector 66 or a DC input power jack 68 or a DC supplied from the battery 71. Power is applied to the first power connector 46 of the target lower board 40, and the third power connector 71 is supplied with DC power through the DC input power connector 66 or the DC input power jack 68. DC power is distributed through a charging circuit (not shown). When the DC power supply is cut off via the DC input power connector 66 or the DC input power jack 68, the DC power of the battery 72 is discharged through a discharge circuit (not shown). It is supplied to the interface board 60, the target upper and lower boards 40 and 50.

In addition, the chip verification and test module 30 includes an AC input power connector 67 for receiving external AC power to the rear panel 63 and a DC output power connector 66 for outputting at least one DC power. And a power supply element (not shown) and a board (not shown) mounted thereon for producing a DC voltage output from the DC output power connector 66 in place of the interface board 60 and the lower board 40. If necessary, the chip verification and test module 30 may be used as a DC power supply rather than a chip design verification and test purpose. That is, the chip verification and test module 30 receives external AC power and is required by the chip verification and test module 30, that is, the target lower board 40, the target upper board 50, and the interface board 60. It is possible to generate a DC voltage having various voltage levels.

The interface unit 62 of the interface board 60 includes a large memory 62-2 and a large memory 62-2 for storing input and output files such as a test vector for verifying and testing the chip and the operation of the chip. ), A chip 47, and an interface controller 62-1 for controlling signal transmission between the computer.

If necessary, the large-capacity memories 62-2 may be provided not only at the top of the board 61 but also at the bottom thereof, thereby storing input / output signals such as test vectors having a larger capacity, thereby allowing a signal between the interface unit 62 and the computer. By reducing the interfacing load, the computer can be used more efficiently and can process huge amounts of I / O data at the same time during chip verification and test operation of chip verification and test modules.

In addition, the large-capacity memories 62-2 can access a large amount of memory at high speed, such as a simulation stage, a circuit synthesis stage, an FPGA compile stage, and a chip P & R (Placement and Routing) stage. For ram-disk (or solid state disk) applications where the chip verification and test module does not perform chip verification and test operations, such as during design stages before and after chip verification that requires access. To be used. At this time, the lower board 40 and the upper board 50 can be used for the purpose of expanding the memory capacity.

As the memory used for the chip verification and test module 30 uses a large capacity memory, a DRAM (D-RAM), a flash RAM (Flash-RAM), and a phase conversion RAM (P-RAM) are used.

In particular, in the case of using the D-RAM as a large-capacity memory, when the chip verification and test module 30 in which the data is stored is separated from the original computer to move to another computer, When the situation is not normally supplied, the interface control unit 62-1 detects the level of the DC power input, switches the mass memory 62-2 to the self-refresh mode, and provides power. The device 72 is switched from a charged state to a discharged state to receive DC power from the power supply device 72. When the chip verification and test module 30 is installed in another computer and starts to receive external DC power normally, the interface controller 62-1 switches the self-refresh operation mode of the large-capacity memories 62-2. It releases and returns to a normal mode, and returns the power supply device 72 to a charging state.

In the case where the chip verification and test module 30 is mounted on the front of the main body of a computer as in a general hard disk (HDD) and used for a ram-disk, the chip verification and test module 30 is not only mounted but also operated. It is preferably used similarly to a hard disk (HDD).

That is, in a general RAM disk, it is a general form to be mounted in the slot 24 on the motherboard 2 of the main body of the computer. In particular, when the power of the main body of the computer is turned off, all of the contents of the ram disk are completely shut off. The operation involved evacuating data to a specific area on the hard disk designated by the user, which is boring for the user compared to the time required for normal shut-down due to the slow access time of the hard disk. It takes time to feel it.

This behavior is similar to the slow access time of the hard disk even when the computer is booted, even when loading files, folders, or the entire hard disk onto a ram disk at a user-specified location. Due to the time it takes some time was inevitable.

However, in order to eliminate such inconvenience in use, the verification and test module 30 may be mounted on the front of the computer main body and used similarly to a hard disk for ram-disk purposes. In order to connect the first DC power jack (not shown), DC power jack 68 of the rear panel 63 to receive DC power from an external power adapter (not shown) on the connection board (80) A second DC power jack (not shown), a second DC power jack (not shown) for connecting the second DC power jack on the connection board 80 and the DC power jack 68 of the rear panel 63; The first DC power jack and the second DC power jack on the connection board 80 are connected in a PCB pattern on the connection board 80.

In this state, the verification and test module 30 operating as the ram disk regardless of the power supply state of the computer main body has a stable and quick preparation operation.

In other words, when the main body is in the operating state of Booting, since the verification and test module 30 operating as the ram disk is already powered on, the data is retained before the main unit is turned off. There is no need for a separate data loading operation from the hard disk to the ram disk of the verification and test module 30, and even if the main body is turned off, the hard disk from the ram disk of the verification and test module 30 is not required. There is no need to evacuate data to a specific location on the disk, reducing unnecessary waste of time with the RAM disk.

However, even when a power failure occurs, the verification and test module 30 used as a ram disk requires a power supply device 72 because data must not be lost, and even when such a case occurs, the verification and test module ( 30) A stable data holding operation is performed by using a power supply device 72 installed therein and a charge / discharge circuit (not shown) on the interface board 61 when using the RAM disk.

In this case, the power supply device 72 may be implemented as a rechargeable battery capable of charging and discharging a predetermined power or a fuel cell capable of generating a predetermined power.

However, data loss cannot be avoided when battery power is consumed due to a long power outage so that the battery can be arrayed using the bottom surface of the ample space of the connection module. It is possible to increase the capacity of the battery to the maximum by arranging, and even when using a fuel cell, it is easy to secure a space for mounting a container for storing a liquid fuel such as methanol used as fuel of the fuel cell.

However, when the AC main power connected to the computer main body is in a normal shut-down state for a long time, the power supply voltage of the power supply device 72 of the verification and test module 30 becomes lower than a predetermined level. The control unit 62-1 on the interface board operating with the minimum power consumption is in the Shut-down state through the seventh connector 65, the connection cable (not shown), and the connection board 80 of the rear panel 63. By interrupting the main body 2 of the computer main body, the computer main body can be turned on (Booting) to save data from the RAM disk of the verification and test module 30 to a specific position on a predetermined hard disk.

Therefore, based on the stable data holding operation of the verification and test module 30 used as the RAM disk, the computer main body is turned ON when the main disk (C: \) installed with the OS is used instead of the disk serving as an auxiliary role. It is possible to drastically reduce the booting time and shut-down time required during / OFF.

The chip verification and test module of FIG. 2 is a target chip and its peripheral circuit portion is relatively large, the target upper board 50 as well as the target lower board 40, if the sufficient placement is not possible only in the target lower board 40. And the input / output signal of the target lower board 40 to the target upper board 50 through the combination of the second connector 44 of the target lower board 40 and the fourth connector 54 of the upper board 50. The DC power source will be connected.

In the case of utilizing the upper board 50, the length of the upper board 51 can be extended in the direction of the interface board 60, so that the target upper board 50 has a relatively large target chip and its peripheral circuit elements. It is possible to mount. At this time, the second connectors 44 of the target lower board 40 and the fifth connectors 54 of the target upper board, which are to be supplied with the input / output signal and the power, are connected to the interface controller 62 of the interface board 60. Arranged between the eighth connectors 69 and directly connected to the target upper board 51 on the interface board 60, it is also possible to connect the input and output signals and DC power without going through the target lower board 41. This structure has a shorter input / output signal wiring structure in case of connecting through the second connectors 44 of the lower board 40 and the fifth connectors 54 of the upper board on the lower board 40. In addition, since the input / output signal does not have to pass through the third connectors 45 and the eighth connectors 69, the contact resistance is reduced when the connector is connected, thereby driving the target chip 55 with a faster interface. You can do it.

In addition, when the number of signal lines connected from the lower board 40 to the upper board 50 is large, the connection of only the second connectors 44 and the fifth connectors 54 may not be sufficient. Signal between the upper and lower boards 40 and 50 by connecting the first connectors 43 used to connect an external target board or a control / measuring device to the fourth connectors 53 by using It is possible to connect the lines by extension.

At this time, the means for connecting between the upper and lower boards 40 and 50 may be a cable, and for higher speed operation, the first connectors 43 and the fourth connectors are provided on separate vertical boards (not shown). Each of the connectors 53 (not shown) corresponding to the field 53 may be connected to form a connection board combining the 'c' shape.

On the other hand, if the target chip and its peripheral circuit are relatively simple and can be sufficiently arranged in the lower board 41, only the lower board on which the chip or the chip is mounted and the test socket on which the chip is mounted and the elements of the peripheral circuit are separately manufactured. It is possible to connect to the interface board 60 to perform chip verification and test. In this case, the condition is not a condition for connecting a separate target board existing by a cable, but a chip through the connection between the eighth connector 69 of the interface board 60 and the third connector 45 of the lower board 40. Since the input / output signal can be connected to the 47, the interface board 60 can operate the chip 47 at a higher speed.

In addition, when the size of the target chip and its peripheral circuit is large and mounted on an external target board (not shown), the lower board 40 may be a static electricity and overcurrent protection circuit, a PMU (Power Management Unit), an ADC instead of the chip. (Analog to Digital Converter), DAC (Digital to Analog Converter), matrix switch circuit, etc. to provide a buffer means for the interface, and through the buffer means the first connector 43 and the third connector (45) By buffering the signal between), you can interface the signals transmitted between the external target board and the interface means.

In this case, the lower board 40 may be connected to the external target board using a separate cable or may be directly coupled to the external target board through the first connectors 43.

In this case, the upper board 50 processes any output signal of the external target board transmitted to the inside of the computer through the interface board 60, and the result is again passed through the lower board 40 through the interface board 60. The output signal for final monitoring may be generated by the upper board 50. Alternatively, the output of the external target board input through the first connectors 43 may be output to the second connectors 44 and the second connectors 44. It is also possible to receive the direct output from the lower board 40 via the connection of the five connectors 54 and generate the final output signal for monitoring.

Meanwhile, the chip verification and test device module of FIG. 2 not only performs chip verification and test operation, but also successfully completes the chip verification and test operation, together with the embedded target boards 40 and 50, and the CD of the computer main body. It can be mounted as a ROM drive or hard disk drive and used directly as a finished product.

For example, in a product installed in the PCI slot as a PCI card type such as a digital TV receiving card, a separate cable accessory type because parts such as a remote control receiver, a video signal input terminal, and various control switches cannot be located at the front of the computer. It could not only be provided through the PCI connection port on the back side, but also the convenience of operation was not good.

However, when considering the same product using the module of the present invention, the above-described remote control receiver and video signal arranged in the space where the first connectors 43 and the fourth connectors 53 of the front panel 52 are arranged. Front terminals of input terminals, various control switches, and the like can be easily disposed to increase the convenience of operation.

In addition, in order to secure the mobility of the chip verification and test module 30, the chip verification and test module 30 is connected to the computer main body and the components 65, 66, 67, 68 located on the backplane 63. A module detachable back plane (not shown) corresponding to the above may be further provided, and a module detachable back plane may be easily detached from the front of the computer through the module detachable back plane. Of course, even in the case where it is desirable to be wired or arranged through the back side as usual, such as an antenna line and a tuner, in the case of using the chip verification and test module of the present invention, a tuner unit (not shown) is mounted directly on the connection board and output thereof. Signal board using the first connector 82 of the connection board 80, the connection cable (not shown), the seventh connector 65 of the rear panel 63, the interface board 60, the target chip This problem can be easily solved by securing a wiring structure for directly connecting between the upper and lower boards 40 and 50 implemented. In the case where the tutor unit is disposed on the target lower board 40 or the upper board 50, the antenna line is connected to the rear panel 63 of the chip verification and test module 30 through the PCI port on the rear of the computer. It is also possible to achieve the above object by arranging a separate connector (not shown) to connect the antenna wire pre-wired on the interface board 60 to the target board on which the tuner is located.

The package device 74 of FIG. 3 covers the entire surface of the chip verify and test module 30 to protect the chip verify and test module from the external environment.

At this time, the package device 74 is to form the surface of the 'T'-shaped concave-convex shape, so as to facilitate fastening with different target chip verification and test module and heat dissipation inside, and at the same time through-hole An array is formed to allow air flow to double the heat dissipation effect through the holes. Of course, the target lower board 40 and the target upper board 50, the front plate (42, 52), the rear plate 63, the rear plate 63 of the package device 72 is fastened to the purpose of heat dissipation One hole-array can be formed.

Preferably, the package device 74 covers the front surface of the first package device 75 and the interface board 60 to cover the front surfaces of the target lower board 40 and the target upper board 50 as shown in FIG. 3. The target upper board 40 and the target lower board 50 can be easily separated from the interface board 70 by being separated into the second package device 76.

Accordingly, the package device 74 may protect the portion of the interface board 60 that is carefully designed when the target chips 47 and 55 exist inside the connection module 30 and provide a smooth debugging environment at the same time. It has a structure to provide a structure capable of opening and closing only the upper end of the front portion of the 75, thereby easily separating or coupling the target upper board 40 and the target lower board 50 from the interface board 70 To be possible.

Therefore, when the chip verification and test module 30 is mounted on the front of the computer, when it is necessary to debug the lower board 40 or the upper board 50 of the connection module 30, the connection module 30 The first package device 75 along the guides (not shown) fixed to the computer main body at both sides of the entrance of the 'T'-shaped unevenness on the surface of both sides of the package device and the corresponding connection module 30. After opening and closing only the upper end of the front part of the first packaging device 74 at the position reaching the temporary fixing position by protruding toward the front part, the first connectors of the second connection module 30 mounted on the front part are separated. The probes connected to the opposite side of the cable connected to 43 are connected to the probe target position of the upper board 50 or the lower board 40 of the first connection module 30 to be debugged. Module 30 is for design validation or testing purposes A second connection module 30 is connected separately while the smaller and can be used for debugging purposes.

FIG. 4 shows the structure of a computer body on which the chip verification and test modules of FIG. 3 are mounted.

Referring to FIG. 4, the chip verification and test module 30 of FIG. 2 is mounted to a portion where a CD ROM drive or a hard disk is mounted on the front portion 12 of the computer main body 1.

The seventh connector 65 of the chip verification and test module 30 is directly connected to the slots 24 and 26 on the main board 2 through a connecting cable (not shown), or the slot on the main board 2 ( It is connected to the slots 24 and 26 on the main board 2 via the connection board 80 mounted on the 24 and 26.

More specifically, when the seventh connector 65 and the slot 26 use a serial data transmission method such as the PCI Express interface method, the interface board connection connector and the slot 26 are directly connected through a connection cable (not shown). It may be possible, or may be connected through a separate connection board (80). In addition, when using a parallel data transmission method such as the PCI interface method, the connection board 80 is mounted on the slot 24, and the connection board 80 and the seventh connector 65 are connected through a connection cable (not shown). To connect the seventh connector 65 to the slot 24 via the connection board 80.

FIG. 5 is a diagram illustrating an embodiment of the connection board of FIG. 4.

Referring to FIG. 5, the connecting board 80 includes a board 81, a first connector 82, a second connector 83, a bridge element (or a switch element) 84, and a peripheral circuit (not shown). It is configured by. On the board 81, a slot connecting terminal 85 mounted in a slot 24 or 26 on the main board 2, a first connector 82, a second connector 83, a slot connecting terminal 85, and Signal lines (not shown) for connecting the bridge elements 84 are disposed.

The first connector 82 is for connecting with modules mounted inside the computer body, the second connector is for connecting with modules located outside the computer body, and the bridge element 84 is connected to the first connector ( 82), the second connector 83, and the slot connection terminal 85 are used to perform signal flow control, and the slot connection terminal 85 is to be connected to a slot on the main board.

The first connector 82 of the connection board of FIG. 5 is connected to the seventh connector 65 of the chip verification and test module. That is, the first connector 82 of the connection board is provided using a connection cable (not shown) having a connector connected to the first connector 82 on one side and a connector connected to the seventh connector 65 on the other side. ) And the seventh connector 65 of the chip verification and test module.

In the above description, the case where the chip verification and test module of FIG. 2 is mounted on the front side of the computer has been described. However, in some cases, the number of chip verification and test modules used may be increased, and thus, the chip verification and test modules may not all be mounted on the front surface of the computer main body.

Accordingly, a structure for connecting a plurality of chip verification and test modules to the outside of the computer body and then connecting the computer body will be described.

FIG. 6 illustrates an embodiment of a structure for installing a plurality of chip verification and test modules outside the computer main body and connecting the computer according to the present invention.

Referring to FIG. 6, each of the plurality of chip verify and test modules 30 is coupled with a different chip verify and test module 30 using the surface of the package device 70 having a 'T'-shaped concave-convex shape. Accordingly, the plurality of chip verification and test modules 30 may be extended by a required number in up, down, left, and right directions.

Each of the chip verification and test modules 30 is directly connected to the slots 26 on the main board 2 through a connecting cable (not shown) or mounted in the slots 24 or 26 on the main board 2. It is connected to the second connectors 83 of the connection board 80 is connected to the slot (24 or 26) on the main board (2) via the bridge element (or switch element) 84.

7 illustrates another embodiment of a structure for installing a plurality of chip verification and test modules outside of a computer body and connecting to a computer according to the present invention.

Referring to FIG. 7, the connecting device 90 includes a housing 91, an upper plate 92, a lower plate 93, guides 94 symmetrically mounted on the upper plate and the lower plate 92, 93, and a back plane. plane 95, first connectors 96 on back plane 95 disposed to correspond to guides 94, and second connectors 97 disposed on one side of first connectors 96, The third connector 98 disposed to correspond to the guides 94 at the bottom of the first connector, the fourth connector 99 disposed to correspond to the guides 94 at the bottom of the third connector 98, and the fourth connector 98. The connector 99 is composed of an AC power input terminal 100 disposed on one side. In addition, the first connectors 96 and the second connector 97 are connected to each other through a signal line of the backplane 95, and the third connectors 98 are connected to each other through a DC power line. The four connectors 99 and the AC power input terminal 100 are connected to each other through an AC power line.

Hereinafter, the functions of the components constituting the connecting device will be described.

The 86 housing 91 forms a hole-array for the heat dissipation of the upper plate 92 and the lower plate 93 and is used as a means for supporting the guides 94 and the back plane 95. The upper plate 92 may be integrally formed to include the guide 94 to be the upper plate guide 93, and the lower plate 93 may also be the lower plate guide 93 to the integral structure including the guide 94. .

The backplane 95 is used for the connection between the connection board 80 mounted in the slot on the main board 2 and the chip verification and test modules mounted in the connector 90. The first connectors 96, the third connectors 98, and the fourth connectors 99 connected to the backplane 95 are for connection with a chip verification and test module mounted on the connector 90. The first connector 96 is connected to the seventh connector 65 of the chip verification and test module 30, and the third connector 98 is connected to the DC input power connector 66 of the chip verification and test module 30. The fourth connector 99 is connected to the AC input power connector 67 of the chip verification and test module 30, respectively. The second connector 97 is for direct connection to the slot 26 on the main board or for connection with the second connector 83 of the connection board 80. Guides 94 allow chip verification and test modules 30 mounted on connecting device 90 to first, third and fourth connectors 96, 98, and 98 of backplane 95, respectively. It is intended to be connected.

In FIG. 7, the first connectors 96 are connected to the second connectors 83 of the connection board 80 mounted in the slots on the main board 2 through a connection cable (not shown), thereby connecting the connection board 80. Is connected to the slot 24 or 26 on the main board 2 or individually to each slot 26 on the main board 2 without passing through the connecting board 80. In addition, when the connection is performed using the second connector 97 that is commonly connected to the first connectors 96, the connection cable may be directly connected to the slot 26 on the main board 2 through a connection cable (not shown). Or it is connected to the slot (24 or 26) on the motherboard (2) via the connection board (80).

The connecting device 90 is connected to each of the chip verification and test modules 30 by the first connector 96, the third connector 98, and the fourth connector 99. To be connected to slots 24 and 26.

The connecting device 90 of FIG. 7 may form a hole-array for heat dissipation, like the package device 74.

8 shows a configuration according to a preferred embodiment of the backplane of the connection device of FIG.

Referring to FIG. 8, the backplane 95 includes first connectors 96, third connectors 98, and fourth connectors disposed on the backplane 95 to correspond to the guides 94. 99 and the second connector 97 disposed on one side of the first connectors 96 and the AC power input terminal 100 disposed on one side of the fourth connector 99.

The first connectors 96 and the second connector 97 are commonly connected by the signal lines SL, and the third connectors 98 are connected to each other through the DC power line DC PL. The four connectors 99 and the AC power input terminal 100 are connected to each other through an AC power line AC PL.

The chip verification and test module of the present invention has a different voltage level of an operating power source according to the type of the chip and its peripheral circuits in addition to the DC voltage basically required by the interface board 60. Accordingly, the backplane 95 generates operating powers having various voltage levels through a power supply element (not shown), supplies the power to the power lines DC PL, and verifies a chip mounted through the guides 94. Each of the DC input power connectors 66 of the test modules 30 requires a corresponding chip verification and test module among DC input powers of the third connector 98 supplied through the power lines DC PL. The DC input power source is selected to be provided to the corresponding chip verification and test module.

Also, when the chip verify and test module 30 as described above instead of a power supply element (not shown) operates as a DC power supply, the plurality of chip verify and test modules 30 can generate a DC power source. Make sure In the case where the supply capacity of the specific DC power supply of the chip verification and test modules 30 is insufficient, the number of the chip verification and test modules 30 generating the corresponding DC power supply may be increased to increase the power supply capability.

FIG. 9A illustrates another embodiment of a structure for installing a plurality of chip verification and test modules outside of a computer body and connecting to a computer according to the present invention.

The connecting device 110 of FIG. 9A includes guides 94 and a back plane symmetrically mounted on the housing 91, the upper plate 92, the lower plate 93, the upper plate and the lower plate 92, 93 as shown in FIG. back plane) 95, having a toroidal cylindrical structure, and having an upper surface open.

The pair of guides 94 are disposed symmetrically on the inner and outer plates of the donut-shaped cylinder, the backplane 95 is disposed on the lower surface of the donut-shaped cylinder, and the first, third and fourth connectors ( 96, 98, and 99 are arranged in line from the inner side to the outer side of the donut-shaped cylinder on the backplane 95 in correspondence with the guides 94. In addition, the second connector 97 and the AC power input terminal 100 for connection with the computer main body are arranged (not shown) to protrude outward for connection of a cable (not shown) and a power cable (not shown). .

Accordingly, the chip verification and test device 30 is mounted to the connection device 110 through a pair of guides 94, so that the first, third, and fourth connectors 96, 98, and 99 of the backplane 95 are connected. ), And may be connected to the slots 24 and 26 of the main board 2.

In addition, the connection device 110 may be configured such that the first connectors 43 of the plurality of chip verification and test modules 30 mounted on the connection device 110 are mounted on the external target board 120 on which the target chip 47 is mounted. Allows direct connection with connectors (not shown) located on the bottom surface or through connection cables.

Accordingly, the connection device 110 may provide a useful environment for verifying or testing a large-capacity target chip that requires the connection of many input / output signals through a plurality of chip verification and test modules 30 mounted in the device.

In particular, when the first connectors 43 of the plurality of chip verification and test modules 30 are directly coupled with the connectors of the external target board 120, the signal delay and the response speed due to the connection cable may be prevented. This allows for faster chip verification and test environments. In addition, the donut-shaped cylindrical structure of the connecting device 110 is located at the center of the target board 120 by allowing the first connectors 43 for connecting the external target board 120 to be naturally arranged in a circular shape on the top surface thereof. It is advantageous to make each pin wiring structure between the target chip 47 and the first connectors 43 have the same physical length.

The connecting device 110 of FIG. 9A forms a hole-array on the surface, and attaches a large-capacity cooling fan 112 to the inner circular space to verify and test each chip from the outside of the connecting device 110. Through the module through the cooling fan 112 of the central air flow to be exhausted downward or to generate a flow of air in the opposite direction to thereby double the heat dissipation effect.

In addition, as shown in FIG. 9B, the connection device of FIG. 9A is divided into a plurality of housings 131 corresponding to each of the plurality of chip verification and test modules, and each of the plurality of housings 131 is different from each other. It may be coupled to or separated from the housing 131.

Of course, each of the plurality of housings 131 at this time is formed in the form of a 'T'-shaped concave-convex to facilitate fastening with different housings and heat dissipation inside, as well as hole-array penetrating the surface It forms a hole-array to increase the heat dissipation effect.

The above-described embodiment describes a case in which the chip verification and test module of FIG. 2 and the board of FIG. 5 are mounted on a main body of a personal computer. However, the chip verification and test module of FIG. 2 and the board of FIG. 5 may be mounted in a notebook computer. In this case, the module configuration of FIG. 2 and the board of FIG. 5 should be changed according to the structure of the notebook computer.

10A and 10B show a schematic structure of the side of a notebook computer. 10C is a schematic structure of the rear portion of a notebook computer.

10A, side portion 140-1 of notebook computer 140 includes modem port 141, network (Ethernet) port 142, CD ROM drive 143, drive eject button 144, and security slot 146. ), A CD-ROM IDE connector (147), and a PCI Express bus connector (148).

10B is a side view 140-2 of another notebook computer, showing the PC card eject button 149, the PC card slot 150, the PCI ExpressCard slot 151, the PCI Express bus connector 152, and the high speed USB port 153. ), A video output (OUTPUT) port 154, a monitor port 155, and a DC power port 156.

As shown in FIG. 10A, unlike the personal computer of FIG. 1, the notebook computer has a CD ROM drive 143 disposed on the side thereof, and the CD ROM drive 143 is connected to the CD ROM IDE connector 147 to transmit and receive data. .

The PCI Express slot 151 is equipped with various interface boards (not shown), the interface board (not shown) is connected to the PCI Express card host connector 152, and the PCI Express card host connector 152 is the main board (not shown) It is connected to the PCI Express bus (not shown). In addition, a PCI Express bus connector (not shown) is also connected to the PCI Express bus (not shown) on the main board (not shown). Data is transmitted and received between a CPU (not shown) and other functional blocks (not shown) on a main board (not shown) through a PCI Express bus (not shown). 10-C, the back portion of the notebook computer includes a battery 157.

FIG. 11 illustrates an embodiment of a chip verify and test module for application to the notebook computer shown in FIG.

The connection module 160 shown in FIG. 11 includes the interface board 61 from which the backplane 63 is removed, and the seventh connector 65 of the backplane 63 of the interface board 61 of FIG. DC input power source 66 is placed on board 61.

The connection module 160 shown in FIG. 11 removes the CD ROM drive 143 that was mounted in the notebook computer of FIG. 10 and is mounted where the CD ROM drive 143 is connected. At this time, the seventh connector 65 of the connection module 160 shown in FIG. 11 and the PCI Express bus connector 148 of FIG. 10 are connected. As a result, high-speed data transmission becomes possible. Of course, the seventh connector 65 is configured to be connected to the seventh connector 65 of the module 160 and the CD ROM IDE connector 147 of FIG. 10 to transmit and receive data through the CD ROM IDE connector 147. In this case, however, the data transmission speed is slower than in the case of transmitting and receiving data through the PCI Express bus connector 148. In addition, a DC power connector (not shown) corresponding to the DC input power connector 66 may be installed on the main board 143.

And, the drive size of a CD ROM for a notebook computer is smaller than that of a CD ROM drive for a normal computer. Therefore, only the connection board 160 shown in Fig. 11 is mounted to the CD ROM drive 146, and the remaining upper board 51 and the lower board 41 are external to the CD ROM drive 146, i.e., a notebook computer, if necessary. It is connected to the connection board 160 from the outside. The connection between the upper board 51 and the lower board 41 which are separately present in the outside is the same as the connection method described with reference to FIG.

In addition, the connection of the connection module 160 and the external device is made by the eighth connector 69 performing a function of the first connector 43 for external connection of the existing lower board 41.

Accordingly, portability is maintained by the connection module 160 using the connection portion of the existing CD ROM drive 143, and the connection with the external device is made through the eighth connector 69 to process the input / output signal for the external interface. Support is also available.

If the connection module 160 is mounted on the notebook computer for the purpose of using a RAM disk, the DC input power output from the second power connector 70 of the connection module 160 and the battery 155 of the notebook computer 140 may be used. A connector (not shown) can be connected. Alternatively, the DC input power connector 66 may be connected to a DC power connector (not shown) on the main board (not shown) so that the connection module 160 may receive power. When power is input in this way, the connection module 160 can be used without additional power input from the outside. Thus, when the power of the battery 155 of the notebook computer 140 remains to the extent that the operation of the connection module 160 is possible, the notebook module 140 may be mounted on the connection module 160 regardless of whether the notebook computer is turned on or off. It is possible to keep data in memories. That is, as the data stored in the hard disk of the personal computer is maintained regardless of whether the power switch is on or off, the memory of the connection module 160 is a dynamic memory that requires a refresh operation. If power of the battery 155 is being supplied to the connection module 160, data of the memory of the connection module 160 may be maintained.

In addition, the external power supply device 72 is connected to the connection module 160 through the second power connector 70 to continuously supply the battery power, thereby maintaining the data of the connection module 160 while maintaining the connection module 160. It can also be attached to another computer. Therefore, after the power supply device 72 is connected, the connection module 160 may be separated from the notebook computer and connected to another computer, thereby increasing portability.

That is, the connection module 160 is a general computer except for the difference in the structure in which the rear panel is removed from the interface board 60 so that the relevant connector is directly located on the board and the structural difference in which the lower board 41 is connected to each other through a connection cable. This is the same as using RAM disk for. In addition, it is possible to add an expansion RAM disk externally using the eighth connector 69 exposed to the outside. However, for aesthetic reasons, the eighth connector 69 may be removed as necessary.

Figure 12 illustrates an embodiment of a connection board for connecting a chip verification and test module with a notebook computer in accordance with the present invention.

FIG. 12 is a view in which the slot connection terminal 85 is removed from the connection board 81 shown in FIG. 5, and is used to control the signal flow between the first connector 82 and the second connector 83. The 84 may be removed in the short-range signal transmission that can be supported by the PCI Express bus, and in the case of the long-distance signal transmission, it functions as a repeater to support signal transmission with an external device remotely connected to the notebook computer 140.

The connection to the notebook computer utilizes a built-in PCI Express card slot 151 for an external high speed signal interface. Inside the PCI Express card slot 151 is a PCI Express card host connector 152 connected to the main board of the notebook computer, and is connected to the first connector 82 of the connection board 81. The external chip verification and test module 30 is connected to the second connector 83 by using a connection cable (not shown).

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Therefore, the present invention not only enables the chip verification and test module to mount the chip therein to verify and test the chip, but also to be easily connected to the inside of the computer main body.

In addition, the computer main body has a chip verification and test module mounted on the front surface thereof so that the chip verification and test module can be easily connected to the inside of the computer. In addition, the plurality of chip verification and test modules can be connected to the inside of the computer through a connection cable even if the outside of the computer is installed.

Claims (46)

A first target board having first connectors; And Second connectors connected to first connectors of the first target board, a third connector for connecting with a computer, and connected between the second connectors and the third connector, And an interface board including an interface unit for interfacing signals transmitted between the third connectors. The method of claim 1, wherein the first target board is The chip verification and test module further comprises a chip connected with the first connectors. The method of claim 2, wherein the first target board is And a fourth connector connected to the first connectors. The method of claim 3, wherein the module Fifth connectors connected to the fourth connectors; And Further comprising a second target board having sixth connectors connected to the fifth connectors, And the sixth connectors are connected to an external device. The method of claim 2, wherein the interface board And a fourth connector connected to the second connectors. The method of claim 5, wherein the module Fifth connectors connected to the fourth connectors; And And a second target board having sixth connectors connected to the fifth connectors. And the sixth connectors are connected to an external device. The method of claim 4 or 6, wherein the second target board is A circuit element connected to the fifth connectors and the sixth connectors and converting signals transmitted through the fifth connectors into a signal that can be recognized by the external devices, and then transmitting to the sixth connectors. Chip verification and test module, characterized in that further comprising. The method of claim 1, wherein the first target board is And a buffer means connected to the first connectors. The method of claim 8, wherein the first target board is It is connected to the buffer means, and further provided with fourth connectors for connecting to external devices, the buffer means for buffering the signals transmitted between the first connectors and the fourth connectors Chip verification and test module. The method of claim 8, wherein the first target board is And a fourth connector connected to the first connectors. The method of claim 10, wherein the module is Fifth connectors connected to the fourth connectors; And And a second target board having sixth connectors connected to the fifth connectors. And the sixth connectors are connected to an external device. The method of claim 11, wherein the second target board A circuit element connected to the fifth connectors and the sixth connectors and converting signals transmitted through the fifth connectors into a signal that can be recognized by the external devices, and then transmitting to the sixth connectors. Chip verification and test module, characterized in that further comprising. The method of claim 1, wherein the interface unit An interface controller for controlling interface transmission of signals between the second connectors and the third connector; And And a memory for storing information for the operation of the interface controller. The memory of claim 13, wherein the memories are Chip verification and test module, characterized in that one of the DRAM (D-RAM), flash-RAM (Flash-RAM), and phase-conversion RAM (P-RAM). The method of claim 13, wherein the interface board The chip verification and test module, characterized in that it further comprises a first power input connector for receiving an external power. The method of claim 15, wherein the interface board And at least one of a second power input connector and a DC input power jack for receiving DC power from an external source. The method of claim 16, wherein the interface board And a third power input connector for receiving AC power from the outside. The method of claim 16, wherein the chip verification and test module And a power supply element for generating a DC power supply having various voltage levels from the AC power supply. The method of claim 16, wherein the chip verification and test module And a power supply device configured to provide the DC power to the first power input connector. The method of claim 1, wherein the chip verification and test module The chip verification and test module, characterized in that further comprising a package device for packaging the front surface of the first target board and the interface board. The method of claim 20, wherein the package device A first package device for packaging the first target board; And A second package device for packaging the interface board, And the first package device and the second package device may be coupled to or separated from each other. The method of claim 21, wherein the first and second package devices are Chip verification and test module, characterized in that the surface is formed in the irregular shape. 23. The apparatus of claim 22, wherein the first and second package devices are Chip verification and test module, characterized in that the hole-array formed on the surface. The method of claim 4, 6 or 11, wherein the package device A first package device for packaging the first and second target boards; A second package device for packaging the interface board, The chip verification and test module, characterized in that for combining or detaching the first and second package devices. 25. The apparatus of claim 24, wherein the first and second package devices Chip verification and test module, characterized in that the hole-array formed on the surface. First connectors for connecting with external devices, second connectors for connecting with a computer, and connected between the first connectors and the second connector and transmitted between the first connectors and the second connector A board having a signal processing unit for processing a signal to be provided, And a module which can be mounted at a position at which the CD ROM drive of the computer is mounted. 27. The module of claim 26, wherein the module is And a connection cable for connecting the second connector and the computer. The method of claim 26, wherein the signal processing unit A signal generator configured to generate a signal to be transmitted to the first connector or the second connector; And And an interface unit for an interface of signals transmitted between the signal generator and the second connector. The board of claim 28, wherein the board is A first board including the first connectors and the signal generator connected to the first connectors; And And a second board including a third connector connected to the signal generating unit, the second connectors, and the interface unit connected to the third connector and the second connectors. The method of claim 27, wherein the module is And a connection board having a third connector for connecting to the second connector and a slot connection terminal connected to a slot of the computer. And connecting the second connector and the third connector through the connection cable. 27. The module of claim 26, wherein the module is And a connecting board having third connectors for connecting to the external devices and a slot connecting terminal connected to a slot of the computer. A board having a first connector for connecting to the computer and a data storage for storing a signal transmitted through the first connector, the board being mounted at a position where the CD ROM drive of the computer is mounted; The data storage unit And a plurality of semiconductor memory devices for storing a signal input through the first connector and outputting the stored signal through the first connector. 33. The semiconductor memory device of claim 32, wherein the semiconductor memory device is A module comprising one of a DRAM, a flash-RAM, and a P-RAM. 34. The board of claim 33, wherein the board is And a power supply device for supplying power for maintaining data of the plurality of DRAMs. 35. The apparatus of claim 34, wherein the power supply device A module comprising at least one of a rechargeable battery and a fuel cell. 33. The method of claim 32, wherein the module is And a connection cable for connecting the first connector and the computer. 37. The module of claim 36, wherein the module is And a connection board including second connectors for connecting to the first connector and a slot connecting terminal connected to a slot of the computer. And connecting the first connector and the second connector through the connection cable. 33. The method of claim 32, wherein the module is And a connecting board having second connectors for connecting to the external devices and a slot connecting terminal connected to a slot of the computer. The method of claim 37 or 38, wherein the connection board A first power jack for receiving external power and a second power jack for supplying power to the outside; And connecting the second power jack to the power supply connector. 33. The system of claim 32, wherein the board is And a third connector for external connection for reading out the signal stored in the data storage unit. A back plane mounted with a first connector and the predetermined number of second connectors commonly connected to the first connector; And Having at least one housing having a first board and a second board having a predetermined number of second guides provided facing each other to facilitate engagement with a predetermined number of second connectors of the backplane. Characterized in that the connecting device. 42. The method of claim 41 wherein the backplane is And a predetermined number of power supply connectors to which external power sources having various voltage levels are commonly supplied. 42. A connecting device according to claim 41, wherein a hole-array is formed on the surface of the housing. 42. The method of claim 41 wherein the housing is A connecting device, characterized in that the donut-shaped cylindrical structure. 42. The method of claim 41, wherein the housing is composed of a plurality And said plurality of housings are inserted into a case of a toroidal cylindrical structure. 46. The device of claim 44 or 45, wherein the connection device And a cooling fan installed in the inner space of the cylindrical structure.

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